Strobe signal controlling circuit

The present disclosure relates to a semiconductor memory device, and more particularly to a strobe signal controlling circuit.

Generally, a semiconductor memory device employs a strobe signal DQS by using a short pulse signal used to synchronize with an external chip set in order to transmit data during the transmission or the reception of data.

FIG. 1 is a block diagram showing a conventional strobe signal controlling circuit.

As shown in FIG. 1 , according to the conventional strobe signal controlling circuit, an initial write controller generates a signal WT 0 after receiving a pulse signal WTP generated by decoding a write command and synchronizing the pulse signal WTP to a clock signal CLK, so that signals WT 1 to WT 8 are generated through a DQS signal outputting unit. The signals may be selected according to burst lengths. The signals are selected according to the burst lengths BL in a DQS selection unit so that a signal DQS_OFF_CTRL is output. A reset signal generator outputs a reset signal to reset the output of each shift register provided in the DQS signal outputting unit.

FIG. 2 is a circuit diagram of the initial write controller shown in FIG. 1 . If the signal WTP is applied to the initial write controller, the signal WT 0 is enabled and then not disabled until a next high-level clock pulse is applied.

FIG. 3 is a circuit diagram of the reset signal generator shown in FIG. 1 . When receiving the signal WTP, that is, receiving a new write command, the reset signal generator resets the DQS signal outputting unit. In addition, even when receiving a signal RST, which is generated upon MRS or power-up, the reset signal generator performs a reset operation. In a read operation, the reset signal generator performs the reset operation.

FIGS. 4 and 5 are operational timing charts of the strobe signal controlling circuit shown in FIG. 1 . FIG. 4 illustrates the operation of the strobe signal controlling circuit in an ideal case, in which a write command corresponding to “BL=8” is consecutively applied twice. When the write command is input at a t 1 clock pulse, the signal WTP is generated, and the signal WTP is inverted to generate a signal RSTB. The initial write controller generates the signal WT 0 corresponding to one period of the clock signal. In addition, signals WT 1 to WT 4 , which are sequentially shifted from the signal WT 0 by one clock, are generated. Finally, the signal DQS_OFF_CTRL is generated. In this case, although the signal WT 4 must be generated at a t 5 clock pulse, the signal WT 4 is not generated because the DQS signal generator is reset by the signal RSTB. Similarly, even in the second write operation, the signal WT 0 is shifted by one period of the clock signal such that the signals WT 1 to WT 4 are generated. In this case, since the next write command does not exist, the signal WT 4 is normally generated. Thereafter, the signal DQS_OFF_CTRL signal is generated to control the following DQS signal.

FIG. 5 illustrates a case in which the signal WTP is applied prior to the signal CLK. The signal RSTB is generated in the same time point as that of the signal WTP. The signal WT 0 is generated at the same time point as the enable time point of the signal WTP. In this case, when the signal WT 0 is shifted to a shift register, the signal RSTB becomes a high level before the clock signal becomes a low level. In other words, since the clock signal is in the low level when the signal WT 0 is shifted to the shift register, the signal WT 0 is not shifted by ½ CLK, but signals prolonged by ½ CLK are generated. Accordingly, the signal WT 1 is enabled from a time point, at which the low level of the signal RSTB is changed into the high level, to a next enable time point of the clock signal while maintaining a high level. Such signals are consecutively delivered through shift registers, and the signal WT 4 exists in remaining duration except for a portion of a next write signal WTP, differently from that shown in FIG. 4 . The signal WT 4 becomes the signal DQS_OFF_CTRL as it is, to prevent the last falling DQS in the first write operation and a falling DQS in the second write operation from being generated, so that a write fail occurs.

In an aspect of the present disclosure, a strobe signal controlling circuit is provided which is capable of normally controlling a signal DQS even if a write pulse signal is generated prior to a clock signal when a write command is input.

In one embodiment, a strobe signal controlling circuit includes a control signal generator configured to generate a control signal for controlling a write DQS signal in response to a initial write pulse signal in synchronization with a clock signal.

In another embodiment, a strobe signal controlling circuit includes an initial write controller configured to output a write pulse signal, which is activated in a write command, in synchronization with a clock signal, a DQS signal outputting unit configured to output a write DQS signal by synchronizing an output signal of the initial write controller to the clock signal, a control signal generator configured to generate a control signal in response to the output signal of the initial write controller, and a reset signal generator configured to respond to a reset signal and a DQS enable signal to output a reset signal to the DQS signal outputting module in synchronization with the control signal.

The above and other aspects, features and other advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing a conventional strobe signal controlling circuit;

FIG. 2 is a circuit diagram of an initial write controller of FIG. 1 ;

FIG. 3 is a circuit diagram of a reset signal generator of FIG. 1 ;

FIGS. 4 and 5 are operational timing charts of the strobe signal controlling circuit shown in FIG. 1 ;

FIG. 6 is a block diagram showing a strobe signal controlling circuit according to an exemplary embodiment of the present disclosure;

FIG. 7 is a circuit diagram of an initial write controller shown in FIG. 6 ;

FIG. 8 is a circuit diagram of a control signal generator shown in FIG. 6 ;

FIG. 9 is a circuit diagram of a reset signal generator shown in FIG. 6 ;

FIGS. 10 a and 10 b are circuit diagrams of a DQS signal outputting unit shown in FIG. 6 ;

FIG. 11 is a circuit diagram of a DQS selection unit shown in FIG. 6 ; and

FIG. 12 is an operational timing chart of a strobe signal controlling circuit of FIG. 6 .

Hereinafter, examples and exemplary embodiments of the present invention will be described with reference to accompanying drawings.

FIG. 6 is a block diagram showing a strobe signal controlling circuit according to an exemplary embodiment of the present disclosure.

In the exemplary embodiment shown in FIG. 6 , the strobe signal controlling circuit includes an initial write controller 10 , a DQS signal outputting unit 20 , a control signal generator 30 , and a reset signal generator 40 . The initial write controller 10 inputs a write pulse signal WTP, which is activated in a write command, in synchronization with a clock signal CLK. The DQS signal outputting unit 20 outputs write DQS signals WT 1 to WT 8 by synchronizing an output signal WT 0 of the initial write controller 10 to the clock signal CLK. The control signal generator 30 generates a control signal WTP_CLK in response to the output signal WT 0 of the initial write controller 10 . The reset signal generator 40 responds to a reset signal RST and a DQS enable signal EN_DQS to output a reset signal RSTB to the DQS signal outputting unit 20 in synchronization with the control signal WTP_CLK.

FIG. 7 is a circuit diagram of the initial write controller 10 shown in FIG. 6 .

As shown in FIG. 7 , the initial write controller 10 includes a driver 11 , which is driven in response to the write pulse signal WTP, and a clock synchronization unit 12 , which responds to the clock signal CLK to output an output signal of the driver 11 in synchronization with the clock signal.

The driver 11 includes a pull-up driver, which is pull-up driven in response to the write pulse signal WTP, and a pull-down driver, which is pull-down driven in response to the write pulse signal WTP.

The clock synchronization unit 12 includes a pull-up driver, which is pull-up driven in response to the inverse signal of the clock signal CLK, and a pull-down driver, which is pull-down driven in response to the clock signal CLK.

The initial write controller 10 further includes a latch unit 13 for latching the output signal of the driver 11 .

FIG. 8 is a circuit diagram of the control signal generator 30 shown in FIG. 6 .

As shown in FIG. 8 , the control signal generator 30 includes a delay unit 31 , which delays the output signal WT 0 of the initial write controller 10 by predetermined time and then outputs the output signal WT 0 , and an operation unit 32 , which performs a logical operation with respect to the output signal of the initial write controller 10 and the output signal of the delay unit 31 .

FIG. 9 is a circuit diagram of the reset signal generator 40 shown in FIG. 6 .

As shown in FIG. 9 , the reset signal generator 40 includes a first operation unit 41 , which performs a logical operation in response to the reset signal RST and the DQS enable signal EN_DQS, and a second operation unit 42 , which performs a logical operation in response to the output signal of the first operation unit 41 and the control signal WTP_CLK.

FIGS. 10 a and 10 b are circuit diagrams of the DQS signal outputting unit 20 shown in FIG. 6 .

As shown in FIG. 10 a , the DQS signal outputting unit 20 includes a plurality of shift registers 21 which output input write DQS signals WTn in synchronization with the clock signal CLK, and are reset in response to the reset signal RSTB.

As shown in FIG. 10 b , the shift register 21 includes a DQS signal synchronization unit 211 , an operation unit 212 , and a buffer unit 213 . The DQS signal synchronization unit 211 outputs the write DQS signal WTn in synchronization with the clock signal CLK. The operation unit 212 performs a logical operation in response to the output signal of the DQS signal synchronization unit 211 and the reset signal RSTB. The buffer unit 213 buffers the output signal of the operation unit 22 .

FIG. 11 is a circuit diagram of a DQS selection unit 50 shown in FIG. 6 .

In the exemplary embodiment shown in FIGS. 6 and 11 , the DQS selection unit 50 responds to the output signals WT 1 to WT 8 of the DQS signal outputting unit 20 and burst length signals BL 2 , BL 4 , BL 8 , and BL 16 to output a DQS off control signal DQS_OFF_CTRL.

As shown in FIG. 11 , the DQS selection unit 50 includes first to fourth operation units 51 , which perform logical operations in response to the write DQS signals and the burst length signals, and a fifth operation unit 52 , which performs a logical operation with respect to the output signals of the first to fourth operation units 51 .

Hereinafter, the operational procedure according to an exemplary embodiment of the present disclosure having the above structure will be described with reference to FIGS. 6 to 12 . FIG. 12 is an operational timing chart of the strobe signal controlling circuit of FIG. 6 .

As shown in FIGS. 6 and 7 , the initial write controller 10 according to the exemplary embodiment of the present invention outputs the write pulse signal WTP, which is activated in a write command, in synchronization with the clock signal CLK. Even if the write pulse signal WTP is input prior to the clock signal CLK, the pull-up driver and the pull-down driver are synchronized to the clock signal CLK such that the write pulse signal WTP always follows the clock signal CLK.

As shown in FIG. 8 , the control signal generator 30 outputs the control signal WTP_CLK in response to the output signal WT 0 of the initial write controller 10 . In this case, the output signal WT 0 is delayed such that the output signal WT 0 has a predetermined pulse width. This is necessary to prevent the strobe signal controlling circuit from erroneously operating due to a narrow pulse width when the write pulse signal WTP is applied after the clock signal CLK. In addition, the output signal WT 0 synchronized to the clock signal CLK passes through at least two inverter stages, such that the output signal WT 0 is naturally applied after the clock signal CLK.

As shown in FIG. 9 , the reset signal generator 40 responds to the reset signal RST and the DQS enable signal EN_DQS to output the reset signal RSTB to the DQS signal outputting unit 20 in synchronization with the control signal WTP_CLK. In other words, the control signal WTP_CLK is applied to a unit for generating the reset signal RSTB, such that the reset signal RSTB is always generated after the clock signal CLK. Accordingly, it is possible to solve a problem that a write DQS signal is shifted only by ½ period of the clock signal in the first shift register.

As described above, according to the present invention, even if the write pulse signal is generated prior to the clock signal upon the write command, the DQS signal can be normally controlled.

Although examples and preferred embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

The present disclosure claims priority to Korean application number 10-2007-0141029, filed on Dec. 28, 2007, the entire contents of which are incorporated herein by reference.