Multiplication circuit and de/encryption circuit utilizing the same

(A) Field of the Invention

The present invention relates to an arithmetic circuit, and more particularly, to an arithmetic circuit for matrix and scalar multiplication.

(B) Description of the Related Art

As usage of the Internet continues to grow, the demand for security has become the priority issue in network communication. The realizations of information security algorithms can be roughly categorized into two types:

software-based and hardware-based implementations. The software-based implementation utilizes a processing unit to execute the calculation of the cryptographic algorithms. However, when traffic on the network increases, the processing unit will perform poorly as the capacity thereof will mainly occupied by instructions related to the network packets. The performance downgrade is much alleviated in hardware-based implementation, since there is a hardware circuit dedicated to the calculation of the cryptographic algorithms. Therefore, in high rate network communication, most systems are implemented hardware-wise.

Cryptography can be categorized into two types based on the key used in the algorithm: symmetric systems and asymmetric systems. Symmetric systems use the same key during the encryption and decryption process, while asymmetric systems use different ones. Advanced Encryption Standard (AES), which is a new symmetric system announced by the National Institute of Standards and Technology in 2001, requires matrix multiplications during the encryption and decryption process. Meanwhile, Elliptic Curve Cryptography (ECC) and Rivest-Shamir-Adelman (RSA) algorithms, both asymmetric systems, require scalar multiplications during the encryption and decryption process. These systems are used widely in cryptography systems, so an integrated design that can support AES RSA, and ECC is necessary. Therefore, it is necessary to design a multiplication circuit supporting both matrix and scalar multiplications.

A multiplication circuit, generating a product of a matrix and a first scalar when in matrix mode and a product of a second scalar and a third scalar when in scalar mode, is described. The multiplication circuit comprises a sub-product generator, an accumulator and an adder. The adder is configured to sum outputs of the accumulator to generate the product of the second scalar and the third scalar when in scalar mode. When the multiplication circuit is in matrix mode, the sub-product generator generates sub-products of the matrix and the first scalar. The sub-products are stacked into a square form and are summed by the accumulator to generate save of the summation to be the product of the matrix and the first scalar. When the multiplication circuit is in scalar mode, the sub-product generator generates sub-products of the second scalar and the third scalar. The sub-products are stacked and shifted into a stair form, and a middle part is extracted to form a square matrix and zeroes pad the empty fields. The accumulator is configured to sum the square matrix to generate save and carry of the summation of the square matrix. Saves and carries of the summation of the remaining parts of the stair form of the sub-products are also generated.

A de/encryption circuit for Advanced Encryption Standard (AES), Rivest-Shamir-Adelman (RSA) and Elliptic Curve Cryptography (ECC) algorithm comprising an arithmetic circuit, a storage module, a controller circuit and a multiplication circuit according to the multiplication circuit described above, is described. The arithmetic circuit generates the round keys for the AES algorithm. The storage module provides the data to be de/encrypted. The multiplication according executes the multiplication operation of the round keys and the data provided by the arithmetic circuit and the storage module and storing the results in the storage module.

The objectives and advantages of the present invention will become apparent upon reading the following description and upon reference to the accompanying drawings in which:

FIG. 1 shows a matrix multiplication of a matrix multiplied by a scalar vector;

FIG. 2 shows a scalar multiplication of two scalar vectors multiplied together;

FIG. 3 shows the summation of the sub-products of the scalar multiplication;

FIG. 4 shows the architecture of one embodiment of the multiplication circuit of the present invention;

FIG. 5 shows a further description of the operation of the embodiment of the multiplication circuit of the present invention;

FIG. 6 shows the schematic view of the embodiment of the carry-save type accumulator of the multiplication circuit of the present invention;

FIG. 7A and 7B show the multiplication operation of the embodiment of the multiplication circuit of the present invention;

FIG. 8 show the multiplication operation of the embodiment of the multiplication circuit of the present invention; and

FIG. 9 shows the architecture of one embodiment of the de/encryption circuit of the present invention.

FIG. 1 shows a matrix multiplication of a matrix multiplied by a scalar vector. As shown in FIG. 1 , M is an eight-by-eight matrix and contains coefficients m00 to m77. B is a scalar vector containing bits b 0 to b 7 . B′ is the product containing bits b 0 ′ to b 7 ′. The product B′ can be represented as follows:

wherein

c 0 b 7 ={m 00 b 7 , m 10 b 7 , m 20 b 7 , m 30 b 7 , m 40 b 7 , m 50 b 7 , m 60 b 7 , m 70 b 7 }′,

c 1 b 6 ={m 01 b 6 , m 11 b 6 , m 21 b 6 , m 31 b 6 , m 41 b 6 , m 51 b 6 , m 61 b 6 , m 71 b 6 }′,

c 2 b 5 ={m 02 b 5 , m 12 b 5 , m 22 b 5 , m 32 b 5 , m 42 b 5 , m 52 b 5 , m 62 b 5 , m 72 b 5 }′,

c 3 b 4 ={m 03 b 4 , m 13 b 4 , m 23 b 4 , m 33 b 4 , m 43 b 4 , m 53 b 4 , m 63 b 4 , m 73 b 4 }′,

c 4 b 3 ={m 04 b 3 , m 14 b 3 , m 24 b 3 , m 34 b 3 , m 44 b 3 , m 54 b 3 , m 64 b 3 , m 74 b 3 }′,

c 5 b 2 ={m 05 b 2 , m 15 b 2 , m 25 b 2 , m 35 b 2 , m 45 b 2 , m 55 b 2 , m 65 b 2 , m 75 b 2 }′,

c 6 b 1 ={m 06 b 1 , m 16 b 1 , m 26 b 1 , m 36 b 1 , m 46 b 1 , m 56 b 1 , m 66 b 1 , m 76 b 1 }′ and

c 7 b 0 ={m 07 b 0 , m 17 b 0 , m 27 b 0 , m 37 b 0 , m 47 b 0 , m 57 b 0 , m 67 b 0 , m 77 b 0 }′, wherein

c 0 b 7 to c 7 b 0 are called the sub-products of the matrix multiplication, and ⊕ stands for exclusive-or operation.

FIG. 2 shows a scalar multiplication of two scalar vectors multiplied together. As shown in FIG. 2 , D is a scalar vector containing bits d 0 to d 7 , and E is also a scalar vector containing bits e 0 to e 7 . If D and E are respectfully denoted by D=d 7 2 7 +d 6 2 6 + . . . +d 1 2 1 +d 0 and E=e 7 2 7 +e 6 2 6 + . . . +e 1 2 1 +e 0 , then the product F can be represented as follows:

F = E × ( d 7 ⁢ 2 7 + d 6 ⁢ 2 6 + … + d 1 ⁢ 2 1 + d 0 ) = E × d 7 ⁢ 2 7 + E × d 6 ⁢ 2 6 ⁢ ⁢ … + E × d 1 ⁢ 2 1 + E × d 0 ,

wherein E×d 7 2 7 to E×d 0 are called the sub-products of the scalar multiplication. As shown in FIG. 2 , the sub-products are then summed together to obtain the result.

In the present invention the matrix multiplication and the scalar multiplication are integrated together by extracting the similar operations out for the main calculation of the multiplication circuit and executing the remaining operation thereafter. When the multiplication circuit is executing a multiplication operation, the sub-products are first obtained. When the multiplication circuit is in matrix mode, the sub-products are summed together to give the final result. When the multiplication circuit is in scalar mode, on the other hand, the multiplication process is divided into several stages to be integrated with the matrix multiplication operation.

As shown in FIG. 3 , the summation of the sub-products of the scalar multiplication is separated into three parts. P 1 is extracted from the middle part of the stacked sub-products to form a square matrix, wherein zeroes pad the empty fields. P 2 is the least significant part of the stacked sub-products. P 3 is the most significant part of the stacked sub-products. The matrix P 1 is then summed in carry-save sense to give the carry and save of the summation. Since the summation in the matrix multiplication is in fact the exclusive-or operation, the carries do not need to be carried over. Therefore, the save of the summation of P 1 is the result requested when the multiplication circuit is in matrix mode. On the other hand, when the multiplication circuit is in scalar mode, further summations are needed. The carry and save of the summation of P 3 are summed together with the carries and saves of the summation of P 1 and P 2 to give the final result.

FIG. 4 shows the architecture of one embodiment of the multiplication circuit of the present invention. The multiplication circuit 400 supports eight-bit matrix multiplication of a matrix M multiplied by a first scalar A and eight-bit scalar multiplication of the first scalar A multiplied by a second scalar B. The multiplication circuit 400 comprises a sub-product generator 410 , an accumulator 420 and an adder 430 . The sub-product generator 410 receives the first scalar A, the second scalar B and the coefficients m 00 to m 77 of the matrix M.

When the multiplication circuit 400 is in matrix mode, the sub-product generator 410 generates the sub-products of the matrix M and the first scalar A. The accumulator 420 then sums the sub-products to generate the save of the summation to be the product of the matrix multiplication.

When the multiplication circuit 400 is in scalar mode, the sub-product generator 410 generates the sub-products of the first scalar A and the second scalar B. The sub-products are stacked and shifted into a stair form, the middle part P 1 is extracted to form a square matrix and zeroes pad the empty fields, as shown in FIG. 3 , while the remaining parts are denoted by P 2 and P 3 . The accumulator 420 then sums P 1 , P 2 and P 3 to generate the carries and saves. The adder 430 then sums the carries and saves from the accumulator 420 to give the final result. Preferably, the multiplication circuit 400 may further comprise a storage unit 440 , such as a read-only memory (ROM), and the accumulator 420 is carry-save accumulator, such as a Wallace Tree accumulator.

FIG. 5 shows a further description of the operation of the embodiment of the multiplication circuit of the present invention. The inputs of the multiplication circuit 400 are the first scalar A, the second scalar B and the matrix M. As shown in FIG. 5 , the matrix P 1 contains vectors P 10 to P 17 . When the multiplication circuit 400 is in matrix mode, the vectors P 10 to P 17 can be represented as follows:

P 10 ={m 00 a 7 , m 10 a 7 , m 20 a 7 , m 30 a 7 , m 40 a 7 , m 50 a 7 , m 60 a 7 , m 70 a 7 }, P 11 ={m 01 a 6 , m 11 a 6 , m 21 a 6 , m 31 a 6 , m 41 a 6 , m 51 a 6 , m 61 a 6 , m 71 a 6 }, P 12 ={m 02 a 5 , m 12 a 5 , m 22 a 5 , m 32 a 5 , m 42 a 5 , m 52 a 5 , m 62 a 5 , m 72 a 5 }, P 13 ={m 03 a 4 , m 13 a 4 , m 23 a 4 , m 33 a 4 , m 43 a 4 , m 53 a 4 , m 63 a 4 , m 73 a 4 }, P 14 ={m 04 a 3 , m 14 a 3 , m 24 a 3 , m 34 a 3 , m 44 a 3 , m 54 a 3 , m 64 a 3 , m 74 a 3 }, P 15 ={m 05 a 2 , m 15 a 2 , m 25 a 2 , m 35 a 2 , m 45 a 2 , m 55 a 2 , m 65 a 2 , m 75 a 2 }, P 16 ={m 06 a 1 , m 16 a 1 , m 26 a 1 , m 36 a 1 , m 46 a 1 , m 56 a 1 , m 66 a 1 , m 76 a 1 }, and P 17 ={m 07 a 0 , m 17 a 0 , m 27 a 0 , m 37 a 0 , m 47 a 0 , m 57 a 0 , m 67 a 0 , m 77 a 0 }.

When the multiplication circuit 400 is in scalar mode, on the other hand, the vectors P 10 to P 17 can be represented as follows:

P 10 ={0, 0, 0, a 0 b 7 , a 0 b 6 , a 0 b 5 , a 0 b 4 , a 0 b 3 }, P 11 ={0, 0, a 1 b 7 , a 1 b 6 , a 1 b 5 , a 1 b 4 , a 1 b 3 , a 1 b 2 }, P 12 ={0, a 2 b 7 , a 2 b 6 , a 2 b 5 , a 2 b 4 , a 2 b 3 , a 2 b 2 , a 2 b 1 }, P 13 ={a 3 b 7 , a 3 b 6 , a 3 b 5 , a 3 b 4 , a 3 b 3 , a 3 b 2 , a 3 b 1 , a 3 b 0 }, P 14 ={a 4 b 6 , a 4 b 5 , a 4 b 4 , a 4 b 3 , a 4 b 2 , a 4 b 1 , a 4 b 0 }, P 15 ={a 5 b 5 , a 5 b 4 , a 5 b 3 , a 5 b 2 , a 5 b 1 , a 5 b 0 , 0, 0}, P 16 ={a 6 b 4 , a 6 b 3 , a 6 b 2 , a 6 b 1 , a 6 b 0 , 0, 0, 0}, and P 17 ={a 7 b 3 , a 7 b 2 , a 7 b 1 , a 7 b 0 , 0, 0, 0, 0}. P 2 contains vectors P 21 , P 22 and P 23 , which can be represented as follows: P 21 ={a 0 b 2 , a 0 b 1 , a 0 b 0 }, P 22 ={a 1 b 1 , a 1 b 0 }, and P 23 =a 3 b 0 . P 3 contains vectors P 31 , P 32 , P 33 and P 34 , which can be represented as follows: P 31 =a 4 b 7 , P 32 ={a 5 b 7 , a 5 b 6 }, P 33 ={a 6 b 7 , a 6 b 6 , a 6 b 5 }, and P 34 ={a 7 b 7 , a 7 b 6 , a 7 b 5 , a 7 b 4 }.

The matrix P 1 is then summed together by the accumulator 420 as follows:

{C 1 , S 1 }=CSA (P 10 +P 11 +P 12 ), {C 2 , S 2 }=CSA (P 13 +P 14 +P 15 ), and {C 3 , S 3 }=CSA (P 16 +P 17 ), wherein CSA denotes the carry-save adder operation, C 1 to C 3 are carries and S 1 to S 3 are saves. S 1 to S 3 are then summed together as follows: {C 4 , S_}=CSA (S 1 +S 2 +S 3 ). Therefore, S_ equals S 1 ⊕S 2 ⊕S 3 =PP 0 ⊕PP 1 ⊕PP 2 ⊕PP 3 ⊕PP 4 ⊕PP 5 ⊕PP 6 ⊕PP 7 , which is the result requested in matrix mode. When in scalar mode, however, more calculation is needed. C 1 to C 3 are then summed together as follows: {C 5 , S 5 }=CSA (C 1 +C 2 +C 3 ). C 4 , S 5 and S_ are then summed together as follows: {C 6 , S 6 }=CSA (C 4 +S 5 +S_). C 6 , S 6 and C 5 are then summed together as follows: {C, S}=CSA (C 6 +S 6 +C 5 ). FIG. 6 shows the schematic view of the embodiment of the carry-save type accumulator of the multiplication circuit of the present invention. CSA 1 to CSA 7 are carry-save adders, which are connected in the manner according to the accumulation process described above, e.g., the operation in layer 1 in FIG. 5 is executed by CSAs in layer 1 in FIG. 6 . As shown in FIG. 6 , CSA 1 gives the carry C 1 and save S 1 , CSA 2 gives the carry C 2 and save S 2 , and so on.

P 2 are summed together to give save S_P 2 and carry C_P 2 , while P 3 are summed together to give save S_P 3 and carry C_P 3 , as shown in FIG. 7A and 7B . Finally, C, S C_P 2 , S_P 2 , C_P 3 and S_P 3 are summed together in the adder 130 to give the final result, as shown in FIG. 8 .

The embodiment of the multiplication circuit of the present invention shown above is for 8 bits matrix multiplication and 8 bits scalar multiplication. However, the multiplication circuit of the present invention can easily be extended to higher bits multiplication application.

FIG. 9 shows the architecture of one embodiment of the de/encryption circuit of the present invention. The de/encryption circuit 900 comprises the multiplication circuit 910 of the present invention, an arithmetic circuit 920 , an input/output (IO) interface circuit 930 , a controller circuit 940 and a storage module 950 . The multiplication circuit 910 comprises a sub-product generator 911 , an accumulator 912 , which includes an exclusive-or tree calculator 9121 and a Wallace tree calculator 9122 , and an adder 913 . The arithmetic circuit 920 comprises a key expansion circuit 921 and Galois-field inverter 922 . The controller circuit 940 comprises an 10 controller circuit 941 and a main controller 942 . The storage module 950 comprises a storage element 951 and a storage management unit 952 . The multiplication circuit 910 executes the multiplication operation of the data provided by the arithmetic circuit 920 and the storage module 950 and stores the results in the storage module 950 . As shown in FIG. 9 , the multiplication circuit 910 provides three kinds of output: a matrix multiplication output with 128 bits, a polynomial multiplication output with 160 bits and a scalar multiplication output with 161 bits. The polynomial multiplication output is obtained by adding S_, S_P 2 and S_P 3 together. The key expansion circuit 921 generates the round keys for AES algorithm. The Galois-field inverter 922 performs invert operation needed in AES algorithms. In conclusion, the arithmetic circuit 920 performs the calculation other than the matrix multiplication in AES algorithm.

As can be seen in FIG. 9 , the multiplication circuit of the present invention integrates the multiplication operation of AES, RSA and ECC algorithms to form a much compact de/encryption circuit. However, the multiplication circuit of the present not only can be used in cryptography, but can also be used in media data processing, digital signal processing and other data processing algorithms.

The above-described embodiments of the present invention are intended to be illustrative only. Those skilled in the art may devise numerous alternative embodiments without departing from the scope of the following claims.