Measuring and predicting VLSI chip reliability and failure

Reliability becomes a big concern for modern VLSI chips, due to the shrinking lithography, new material, and design complexity, etc. The major causes of reliability failures include electro-migration (modeled as resistive bridges), gate oxide breakdown (resistive shorts), hot carrier injection (delay faults), etc. Most of the reliability failures will cause the chip to degrade or slow down, and eventually the chip will stop functioning. Therefore, there is a need to monitor and predict the reliability of a chip in the field. So far, there is no on-line reliability monitor once the chip is shipped. Therefore, the degradation of a chip cannot be monitored. This embodiment teaches a new solution for this problem.

Logic-Built-In-Self-Test (LBIST) is a widely accepted Design-for-Test (DFT) feature of VLSI chip designs, especially for the microprocessor designs. It can be used to test the circuit at wafer, chip, and system level. During testing, a specific designed circuitry is running and generates test stimulus and collects testing results. Test can be performed at both dc and ac fashion.

With added features and new methodology, LBIST can be used as an on-line reliability monitor with very little or no overhead, depending on the LBIST implementation.

In an embodiment of this invention, instead of using LBIST to get a pass or no-pass result, a selective signature feature is used to collect the top failing paths by shmooing the chip over a cycle time. These paths can be stored on-chip or off-chip for later use. Once the chip is running in the field for a certain time, the same procedure is performed to collect the top failing paths and compared with the stored old paths, if the order of the top paths changes, it indicates that for example there is a path (not the slowest path before) that slows more than others, which could be potential reliability concern. Therefore, a potential reliability failure is identified in the field.

FIG. 1 is a schematic diagram of a typical LSSD configuration.

FIG. 2 is a schematic diagram of a typical L 1 /L 2 latch.

FIG. 3 is a schematic diagram of Stumps LBIST configuration.

FIG. 4 is a schematic diagram of Selective signature LBIST scheme.

FIG. 5 is a flow diagram of Reliability monitor scheme.

The LSSD (level sensitive scan design) methodology is a system design and a Design-for-Test (DFT) approach that incorporates several basic test concepts, i.e. scan design. In such a design, most of the device's storage elements, such as latches or registers, are concatenated in one or more scan chains and can be externally accessible via one or more serial inputs and outputs. Storage elements that are not in this category are usually memory or other special macros that are isolated and tested independently. Furthermore, this design methodology ensures that all logic feedback paths are gated by one or more of these storage elements, thereby simplifying a sequential design into subsets of combinational logic ( 100 , 110 and 120 , respectively) sections as shown in FIG. 1 .

These basic design concepts in conjunction with the associated system and scan clocking sequences greatly simply the test generation, testing, and diagnose-ability of very complex logic structures. Every latch can be used as a pseudo Primary Input (PI) and as a pseudo Primary Output (PO) in addition to the standard PIs and POs to enhance the stimulation and observe-ability of the device being tested or diagnosed. LSSD latches are typically implemented in a L 1 /L 2 configuration where the L 1 or master latch has two data ports and may be updated either using scan clock A/B or functional clock C 1 /C 2 ( 200 and 210 , respectively) as shown in FIG. 2 . The L 2 or slave latch has only one clock input and that clock is out of phase with both L 1 clocks. Scanning is done using separate A and B clocks.

In a typical STUMPS structure, shown in FIG. 3 , LFSR ( 300 ) is used to generate the pseudo random patterns. These patterns are scanned in through L 1 /L 2 latches via A/B clocks. Then, the system clocks C 1 /C 2 are used to insert these patterns into the combination logic and A/B clocks are used to scan the test responses to the MISR ( 310 ). A certain number of responses can be compressed into a MISR signature. This signature can be compared with a simulation signature and the result will show if the chip is good or bad. Repeat this procedure until all the test patterns are applied, thereafter, the whole chip is tested.

This STUMPS structure can be further enhanced by adding some control logic ( 400 ) to not only let the test results from a group of latches compress into MISR, but an individual latch as well. FIG. 4 shows such structure. This feature is called selective signature.

In an embodiment of this invention, with the structure shown in FIG. 4 , every single path on a chip can be tested by only selecting one latch at a time to compress into MISR while shmooing the chip. Once all the results from every latch are recorded, the top critical paths are determined. A critical path (or called critical timing path) is a logical path that runs slower than predicted or slower than any other logical paths in the system. These top critical paths can be stored on chip ( 410 ) as well as off-chip for later comparison. FIG. 5 shows the on-chip and off-chip storage scheme. In the on-chip case, a group of registers is added to store the latches. In the off-chip case, latches can be recorded in any storage medium, such as electronic file, tape, and CD. After a certain period of time ( 500 ), the above procedure is repeated and the top critical paths are recorded ( 510 ). If there is a reliability problem, the order of top critical paths or the timing of top paths will be changed, which will indicate a potential reliability problem ( 520 ).

An embodiment of the invention is a method for measuring and predicting reliability of a VLSI chip, the method is comprised of:

Running a plurality of selective signature shmoo tests on the VLSI chip to determine a first plurality of top critical paths based on a first selective signature shmoo test of the plurality of selective signature shmoo tests; moreover there are a predetermined number of critical paths in the first plurality of top critical paths which results in ordering a first critical path in the first plurality of top critical paths based on a first timing of the first critical path that assigns a first critical path order to the first critical path and storage of the first plurality of top critical paths. If the storing step is done off-chip, the first plurality of top critical paths is recorded in a storage media. If the storing step is done on-chip, the plurality of top critical paths is recorded in one or more critical path registers on the VLSI chip and to determine a second plurality of top critical paths based on a second selective signature shmoo test of the plurality of selective signature shmoo tests; wherein the second selective signature shmoo test is performed in a field after a cycle time proceeding the first selective signature shmoo test and to order each second critical path in the second plurality of top critical paths based on a second timing of the second critical path and assigning a second critical path order to the second critical path. Moreover to compare the second plurality of top critical paths with the first plurality of top critical paths. If in the comparison step, the second critical path order is the same as the first critical path order, and the second critical path is not the same as the first critical path, then reporting a change in critical path order of the first critical path and a potential reliability issue. If in the comparing step, the second critical path order is the same as the first critical path order, the second critical path is the same as the first critical path, and the first timing is more than the second timing by more than a time degradation threshold value, then reporting an increase in timing of the first critical path and a potential reliability issue. The plurality of selective signature shmoo tests are performed using a level sensitive scan design and testing methodology; wherein the VLSI chip has a logic-built-in-self-test feature; and the logic-built-in-self-test feature comprises one or more latches and one or more registers, concatenated in one or more scan chains, accessible via one or more serial inputs and one or more serial outputs, a linear feedback shift register generating one or more pseudo-random patterns, a control logic to select a set of the one or more latches and test results from the set of the one or more latches associated with a selective signature for collection into a multiple-input-signature register, and the multiple-input-signature register.

A system, apparatus, or device comprising one of the following items is an example of the invention: VLSI, chip, reliability analyzer, failure analyzer, tests, storing, registers, Shmoo test, computer monitor, or any display device, applying the method mentioned above, for purpose of VLSI/chip analysis, reliability, and management.

Any variations of the above teaching are also intended to be covered by this patent application.