Coupling cancellation scheme

1. Field of the Invention

Embodiments of the invention relate to electronic devices, and more particularly, in one or more embodiments, to an interconnection layout for integrated circuits and/or printed circuit boards.

2. Description of the Related Art

In many applications in which electronic information is transmitted over a relatively long line, differential signaling has been widely used. Differential signaling is a method of transmitting information using two complementary signals sent on two separate lines. A differential circuit at a receiving end detects and compares the complementary signals, and determines logic changes based on the changes of one of the signals with reference to the other. Differential signaling is known to provide a relatively fast and accurate data transmission mechanism.

In differential signaling, however, a pair of lines carrying complementary signals can have electrical coupling or cross-talk between the pair of lines (intra-pair coupling) and/or with another neighboring pair of lines (inter-pair coupling). This electrical coupling adversely affects the accuracy of information transmitted over the lines. Thus, there is a need to provide a scheme to reduce or eliminate electrical coupling among separate pairs of differential lines.

FIG. 1 illustrates a conventional interconnection layout that can be used in an integrated circuit (IC) or a printed circuit (PC) board (also known as a printed wiring board) for differential signaling. The illustrated portion of the layout 100 can be repeated vertically and/or horizontally in the IC or PC board.

Typically, an interconnection layout for differential signaling can include a pair of lines that are “twisted” (wound), cross back and forth without twisting, or a combination of both. The illustrated portion includes first to fourth differential pairs L 1 -L 4 . Each of the differential pairs L 1 -L 4 includes two lines carrying differential signals. In FIG. 1 , the first pair L 1 includes first and second lines L 1 a , L 1 b . The second pair L 2 includes first and second lines L 2 a , L 2 b . The third pair L 3 includes first and second lines L 3 a , L 3 b . The fourth pair L 4 includes first and second lines L 4 a , L 4 b . The illustrated portion of the layout 100 includes four regions a, b, c, d from left to right. A boundary 121 , 122 , or 123 between neighboring ones of the regions a, b, c, d extends substantially perpendicular to a direction in which the pairs L 1 -L 4 of lines extend. Each of the four regions a, b, c, d includes portions of all the pairs L 1 -L 4 of lines.

Each of the pairs L 1 -L 4 of lines includes crossing portions CP at an interval of ½ l. The crossing portions CP of the lines cross each other, for example, forming an “X” shape. The details of the crossing portions CP will be described later with reference to FIGS. 3A-3C and 4 A- 4 C. Each of the pairs L 1 -L 4 of lines includes parallel portions PP between neighboring ones of the crossing portions CP. The parallel portions PP of the lines extend substantially parallel to each other.

In FIG. 1 , odd-numbered pairs L 1 , L 3 have crossing portions CP adjacent to the parallel portions PP of neighboring even-numbered pairs L 2 , L 4 . Similarly, even-numbered pairs L 2 , L 4 have crossing portions CP adjacent to the parallel portions PP of neighboring odd-numbered pairs L 1 , L 3 . The crossing portions CP of the first and third pairs L 1 , L 3 are positioned at the boundary 122 between the regions b and c. Some of the crossing portions CP of the second and fourth pairs L 2 , L 4 are positioned at the boundary 121 between the regions a and b while the other crossing portions CP of the second and fourth pairs L 2 , L 4 are positioned at the boundary 123 between the regions c and d.

In the layout 100 of FIG. 1 , the line L 2 a is adjacent to the line L 1 b in the region a, the line L 3 a in the region b, the line L 3 b in the region c, and the line L 1 a in the region d. The line L 2 b which pairs with the line L 2 a is adjacent to the line L 3 a in the region a, the line L 1 b in the region b, the line L 1 a in the region c, and the line L 3 b in the region d. Thus, within a length of l, both of the paired lines L 2 a , L 2 b experience electrical coupling with each of the lines L 1 a , L 1 b , L 3 a , L 3 b of the neighboring pairs L 1 , L 3 by ¼ l. Because signals on the paired lines L 1 a , L 1 b are opposite in polarity to each other, coupling induced on the line L 2 a by these lines L 1 a , L 1 b are also opposite in polarity. Thus, coupling between the line L 2 a and the adjacent first pair L 1 is canceled or reduced. Likewise, coupling between the line L 2 a and the other adjacent third pair L 3 is canceled or reduced. Similarly, coupling between the line L 2 b and the first pair L 1 and coupling between the line L 2 b and the third pair L 3 are also canceled or reduced. In this manner, the layout 100 cancels or reduces inter-pair coupling.

The embodiments will be better understood from the Detailed Description of Embodiments and from the appended drawings, which are meant to illustrate and not to limit the embodiments, and wherein:

FIG. 1 is a schematic diagram of a conventional differential pair interconnection layout for an integrated circuit (IC) or printed circuit (PC) board;

FIG. 2 is a schematic diagram of one embodiment of a differential pair interconnection layout;

FIG. 3A is a top plan view of one embodiment of a differential pair interconnection layout;

FIG. 3B is a cross-section of the differential pair interconnection layout of FIG. 3A , taken along lines 3 B- 3 B;

FIG. 3C is a cross-section of the differential pair interconnection layout of FIG. 3A , taken along lines 3 C- 3 C;

FIG. 4A is a top plan view of another embodiment of a differential pair interconnection layout;

FIG. 4B is a cross-section of the differential pair interconnection layout of FIG. 4A , taken along lines 4 B- 4 B;

FIG. 4C is a cross-section of the differential pair interconnection layout of FIG. 4A , taken along lines 4 C- 4 C; and

FIG. 5 is a schematic block diagram of one embodiment of an electronic device including the differential pair interconnection layout of FIG. 2 .

The concepts and principles of the embodiments described below are presented herein in the context of an integrated circuit. A skilled artisan will, however, appreciate that the concepts and principles of the embodiments are applicable to other circuits, including, but not limited to, printed circuit (PC) boards, such as a board for a DIMM module or a memory module.

The layout 100 described above with reference to FIG. 1 cancels inter-pair coupling among separate differential pairs. However, the layout 100 does not cancel or reduce intra-pair coupling within a differential pair. Since signals of a differential pair are opposite in polarity to each other, intra-pair coupling can attenuate the signal levels. Thus, there is a need to provide a scheme that can reduce or eliminate intra-pair coupling as well as inter-pair coupling.

In one embodiment, an interconnection layout for differential signaling can have differential pairs similar to those described with reference to FIG. 1 , and further includes a plurality of shield lines, each of which extends between paired differential lines. The shield lines run parallel to one or more parallel portions of the differential lines while crossing one or more crossing portions thereof. The pairs of differential lines should cancel or reduce inter-pair coupling therebetween while the shield lines should cancel or reduce intra-pair coupling.

Referring to FIG. 2 , a differential signal interconnection layout 200 in an integrated circuit (IC) according to one embodiment will now be described. The illustrated portion of the layout 200 can be repeated vertically and/or horizontally in the IC. The illustrated portion includes first to fourth differential pairs L 1 -L 4 of differential lines. Each of the differential pairs L 1 -L 4 includes two lines and a conductive shield line S 1 , S 2 , S 3 , or S 4 extending between the two lines.

The paired lines carry complementary signals which are opposite in polarity. In the illustrated embodiment, the first differential pair L 1 includes lines L 1 a , L 1 b . The second differential pair L 2 includes L 2 a , L 2 b . The third differential pair L 3 includes L 3 a , L 3 b . The fourth differential pair L 4 includes L 4 a , L 4 b . The illustrated portion of the layout 200 includes four regions a, b, c, d from left to right. A boundary 221 , 222 , or 223 between neighboring ones of the regions a, b, c, d extends substantially perpendicular to a direction in which the differential pairs L 1 -L 4 of lines extend. Each of the four regions a, b, c, d includes portions of all the differential pairs L 1 -L 4 of lines.

Each of the illustrated differential pairs L 1 -L 4 includes crossing portions CP at an interval of ½ l. The crossing portions CP are located where the differential pair of lines cross each other. Each of the differential pairs L 1 -L 4 includes parallel portions PP between neighboring two of the crossing portions CP. The parallel portions PP of the differential pair of lines extend substantially parallel to each other.

Odd-numbered differential pairs L 1 , L 3 have crossing portions CP adjacent to the parallel portions PP of neighboring even-numbered differential pairs L 2 , L 4 . Similarly, even-numbered pairs L 2 , L 4 have crossing portions CP adjacent to the parallel portions PP of neighboring odd-numbered differential pairs L 1 , L 3 . The crossing portions CP of the first and third differential pairs L 1 , L 3 are positioned at the boundary 222 between the regions b and c. Some of the crossing portions CP of the second and fourth differential pairs L 2 , L 4 are positioned at the boundary 221 between the regions a and b while the other crossing portions CP of the second and fourth differential pairs L 2 , L 4 are positioned at the boundary 223 between the regions c and d.

The shield line S 1 , S 2 , S 3 , or S 4 of each pair extends substantially parallel to the parallel portions PP of the paired lines. In the illustrated embodiment, the shield line S 1 , S 2 , S 3 , or S 4 includes parallel portions interposed between the parallel portions PP of the paired lines. The parallel portions of the shield line S 1 , S 2 , S 3 , or S 4 can be spaced substantially the same distance from the parallel portions PP of the paired lines. The shield line S 1 , S 2 , S 3 , or S 4 also includes crossing portions which crosses both of the paired lines at the crossing portions CP.

Although not illustrated in FIG. 2 , the shield lines S 1 -S 4 are electrically insulated from the paired lines. The shield lines S 1 -S 4 are connected to a voltage reference, such as a DC voltage source Vcc or ground GND. In certain embodiments, some of shield lines may be connected to a DC voltage source Vcc while other shield lines are connected to ground GND. A skilled artisan will, however, appreciate that the positions and configurations of the shield lines S 1 -S 4 may be adjusted depending on the layout of the IC. In other embodiments, a single differential pair can include two or more shield lines which extend parallel to one another. In yet other embodiments, a single differential pair can include two or more shield lines, each of which extends between different parallel portions of the differential lines.

In the layout of FIG. 2 , the line L 2 a is adjacent to the line L 1 b in the region a, the line L 3 a in the region b, the line L 3 b in the region c, and the line L 1 a in the region d. The line L 2 b which pairs with the line L 2 a is adjacent to the line L 3 a in the region a, the line L 1 b in the region b, the line L 1 a in the region c, and the line L 3 b in the region d. Thus, within a length of l, both of the paired lines L 2 a , L 2 b experience inter-pair electrical coupling with each of the lines L 1 a , L 1 b , L 3 a , L 3 b of the neighboring differential pairs L 1 , L 3 by ¼ l. Because signals on the paired lines L 1 a , L 1 b are opposite in polarity, coupling induced on the line L 2 a by these lines L 1 a , L 1 b are also opposite in polarity. Thus, coupling between the line L 2 a and the adjacent first pair L 1 should be canceled or reduced. Likewise, coupling between the line L 2 a and the other adjacent third pair L 3 should be canceled or reduced. Similarly, coupling between the line L 2 b and the first pair L 1 and coupling between the line L 2 b and the third pair L 3 should also be canceled or reduced. In this manner, inter-pair coupling between pairs of differential lines should be reduced and canceled.

In addition, the layout 200 can be further configured to cancel or reduce intra-pair coupling. For example, in the second differential pair L 2 of lines L 2 a , L 2 b , the first line L 2 a experiences coupling with the shield line S 2 and the second line L 2 b also experiences coupling with the shield line S 2 . Because a signal on the first line L 2 a is opposite in polarity from a signal on the second line L 2 b , the coupling between the line L 2 a and the shield line S 2 is opposite in polarity from the coupling between the line L 2 b and the shield line S 2 . Thus, the couplings should be reduced or canceled. Thus, intra-pair coupling between a differential pair of lines should be reduced or canceled.

Referring to FIGS. 3A-3C , an example of a structure of an interconnection layout according to one embodiment will be now described. The illustrated interconnection layout 300 can be implemented with 2 metal layers (L 1 , L 2 ) and includes a differential pair and a shield line 330 formed in metallization layers over a silicon substrate assembly. The differential pair includes a first line 310 and a second line 320 . The first and second lines 310 , 320 and the shield line 330 are insulated from one another with an insulating material.

The first line 310 includes parallel portions 310 a , 310 b and a crossing portion 310 c . In the illustrated embodiment, the parallel portions 310 a , 310 b and the crossing portion 310 c are positioned at a first level L 1 ( FIG. 3B ).

The second line 320 includes parallel portions 320 a , 320 b and a crossing portion 320 c . In the illustrated embodiment, the parallel portions 320 a , 320 b and parts of the crossing portion 320 c extending from the parallel portions 320 a , 320 b are positioned at the first level L 1 . The crossing portion 320 c also includes a connecting line 320 d at a second level L 2 lower than the first level L 1 ( FIG. 3C ). The crossing portion 320 c further includes interconnects, such as plugs/vias, (not shown) to electrically connect the connecting line 320 d to the parts of the crossing portions 320 at the first level L 1 . The connecting line 320 d provides electrical connection between the parts of the crossing portions 320 c at the first level L 1 while being insulated from the first line 310 .

The shield line 330 includes parallel portions 330 a , 330 b and a crossing portion 330 c . The parallel portions 330 a , 330 b are positioned at the first level L 1 ( FIG. 3C ) while the crossing portion 330 c is positioned at the second level L 2 ( FIG. 3C ). The crossing portion 330 c of the shield line 330 is laterally spaced apart from the connecting line 320 d of the second line 320 at the second level L 2 . The shield line 330 further includes interconnect vias 335 a , 335 b to electrically connect the crossing portion 330 c to the parallel portions 330 a , 330 b . The crossing portion 330 c provides electrical connection between the parallel portions 330 a , 330 b while being insulated from the first and second lines 310 , 320 .

Referring to FIGS. 4A-4C , the structure of another example of an interconnection layout will be now described. The illustrated interconnection layout 400 can be implemented with 3 metal layers (L 1 , L 2 , L 3 ) and includes a differential pair and a shield line 430 . The differential pair includes a first line 410 and a second line 420 . The first and second lines 410 , 420 and the shield line 430 are insulated from one another with an insulating material.

The first line 410 includes parallel portions 410 a , 410 b and a crossing portion 410 c . In the illustrated embodiment, the parallel portions 410 a , 410 b and the crossing portion 410 c are positioned at a first level L 1 ( FIG. 4B ).

The second line 420 includes parallel portions 420 a , 420 b and a crossing portion 420 c . In the illustrated embodiment, the parallel portions 420 a , 420 b are positioned at the first level L 1 while the crossing portion 420 c is positioned at a second level L 2 lower than the first level L 1 ( FIGS. 4B and 4C ). The second line 420 further includes interconnect vias 425 to electrically connect the crossing portion 420 c to the parallel portions 420 a , 420 b at the first level L 1 . The crossing portion 420 c provides electrical connection between the parallel portions 420 a , 420 b while being insulated from the first line 410 .

The shield line 430 includes parallel portions 430 a , 430 b and a crossing portion 430 c . The parallel portions 430 a , 430 b are positioned at the first level L 1 ( FIG. 4C ) while the crossing portion 430 c is positioned at a third level L 3 lower than the second level L 2 ( FIG. 4C ). The shield line 430 further includes interconnect plugs/vias 435 a , 435 b to electrically connect the crossing portion 430 c to the parallel portions 430 a , 430 b . The crossing portion 430 c provides electrical connection between the parallel portions 430 a , 430 b while being insulated from the first and second lines 410 , 420 .

A skilled artisan will appreciate that any suitable configurations of a differential pair and a shield line can be used to provide the interconnection layout described above. In certain embodiments in which the interconnection layout is used in a printed circuit board, the structures described above with respect to FIG. 3A-3C or 4 A- 4 C can also be used or modified, depending on the circuit board configuration.

Referring to FIG. 5 , one embodiment of an electronic device including the differential line layout of FIG. 2 will now be described. The illustrated electronic device 500 includes internal circuits 510 , an input/output (I/O) buffer 520 , an interconnecting bus 530 , an I/O bus 540 , and an I/O port 550 .

The internal circuits 510 may include integrated circuits, including, but not limited to, at least one of a processor and a memory cell array. The interconnecting bus 530 electrically connects the internal circuits to the I/O buffer 520 . The I/O buffer 520 temporarily stores data being inputted to or being outputted from the internal circuits 510 . The I/O bus 540 electrically connects the I/O buffer 520 to the I/O port 550 .

In one embodiment, the interconnecting bus 530 may include a plurality of pairs of differential lines with the layout described above in connection with FIG. 2 . A skilled artisan will appreciate that the layout can also be used in other portions of the electronic device (e.g., printed circuit boards) where differential lines are used.

The differential line layouts of the embodiments described above can apply to various electronic devices. Examples of the electronic devices can include, but are not limited to, consumer electronic products, electronic circuits, electronic circuit components, parts of the consumer electronic products, electronic test equipments, etc. Examples of the electronic devices can also include memory chips, memory modules, receiver circuits of optical networks or other communication networks, disk driver circuits, and serializer/deserializer (SerDes). The consumer electronic products can include, but are not limited to, a mobile phone, a telephone, a television, a computer monitor, a computer, a hand-held computer, a personal digital assistant (PDA), a microwave, a refrigerator, a stereo system, a cassette recorder or player, a DVD player, a CD player, a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multi functional peripheral device, a wrist watch, a clock, etc. Further, the electronic device can include unfinished products.

In the embodiments described above, the differential signal interconnection layout should reduce or eliminate intra-pair coupling as well as inter-pair coupling. Because each of the shield lines is positioned between a pair of differential lines, the layout can be implemented without sacrificing a substantial space in the IC.

One embodiment is an apparatus including a first pair of electrically conductive lines insulated from each other. The first pair of lines includes: one or more crossing portions crossing each other; and one or more parallel portions extending on the same plane substantially parallel to each other. The parallel portions alternate with the crossing portions. The apparatus further includes an electrically conductive shield line connected to a voltage reference and electrically insulated from the first pair of lines. The shield line includes a first portion disposed between the parallel portions of the first pair of lines. The first portion of the shield line extends substantially parallel to the parallel portions of the first pair of lines.

Another embodiment is an apparatus including a plurality of differential pairs of lines. Each pair includes two lines including one or more parallel portions extending substantially parallel to each other. The apparatus further includes a plurality of shield lines. Each of the shield lines includes one or more parallel portions interposed between the parallel portions of a respective one of the differential pairs. One or more of the shield lines are electrically connected to a voltage reference.

Yet another embodiment is a method of forming an interconnection layout. The method includes forming a first pair of electrically conductive lines electrically insulated from each other on a substrate. The first pair of lines includes: one or more crossing portions crossing each other; and one or more parallel portions extending on the same plane substantially parallel to each other. The parallel portions alternate with the crossing portions. The method further includes forming an electrically conductive shield line on the substrate. The shield line is connected to a voltage reference and electrically insulated from the first pair of lines. The shield line includes a first portion disposed between the parallel portions of the first pair of lines. The first portion of the shield line extends substantially parallel to the parallel portions of the first pair of lines.

Although this invention has been described in terms of certain embodiments, other embodiments that are apparent to those of ordinary skill in the art, including embodiments that do not provide all of the features and advantages set forth herein, are also within the scope of this invention. Moreover, the various embodiments described above can be combined to provide further embodiments. In addition, certain features shown in the context of one embodiment can be incorporated into other embodiments as well. Accordingly, the scope of the present invention is defined only by reference to the appended claims.