Inventor

Todd A. Merritt

Inventor

Boise, ID, US

Overview

1993–2016

Patent span

Physics

Primary field (CPC G)

Patents· 173 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores54%

G06FElectric digital data processing9%

H10BElectronic memory devices9%

H03KPulse technique8%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%

G01RMeasuring electric variables4%

H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems3%

H10DInorganic electric semiconductor devices2%

G01HMeasurement of mechanical vibrations or ultrasonic, sonic or infrasonic waves1%

G05FSystems for regulating electric or magnetic variables1%

PatentTitleYear

9,477,636'Memory having internal processors and data communication methods in memory'2016 9,082,466'Apparatuses and methods for adjusting deactivation voltages'2015 8,743,628'Line driver circuits, methods, and apparatuses'2014 8,644,103'Circuits, systems, and methods for reducing simultaneous switching output noise, power noise, or combinations thereof'2014 8,213,244'Distributed write data drivers for burst access memories'2012 8,143,966'Coupling cancellation scheme'2012 8,107,304'Distributed write data drivers for burst access memories'2012 7,894,285'Circuits, systems, and methods for reducing simultaneous switching output noise, power noise, or combinations thereof'2011 7,830,221'Coupling cancellation scheme'2010 RE041441'Output buffer having inherently precise data masking'2010 7,681,006'Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation'2010 7,681,005'Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation'2010 7,646,654'Distributed write data drivers for burst access memories'2010 7,397,711'Distributed write data drivers for burst access memories'2008 7,376,025'Method and apparatus for semiconductor device repair with reduced number of programmable elements'2008 7,218,561'Apparatus and method for semiconductor device repair with reduced number of programmable elements'2007 7,160,795'Method and structures for reduced parasitic capacitance in integrated circuit metallizations'2007 7,142,443'Reduced data line pre-fetch scheme'2006 7,137,050'Compression circuit for testing a memory device'2006 7,124,256'Memory device for burst or pipelined operation with mode selection circuitry'2006 7,103,742'Burst/pipelined edo memory device'2006 7,099,174'Metal wiring pattern for memory devices'2006 7,095,660'Sending signal through integrated circuit during setup time'2006 7,088,625'Distributed write data drivers for burst access memories'2006 7,075,857'Distributed write data drivers for burst access memories'2006 7,043,672'Layout for a semiconductor memory device having redundant elements'2006 7,006,394'Apparatus and method for semiconductor device repair with reduced number of programmable elements'2006 7,006,393'Method and apparatus for semiconductor device repair with reduced number of programmable elements'2006 6,982,921'Multiple configuration multiple chip memory device and method'2006 6,980,478'Zero-enabled fuse-set'2005 6,950,898'Data amplifier having reduced data lines and/or higher data rates'2005 6,914,830'Distributed write data drivers for burst access memories'2005 6,909,196'Method and structures for reduced parasitic capacitance in integrated circuit metallizations'2005 6,882,590'Multiple configuration multiple chip memory device and method'2005 6,833,752'High output high efficiency low voltage charge pump'2004 6,801,076'High output high efficiency low voltage charge pump'2004 6,750,695'Voltage pump and a level translator circuit'2004 6,735,729'Compression circuit for testing a memory device'2004 6,728,142'Distributed write data drivers for burst access memories'2004 6,704,828'System and method for implementing data pre-fetch having reduced data lines and/or higher data rates'2004 6,693,844'Sending signal through integrated circuit during setup time'2004 6,664,634'Metal wiring pattern for memory devices'2003 6,654,306'Apparatus and method for generating an oscillating signal'2003 6,615,325'Method for switching between modes of operation'2003 6,587,978'Circuit and method for varying a pulse width of an internal control signal during a test mode'2003 6,577,552'Apparatus and method for generating an oscillating signal'2003 6,578,165'Internal guardband for semiconductor testing'2003 6,560,728'Layout for semiconductor memory device having a plurality of rows and columns of circuit cells divided into first and second planes that are not simultaneously active'2003 RE038109'Block write circuit and method for wide data path memory device'2003 6,556,643'Majority filter counter circuit'2003 6,545,894'Die architecture accommodating high-speed semiconductor devices'2003 6,535,999'Test and observe mode for embedded memory'2003 6,529,426'Circuit and method for varying a period of an internal control signal during a test mode'2003 6,525,971'Distributed write data drivers for burst access memories'2003 6,504,421'Voltage pump and a level translator circuit'2003 6,504,743'Die architecture accommodating high-speed semiconductor devices'2003 6,501,669'Die architecture accommodating high-speed semiconductor devices'2002 6,498,740'Die architecture accommodating high-speed semiconductor devices'2002 6,490,220'Method for reliably shutting off oscillator pulses to a charge-pump'2002 6,484,278'Method and apparatus for testing an embedded DRAM'2002 6,452,845'Apparatus for testing redundant elements in a packaged semiconductor memory device'2002 6,438,011'Die architecture accommodating high-speed semiconductor devices'2002 6,430,075'Die architecture accommodating high-speed semiconductor devices'2002 6,418,547'Internal guardband for semiconductor testing'2002 6,414,902'Use of setup time to send signal through die'2002 6,407,939'Single deposition layer metal dynamic random access memory'2002 6,385,709'Multiplexed data transfer arrangement including a multi-phase signal generator for latency control'2002 6,384,669'High voltage charge pump circuit'2002 6,381,180'Distributed write data drivers for burst access memories'2002 6,378,089'Internal guardband for semiconductor testing'2002 6,365,421'Method and apparatus for storage of test results within an integrated circuit'2002 6,363,032'Programmable counter circuit for generating a sequential/interleave address sequence'2002 6,356,487'Memory device having data path containing dual mode flip-flop used for normal operation and for internal testing'2002 6,353,549'Architecture and package orientation for high speed memory devices'2002 6,351,421'Data output buffer'2002 6,333,882'Equilibration/pre-charge circuit for a memory device'2001 6,327,167'Die architecture accommodating high-speed semiconductor devices'2001 6,320,779'Die architecture accommodating high-speed semiconductor devices'2001 6,314,012'Die architecture accommodating high-speed semiconductor devices'2001 6,307,398'Low power, high speed level shifter'2001 6,301,142'Die architecture accomodating high-speed semiconductor devices'2001 6,301,141'Die architecture accommodating high-speed semiconductor devices'2001 6,285,243'High-voltage charge pump circuit'2001 6,259,270'Semiconductor programmable test arrangement such as an antifuse ID circuit having common programming switches'2001 6,243,797'Multiplexed semiconductor data transfer arrangement with timing signal generator'2001 6,215,729'Programmable counter circuit for generating a sequential/interleave address sequence'2001 6,205,085'Method and circuit for sending a signal in a semiconductor device during a setup time'2001 6,205,078'Method and apparatus for translating signals'2001 6,197,620'Method of manufacturing a single deposition layer metal dynamic random access memory'2001 6,194,738'Method and apparatus for storage of test results within an integrated circuit'2001 6,191,616'Low power, high speed level shifter'2001 6,192,002'Memory device with command buffer'2001 6,190,972'Method for storing information in a semiconductor device'2001 6,188,239'Semiconductor programmable test arrangement such as an antifuse to ID circuit having common access switches and/or common programming switches'2001 6,185,145'Method and apparatus for translating signals'2001 6,166,942'Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines'2000 6,163,860'Layout for a semiconductor memory device having redundant elements'2000 6,154,864'Read only memory embedded in a dynamic random access memory'2000 6,144,575'Die architecture accommodating high-speed semiconductor devices'2000 6,141,286'Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines'2000 6,121,822'Charge pump circuit for generating a substrated bias'2000 6,118,711'Apparatus for testing redundant elements in a packaged semiconductor memory device'2000 6,104,643'Integrated circuit clock input buffer'2000 6,072,728'Data output buffer'2000 6,055,208'Method and circuit for sending a signal in a semiconductor device during a setup time'2000 6,055,202'Multi-bank architecture for a wide I/O DRAM'2000 6,055,172'Single deposition layer metal dynamic random access memory'2000 6,052,325'Method and apparatus for translating signals'2000 6,049,489'Methods using a data read latch circuit in a semiconductor device'2000 6,043,107'Method for producing an integrated circuit assembly'2000 6,018,811'Layout for semiconductor memory device wherein intercoupling lines are shared by two sets of fuse banks and two sets of redundant elements not simultaneously active'2000 6,011,727'Block write circuit and method for wide data path memory devices'2000 5,995,402'Die architecture accommodating high-speed semiconductor devices'1999 5,991,214'Circuit and method for varying a period of an internal control signal during a test mode'1999 5,986,944'Method and apparatus using a data read latch circuit in a semiconductor device'1999 5,986,916'On-chip program voltage generator for antifuse repair'1999 5,986,488'Method and apparatus for fast reset of a one-shot circuit'1999 5,983,314'Output buffer having inherently precise data masking'1999 5,978,302'Multi-bank architecture for a wide I/O DRAM'1999 5,978,289'Apparatus for testing redundant elements in a packaged semiconductor memory device'1999 5,963,493'Memory device communication line control'1999 5,952,845'Semiconductor programmable test arrangement such as an antifuse ID circuit having common access switches and/or common programming switches'1999 5,939,935'Charge pump'1999 5,936,893'Integrated circuit clock input buffer'1999 5,936,428'Low power, high speed level shifter'1999 5,936,877'Die architecture accommodating high-speed semiconductor devices'1999 RE036264'Read circuit for accessing dynamic random access memories (DRAMs)'1999 5,903,491'Single deposition layer metal dynamic random access memory'1999 5,895,962'Structure and a method for storing information in a semiconductor device'1999 5,880,987'Architecture and package orientation for high speed memory devices'1999 5,877,987'Method and circuit for self-latching data read lines in the data output path of a semiconductor memory device'1999 5,875,140'Memory device communication line control'1999 5,852,371'Low power, high speed level shifter'1998 5,841,714'Supervoltage circuit'1998 5,835,422'Circuit and method for generating a control signal for a memory device'1998 5,831,932'Self-enabling pulse-trapping circuit'1998 5,831,918'Circuit and method for varying a period of an internal control signal during a test mode'1998 5,828,095'Charge pump'1998 5,811,990'Voltage pump and a level translator circuit'1998 5,812,462'Integrated circuit clock input buffer'1998 5,812,488'Synchronous burst extended data out dram'1998 5,793,692'Integrated circuit memory with back end mode disable'1998 5,790,448'On-chip program voltage generator for antifuse repair'1998 5,781,486'Apparatus for testing redundant elements in a packaged semiconductor memory device'1998 5,774,412'Local word line phase driver'1998 5,757,703'Distributed write data drivers for burst access memories'1998 5,745,429'Memory having and method for providing a reduced access time'1998 5,732,036'Memory device communication line control'1998 5,723,999'Redundant row fuse bank circuit'1998 5,706,292'Layout for a semiconductor memory device having redundant elements'1998 5,706,247'Self-enabling pulse-trapping circuit'1998 5,703,813'DRAM having multiple column address strobe operation'1997 5,687,122'Data output buffer'1997 5,682,115'Active pull-up voltage spike reducer'1997 5,677,645'Vccp pump for low voltage operation'1997 5,668,773'Synchronous burst extended data out DRAM'1997 5,666,070'Low power, high speed level shifter'1997 5,657,293'Integrated circuit memory with back end mode disable'1997 5,644,538'Circuit and method for controllng the duration of pulses in a control signal from an electronic system'1997 5,640,364'Self-enabling pulse trapping circuit'1997 5,604,714'DRAM having multiple column address strobe operation'1997 5,604,693'On-chip program voltage generator for antifuse repair'1997 5,598,376'Distributed write data drivers for burst access memories'1997 5,586,080'Local word line phase driver'1996 5,583,463'Redundant row fuse bank circuit'1996 5,528,173'Low power, high speed level shifter'1996 5,525,926'Active pull-up voltage spike reducer'1996 5,513,140'Data output buffer'1996 5,455,801'Circuit having a control array of memory cells and a current source and a method for generating a self-refresh timing signal'1995 5,444,408'Active pull-up voltage spike reducer'1995 5,349,566'Memory device with pulse circuit for timing data output, and method for outputting data'1994 5,331,593'Read circuit for accessing dynamic random access memories (DRAMS)'1994 5,245,577'Integrated circuit two-cycle test mode activation circuit'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2016Patents assigned to MICRON TECHNOLOGY INC (165)· patent assignee history

1993–2016Based in Boise, ID, US· patent location history

1994–1995Patents assigned to MICRON SEMICONDUCTOR INC (3)· patent assignee history

2012–2016Patents assigned to MERRITT TODD A (4)· patent assignee history

2012Patents assigned to MANNING TROY A (2)· patent assignee history

2012–2014Patents assigned to MERRITT TODD (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	165	1993–2016
MERRITT TODD Aself	4	2012–2016
MICRON SEMICONDUCTOR INC	3	1994–1995
MANNING TROY A	2	2012
MERRITT TODDself	2	2012–2014

Locations

Location	Patents	Span
Boise, ID, US	173	1993–2016