Latchup robust gate array using through wafer via

The present invention relates to the field of integrated circuits; more specifically, it relates to gate array structures and method of making gate arrays latchup robust.

In modern integrated circuits, gate arrays comprising p-channel field effect transistors (PFETs) and n-channel field effect transistors (NFETs) can be susceptible to latchup. Latch-up causes Metal-Oxide-Silicon FETs (MOSFETs) to consume large amounts of current overheating and destroying the integrated circuit in which latchup occurs. Existing methods for reducing this propensity to complementary MOS (CMOS) latchup have become increasingly less effective as doping levels of the substrates of integrated circuits have decreased. Therefore there is a need in the industry for more robust latchup preventive structures and methods for preventing latchup for gate arrays in integrated circuit chips.

A first aspect of the present invention is a structure, comprising: a P-well and an N-well formed in a semiconductor substrate, the P-well extending from a top surface of the substrate into the substrate a first distance, the N-well extending from the top surface of the substrate into the substrate a second distance; dielectric isolation extending from the top surface of the substrate into the substrate a third distance, the first, second and third distances less than a whole distance between the top and bottom surfaces of the substrate, the first and second distances greater than the third distances, the P-well abutting a bottom surface of the dielectric isolation and the N-well abutting the bottom surface of the dielectric isolation where the dielectric isolation extends into the N-well and the P-well; an array of spaced apart first gate electrodes positioned over the P-well, a first set of source/drains formed in the P-well between the first gate electrodes; an array of spaced apart second gate electrodes positioned over the N-well, a set of second source/drains formed in the N-well between the second gate electrodes; and an electrically conductive through via extending from the bottom surface of the substrate into the substrate a fourth distance, the fourth distance less than the whole distance, the through via contacting the P-well and abutting the bottom surface of shallow trench isolation that extends into the P-well.

A second aspect of the present invention is a method, comprising: forming a P-well and an N-well in a semiconductor substrate, the P-well extending from a top surface of the substrate into the substrate a first distance, the N-well extending from the top surface of the substrate into the substrate a second distance; forming dielectric isolation in the substrate, the dielectric isolation extending from the top surface of the substrate into the substrate a third distance, the first, second and third distances less than a whole distance between the top and bottom surfaces of the substrate, the first and second distances greater than the third distances, the P-well abutting a bottom surface of the dielectric isolation and the N-well abutting the bottom surface of the dielectric isolation where the dielectric isolation extends into the N-well and the P-well; forming an array of spaced apart first gate electrodes positioned over the P-well, a first set of source/drains formed in the P-well between the first gate electrodes; forming an array of spaced apart second gate electrodes positioned over the N-well, a set of second source/drains formed in the N-well between the second gate electrodes; and forming an electrically conductive through via extending from the bottom surface of the substrate into the substrate a fourth distance, the fourth distance less than the whole distance, the through via contacting the P-well and abutting the bottom surface of shallow trench isolation that extends into the P-well.

The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a plan view of an gate array according to embodiments of the present invention;

FIG. 2 is a cross-section through line 2 - 2 of FIG. 1 ; and

FIG. 3 is a cross-section through line 3 - 3 of FIG. 1 .

Latchup is defined as the triggering of a parasitic structure which then acts as a short circuit creating a low impedence path between the power supply rails and an electrical component.

FIG. 1 is a plan view of a gate array according to embodiments of the present invention. In FIG. 1 , formed in a substrate 100 is a gate array 105 . Gate array 105 is surrounded by shallow trench isolation (STI) 110 (heavy lines). Gate array 105 includes a PFET gate array 115 and an NFET gate array 120 . It should be understood that a “gate array” includes at least one PFET device, and one NFET device, whereas a “PFET gate array” includes one or more PFET devices, and whereas a “NFET gate array” includes at least one or more NFET devices, where spatially the PFET device or gate array and the NFET device or gate array are in proximate to each other. PFET gate array 115 includes an N-well 125 , source drains 130 formed in the N-well and an N-well contact 135 to the N-well. NFET gate array 120 includes a P-well 140 , source drains 145 formed in the P-well and a P-well contact 150 to the P-well. An array of gate electrodes 155 is common to both PFET gate array 115 and NFET gate array 120 . When substrate 100 is P-type, P-well contact 150 is also a substrate contact. It should be noted that N-well contact 135 and P-well contact 150 on located on opposing sides of gate array 105 to allow compact layout of gate electrodes 155 . An electrically conductive through via 160 contacts P-well 140 and STI 110 (see FIG. 3 and description infra).

Alternatively, a first array of gates may be positioned over N-well 125 and a second array of gates, not physically attached to the first array of gates, may be positioned over P-well 140 , instead of common gates 155 .

FIG. 2 is a cross-section through line 2 - 2 of FIG. 1 . In FIG. 2 , source/drains 145 are separated by channel regions of P-well 140 under gate electrodes 155 and gate dielectric 165 intervenes between the gate electrodes 155 and these channel regions. A top surface of STI 110 is coplanar with a top surface 170 of substrate 100 . P-well 140 abuts a bottom surface 185 of STI 110 . Formed on a bottom surface 175 of substrate 100 is an optional electrically conductive layer 180 . The structure of PFET array 115 is similar with P-well 140 being replaced with N-well 125 (see FIG. 1 ) and source/drains 145 being replaced with source/drains 130 (see FIG. 1 ).

FIG. 3 is a cross-section through line 3 - 3 of FIG. 1 . In FIG. 3 , through via 160 extends from bottom surface 180 , through substrate 100 , through P-well 140 to abut a bottom surface 185 of the region of STI 110 between PFET gate array 115 and NFET gate array 120 . Either an electrically conductive contact, which may be ohmic (e.g., having resistance of about 1 ohm or less) or a Schottky diode is formed at the interface of through vias 160 and P-Well 140 . Conductive layer 180 provides a low-resistance contact to through via 160 . Through via 160 prevents latchup by preventing formation of a parasitic lateral PNPN device comprising source/drains 130 and 145 (see FIGS. 1 and 2 ) P-well 140 and N-well 125 . Through via 160 eliminates the regenerative feedback between the PNP and NPN portions of the PNPN device through substrate 100 . In FIG. 3 , through via 160 does not touch N-well 125 .

In one example, through via 160 comprises doped polysilicon, one or more refractory metals examples of which include tungsten, titanium and tantalum, or combinations thereof. In one example, conductive layer 180 comprises doped polysilicon, aluminum, platinum, nickel, cobalt, a metal silicide, one or more refractory metals examples of which include tungsten, titanium and tantalum, or combinations thereof.

It should be understood, that substrate 100 may be P or N-type and through via 160 may formed through N-well 125 instead of P-Well 140 (see FIG. 3 ).

Thus, the embodiments of the present invention provide more robust latchup preventive structures and methods for preventing latchup for gate arrays in integrated circuit chips.

The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.