Inventor

Steven H. Voldman

Inventor

South Burlington, VT, US

Overview

1995–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 265 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices46%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%

G06FElectric digital data processing4%

G11BInformation storage based on relative movement between record carrier and transducer3%

H01LSemiconductor devices3%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

Y10TTechnical subjects covered by former us classification3%

H03KPulse technique2%

H10BElectronic memory devices2%

PatentTitleYear

10,978,452Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry2021 10,615,260Method for forming FinFET device structure2020 10,170,476Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry2019 10,038,058FinFET device structure and method for forming same2018 9,842,838'Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry'2017 9,397,010'Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry'2016 9,275,997'Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry'2016 9,087,925'Si and SiGeC on a buried oxide layer on a substrate'2015 8,994,026'Structure, structure and method of latch-up immunity for high and low voltage integrated circuits'2015 8,962,480'ESD network circuit with a through wafer via structure and a method of manufacture'2015 8,963,158'Structure, structure and method of latch-up immunity for high and low voltage integrated circuits'2015 8,946,013'Lateral diffusion field effect transistor with drain region self-aligned to gate electrode'2015 8,859,337'Thermal matching in semiconductor devices using heat distribution structures'2014 8,853,789'Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry'2014 8,847,317'Isolated epitaxial modulation device'2014 8,519,402'Structure, structure and method of latch-up immunity for high and low voltage integrated circuits'2013 8,487,379'Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications'2013 8,423,936'Semiconductor structure and method of designing semiconductor structure to avoid high voltage initiated latch-up in low voltage sectors'2013 8,420,518'Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry'2013 8,410,534'Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact'2013 8,390,074'Structure and method for latchup improvement using through wafer via latchup guard ring'2013 8,362,564'Isolated epitaxial modulation device'2013 8,301,288'Optimized scheduling based on sensitivity data'2012 8,232,625'ESD network circuit with a through wafer via structure and a method of manufacture'2012 8,227,318'Integration of multiple gate oxides with shallow trench isolation methods to minimize divot formation'2012 8,193,563'High power device isolation and integration'2012 8,188,570'Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications'2012 8,178,925'Semiconductor diode structure operation method'2012 8,171,435'Integrated circuit structure incorporating an inductor, an associated design method and an associated design system'2012 8,143,671'Lateral trench FETs (field effect transistors)'2012 8,138,579'Structures and methods of forming SiGe and SiGeC buried layer for SOI/SiGe technology'2012 8,129,772'Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact'2012 8,114,750'Lateral diffusion field effect transistor with drain region self-aligned to gate electrode'2012 8,110,875'Structure for charge dissipation during fabrication of integrated circuits and isolation thereof'2012 8,110,853'Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication'2012 8,108,822'Methodology for placement based on circuit function and latchup sensitivity'2012 8,108,817'Semiconductor structure and method of designing semiconductor structure to avoid high voltage initiated latch-up in low voltage sectors'2012 8,105,924'Deep trench based far subcollector reachthrough'2012 8,088,656'Fabricating ESD devices using MOSFET and LDMOS'2012 8,054,597'Electrostatic discharge structures and methods of manufacture'2011 8,044,510'Product and method for integration of deep trench mesh and structures under a bond pad'2011 8,035,190'Semiconductor devices'2011 8,017,471'Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry'2011 8,017,995'Deep trench semiconductor structure and method'2011 8,015,538'Design structure with a deep sub-collector, a reach-through structure and trench isolation'2011 8,015,518'Structures for electrostatic discharge protection for bipolar semiconductor circuitry'2011 7,989,282'Structure and method for latchup improvement using through wafer via latchup guard ring'2011 7,989,306'Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate'2011 7,977,714'Wrapped gate junction field effect transistor'2011 7,956,412'Lateral diffusion field effect transistor with a trench field plate'2011 7,949,983'High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature'2011 7,943,437'Apparatus and method for electronic fuse with improved ESD tolerance'2011 7,886,240'Modifying layout of IC based on function of interconnect and related circuit and design structure'2011 7,876,547'Vertical parallel plate capacitor structures'2011 7,872,334'Carbon nanotube diodes and electrostatic discharge circuits and methods'2011 7,855,420'Structure for a latchup robust array I/O using through wafer via'2010 7,855,104'Structure and method for latchup suppression'2010 7,842,580'Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications'2010 7,821,099'Structure for low capacitance ESD robust diodes'2010 7,807,562'Dendrite growth control circuit'2010 7,800,184'Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact'2010 7,781,292'High power device isolation and integration'2010 7,755,161'Semiconductor devices'2010 7,750,408'Integrated circuit structure incorporating an inductor, a conductive sheet and a protection circuit'2010 7,741,681'Latchup robust array I/O using through wafer via'2010 7,732,293'Tunable semiconductor diodes'2010 7,732,835'Vertical P-N junction device and method of forming same'2010 7,718,481'Semiconductor structure and method of manufacture'2010 7,709,924'Semiconductor diode structures'2010 7,709,930'Tuneable semiconductor device with discontinuous portions in the sub-collector'2010 7,705,426'Integration of a SiGe- or SiGeC-based HBT with a SiGe- or SiGeC-strapped semiconductor device'2010 7,696,541'Structure for a latchup robust gate array using through wafer via'2010 7,698,678'Methodology for automated design of vertical parallel plate capacitors'2010 7,691,734'Deep trench based far subcollector reachthrough'2010 7,671,423'Resistor ballasted transistors'2010 7,606,013'Electro-static discharge protection circuit'2009 7,582,949'Semiconductor devices'2009 7,560,778'Charge modulation network for multiple power domains for silicon-on-insulator technology'2009 7,549,135'Design methodology of guard ring design resistance optimization for latchup prevention'2009 7,541,247'Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication'2009 7,538,409'Semiconductor devices'2009 7,535,105'Inter-chip ESD protection structure for high speed and high frequency devices'2009 7,521,359'Interconnect structure encased with high and low k interlevel dielectrics'2009 7,498,622'Latchup robust gate array using through wafer via'2009 7,485,965'Through via in ultra high resistivity wafer and related methods'2009 7,482,258'Product and method for integration of deep trench mesh and structures under a bond pad'2009 7,477,497'Apparatus for electrostatic discharge protection of bipolar emitter follower circuits'2009 7,473,643'Dendrite growth control circuit'2009 7,459,367'Method of forming a vertical P-N junction device'2008 7,445,966'Method and structure for charge dissipation during fabrication of integrated circuits and isolation thereof'2008 7,442,996'Structure and method for enhanced triple well latchup robustness'2008 7,439,145'Tunable semiconductor diodes'2008 7,427,551'High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature'2008 7,411,305'Interconnect structure encased with high and low k interlevel dielectrics'2008 7,401,311'Methodology for placement based on circuit function and latchup sensitivity'2008 7,384,854'Method of forming low capacitance ESD robust diodes'2008 7,358,572'Radiation tolerant electrostatic discharge protection networks'2008 7,348,251'Modulated trigger device'2008 7,348,657'Electrostatic discharge protection networks for triple well semiconductor devices'2008 7,350,160'Method of displaying a guard ring within an integrated circuit'2008 7,334,320'Method of making an electronic fuse with improved ESD tolerance'2008 7,309,898'Method and apparatus for providing noise suppression in an integrated circuit'2007 7,303,968'Semiconductor device and method having multiple subcollectors formed on a common wafer'2007 7,282,771'Structure and method for latchup suppression'2007 7,242,071'Semiconductor structure'2007 7,202,136'Silicon germanium heterojunction bipolar transistor with carbon incorporation'2007 7,200,825'Methodology of quantification of transmission probability for minority carrier collection in a semiconductor chip'2007 7,173,310'Lateral lubistor structure and method'2007 7,166,904'Structure and method for local resistor element in integrated circuit technology'2007 7,138,701'Electrostatic discharge protection networks for triple well semiconductor devices'2006 7,138,669'Silicon germanium heterojunction bipolar transistor with carbon incorporation'2006 7,136,268'Tunable ESD trigger and power clamp circuit'2006 7,134,099'ESD design, verification and checking system and method of use'2006 7,129,545'Charge modulation network for multiple power domains for silicon-on-insulator technology'2006 7,119,401'Tunable semiconductor diodes'2006 7,109,584'Dendrite growth control circuit'2006 7,106,164'Apparatus and method for electronic fuse with improved ESD tolerance'2006 7,102,867'Method, apparatus and circuit for latchup suppression in a gate-array ASIC environment'2006 7,089,520'Methodology for placement based on circuit function and latchup sensitivity'2006 7,067,914'Dual chip stack method for electro-static discharge protection of integrated circuits'2006 7,064,416'Semiconductor device and method having multiple subcollectors formed on a common wafer'2006 7,041,581'Method and structure for improving latch-up immunity using non-dopant implants'2006 7,020,857'Method and apparatus for providing noise suppression in a integrated circuit'2006 6,996,786'Latch-up analysis and parameter modification'2006 6,975,015'Modulated trigger device'2005 6,969,903'High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature'2005 6,956,266'Structure and method for latchup suppression utilizing trench and masked sub-collector implantation'2005 6,946,707'Electrostatic discharge input and power clamp circuit for high cutoff frequency technology radio frequency (RF) applications'2005 6,943,578'Method and application of PICA (picosecond imaging circuit analysis) for high current pulsed phenomena'2005 6,895,372'System and method for VLSI visualization'2005 6,891,207'Electrostatic discharge protection networks for triple well semiconductor devices'2005 6,878,976'Carbon-modulated breakdown voltage SiGe transistor for low voltage trigger ESD applications'2005 6,838,323'Diffusion resistor/capacitor (DRC) non-aligned MOSFET structure'2005 6,826,025'Method and apparatus for providing ESD protection and/or noise reduction in an integrated circuit'2004 6,774,017'Method and structures for dual depth oxygen layers in silicon-on-insulator processes'2004 6,762,918'Fault free fuse network'2004 6,750,109'Halo-free non-rectifying contact on chip with halo source/drain diffusion'2004 6,746,947'Post-fuse blow corrosion prevention structure for copper fuses'2004 6,731,488'Dual emitter transistor with ESD protection'2004 6,725,439'Method of automated design and checking for ESD robustness'2004 6,720,637'SiGe transistor, varactor and p-i-n velocity saturated ballasting element for BiCMOS peripheral circuits and ESD networks'2004 6,710,983'ESD protection for GMR sensors of magnetic heads using SiGe integrated circuit devices'2004 6,704,179'Automated hierarchical parameterized ESD network design and checking system'2004 6,700,164'Tungsten hot wire current limiter for ESD protection'2004 6,680,520'Method and structure for forming precision MIM fusible circuit elements using fuses and antifuses'2004 6,670,654'Silicon germanium heterojunction bipolar transistor with carbon incorporation'2003 6,635,548'Capacitor and method for forming same'2003 6,628,159'SOI voltage-tolerant body-coupled pass transistor'2003 6,600,199'Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity'2003 6,586,818'Self-aligned silicon germanium heterojunction bipolar transistor device with electrostatic discharge crevice cover for salicide displacement'2003 6,574,078'Method and apparatus for providing electrostatic discharge protection of a magnetic head using a mechanical switch and an electrostatic discharge device network'2003 6,563,176'Asymmetrical semiconductor device for ESD protection'2003 6,552,406'SiGe transistor, varactor and p-i-n velocity saturated ballasting element for BiCMOS peripheral circuits and ESD networks'2003 6,552,879'Variable voltage threshold ESD protection'2003 6,548,338'Integrated high-performance decoupling capacitor and heat sink'2003 6,549,061'Electrostatic discharge power clamp circuit'2003 6,531,741'Dual buried oxide film SOI structure and method of manufacturing the same'2003 6,526,548'Method for evaluating circuit design for ESD electrostatic discharge robustness'2003 6,512,296'Semiconductor structure having heterogenous silicide regions having titanium and molybdenum'2003 6,498,385'Post-fuse blow corrosion prevention structure for copper fuses'2002 6,476,445'Method and structures for dual depth oxygen layers in silicon-on-insulator processes'2002 6,465,870'ESD robust silicon germanium transistor with emitter NP-block mask extrinsic base ballasting resistor with doped facet region'2002 6,455,902'BiCMOS ESD circuit with subcollector/trench-isolated body mosfet for mixed signal analog/digital RF applications'2002 6,455,919'Internally ballasted silicon germanium transistor'2002 6,441,410'MOSFET with lateral resistor ballasting'2002 6,441,462'Self-aligned SiGe NPN with improved ESD robustness using wide emitter polysilicon extension'2002 6,433,609'Double-gate low power SOI active clamp network for single power supply and multiple power supply applications'2002 6,433,985'ESD network with capacitor blocking element'2002 6,432,809'Method for improved passive thermal flow in silicon on insulator devices'2002 6,429,066'Method for producing a polysilicon circuit element'2002 6,429,489'Electrostatic discharge power clamp circuit'2002 6,429,482'Halo-free non-rectifying contact on chip with halo source/drain diffusion'2002 6,429,045'Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage'2002 6,426,244'Process of forming a thick oxide field effect transistor'2002 6,420,761'Asymmetrical semiconductor device for ESD protection'2002 6,420,766'Transistor having raised source and drain'2002 6,411,480'Substrate pumped ESD network with trench structure'2002 6,410,962'Structure for SOI wafers to avoid electrostatic discharge'2002 6,404,269'Low power SOI ESD buffer driver networks having dynamic threshold MOSFETS'2002 6,404,275'Modified current mirror circuit for BiCMOS application'2002 6,396,107'Trench-defined silicon germanium ESD diode network'2002 6,387,742'Thermal conductivity enhanced semiconductor structures and fabrication processes'2002 6,384,468'Capacitor and method for forming same'2002 6,380,570'Gate overvoltage control networks'2002 6,369,994'Method and apparatus for handling an ESD event on an SOI integrated circuit'2002 6,359,750'Data storage system with TiC MR-head magnetic shield dummy shield spark gap'2002 6,352,905'Method and structure of high and low K buried oxide for SOI technology'2002 6,331,726'SOI voltage dependent negative-saturation-resistance resistor ballasting element for ESD protection of receivers and driver circuitry'2001 6,323,522'Silicon on insulator thick oxide structure and process of manufacture'2001 6,294,419'Structure and method for improved latch-up using dual depth STI with impurity implant'2001 6,292,343'ASIC book to provide ESD protection on an integrated circuit'2001 6,288,426'Thermal conductivity enhanced semiconductor structures and fabrication processes'2001 6,288,880'Method of making TiC MR-head magnetic shield dummy shield spark gap'2001 6,281,593'SOI MOSFET body contact and method of fabrication'2001 6,268,286'Method of fabricating MOSFET with lateral resistor with ballasting'2001 6,262,873'Method for providing ESD protection for an integrated circuit'2001 6,256,184'Method and apparatus for providing electrostatic discharge protection'2001 6,255,178'Method for forming transistors with raised source and drains and device formed thereby'2001 6,245,600'Method and structure for SOI wafers to avoid electrostatic discharge'2001 6,236,103'Integrated high-performance decoupling capacitor and heat sink'2001 6,232,163'Method of forming a semiconductor diode with depleted polysilicon gate structure'2001 6,232,639'Method and structure to reduce latch-up using edge implants'2001 6,229,372'Active clamp network for multiple voltages'2001 6,218,704'ESD protection structure and method'2001 6,198,136'Support chips for buffer circuits'2001 6,187,617'Semiconductor structure having heterogeneous silicide regions and method for forming same'2001 6,171,918'Depleted poly mosfet structure and method'2001 6,166,420'Method and structure of high and low K buried oxide for SoI technology'2000 6,157,530'Method and apparatus for providing ESD protection'2000 6,144,086'Structure for improved latch-up using dual depth STI with impurity implant'2000 6,136,656'Method to create a depleted poly MOSFET'2000 6,118,155'Integrated ESD structures for use in ESD circuitry'2000 6,100,143'Method of making a depleted poly-silicon edged MOSFET structure'2000 6,100,013'Method for forming transistors with raised source and drains and device formed thereby'2000 6,096,584'Silicon-on-insulator and CMOS-on-SOI double film fabrication process with a coplanar silicon and isolation layer and adding a second silicon layer on one region'2000 6,097,068'Semiconductor device fabrication method and apparatus using connecting implants'2000 6,097,069'Method and structure for increasing the threshold voltage of a corner device'2000 6,086,627'Method of automated ESD protection level verification'2000 6,081,409'TiC MR-head magnetic shield dummy shield spark gap'2000 6,075,399'Switchable active clamp network'2000 6,074,899'3-D CMOS-on-SOI ESD structure and method'2000 6,071,803'Electrical contact to buried SOI structures'2000 6,057,184'Semiconductor device fabrication method using connecting implants'2000 6,049,445'Overvoltage and electrostatic discharge protection for a receiver circuit'2000 6,033,949'Method and structure to reduce latch-up using edge implants'2000 6,034,388'Depleted polysilicon circuit element and method for producing the same'2000 6,034,397'Silicon-on-insulator body- and dual gate-coupled diode for electrostatic discharge (ESD) applications'2000 6,015,993'Semiconductor diode with depleted polysilicon gate structure and method'2000 5,998,848'Depleted poly-silicon edged MOSFET structure and method'1999 5,952,695'Silicon-on-insulator and CMOS-on-SOI double film structures'1999 5,945,713'Electrostatic discharge protection circuits for mixed voltage interface and multi-rail disconnected power grid applications'1999 5,943,254'Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes'1999 5,939,767'Structure and process for buried diode formation in CMOS'1999 5,930,098'Multichip semiconductor structures with interchip electrostatic discharge protection, and fabrication methods therefore'1999 5,923,067'3-D CMOS-on-SOI ESD structure and method'1999 5,894,230'Modified keeper half-latch receiver circuit'1999 5,889,293'Electrical contact to buried SOI structures'1999 5,882,967'Process for buried diode formation in CMOS'1999 5,872,378'Dual thin oxide ESD network for nonvolatile memory applications'1999 5,867,888'Magnetic head/silicon chip integration method'1999 5,861,330'Method and structure to reduce latch-up using edge implants'1999 5,811,857'Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications'1998 5,807,791'Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes'1998 5,789,964'Decoupling capacitor network for off-state operation'1998 5,786,237'Method for forming a monolithic electronic module by stacking planar arrays of integrated circuit chips'1998 5,777,829'Method and apparatus for providing electrostatic discharge protection for an inductive coil of a magnetic transducer'1998 5,771,571'Method for manufacturing thin film slider with on-board multi-layer integrated circuit'1998 5,761,009'Having parastic shield for electrostatic discharge protection'1998 5,731,941'Electrostatic discharge suppression circuit employing trench capacitor'1998 5,731,945'Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes'1998 5,712,747'Thin film slider with on-board multi-layer integrated circuit'1998 5,710,682'Electrostatic discharge protection system for MR heads'1998 5,703,747'Multichip semiconductor structures with interchip electrostatic discharge protection, and fabrication methods therefore'1997 5,656,553'Method for forming a monolithic electronic module by dicing wafer stacks'1997 5,654,221'Method for forming semiconductor chip and electronic module with integrated surface interconnects/components'1997 5,644,454'Electrostatic discharge protection system for MR heads'1997 5,637,912'Three-dimensional monolithic electronic module having stacked planar arrays of integrated circuit chips'1997 5,629,544'Semiconductor diode with silicide films and trench isolation'1997 5,625,280'Voltage regulator bypass circuit'1997 5,610,791'Power sequence independent electrostatic discharge protection circuits'1997 5,587,857'Silicon chip with an integrated magnetoresistive head mounted on a slider'1996 5,559,051'Process for manufacturing a silicon chip with an integrated magnetoresistive head mounted on a slider'1996 5,521,434'Semiconductor chip and electronic module with integrated surface interconnects/components'1996 5,521,115'Method of making double grid substrate plate DRAM cell array'1996 5,384,474'Double grid substrate plate trench'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–2021Patents assigned to IBM (259)· patent assignee history

1995–2010Based in Burlington, VT, US· patent location history

1997–2021Based in South Burlington, VT, US· patent location history

2012–2015Patents assigned to VOLDMAN STEVEN H (20)· patent assignee history

2012–2014Patents assigned to VOLDMAN STEVEN HOWARD (8)· patent assignee history

2012–2015Patents assigned to LIU XUEFENG (4)· patent assignee history

2012–2015Patents assigned to RASSEL ROBERT M (4)· patent assignee history

2012Based in Essex Junction, VT, US· patent location history

2018–2020Based in Lake Placid, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	259	1995–2021
VOLDMAN STEVEN Hself	20	2012–2015
VOLDMAN STEVEN HOWARDself	8	2012–2014
LIU XUEFENG	4	2012–2015
RASSEL ROBERT M	4	2012–2015

Locations

Location	Patents	Span
South Burlington, VT, US	231	1997–2021
Burlington, VT, US	29	1995–2010
Essex Junction, VT, US	3	2012
Lake Placid, New York, US	2	2018–2020