Current mode half-bridge power converter

The invention is generally directed to the area of power conversion. The invention is directed, particularly, but not exclusively to the current mode control of half-bridge power converters.

Power converters and power converter controllers may employ either voltage mode control or current mode control. Voltage mode control can be implemented through simple circuit topologies and provides good noise immunity. Voltage mode control generally entails a second order system. Current mode control generally entails more complex circuit topology. However, current mode control typically directly senses the current through an output inductor. Thus, current mode control can provide faster response to changes in output current.

Half-bridge power converters may be employed to provide efficient power conversion. In particular, half-bridge power converters are suited for efficiently powering loads which require substantial current. However, input capacitor stabilization considerations complicate the implementation of current mode half-bridge power converters.

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings. In the drawings, like reference numerals refer to like parts throughout the various figures unless otherwise specified. These drawings are not necessarily drawn to scale.

For a better understanding of the present invention, reference will be made to the following Detailed Description, which is to be read in association with the accompanying drawings, wherein:

FIG. 1 is a block diagram of an embodiment of a power converter according to aspects of the present invention;

FIG. 2 is a schematic diagram of an embodiment of the power converter of FIG. 1 according to aspects of the present invention;

FIG. 3 is a schematic diagram of an embodiment of a pulse logic circuit of FIG. 2 according to aspects of the present invention;

FIGS. 4A-4J are timing diagrams illustrating waveforms of embodiments of signals for an embodiment of the pulse logic circuit of FIG. 3 ;

FIG. 5 is a schematic diagram of an embodiment of a current sense circuit of FIG. 2 according to aspects of the present invention;

FIG. 6 is a schematic diagram of an embodiment of a rectification circuit of FIG. 2 according to aspects of the present invention;

FIG. 7 is a schematic diagram of another embodiment of an error circuit of FIG. 1 according to aspects of the present invention;

FIG. 8 is a schematic diagram of another embodiment of a stabilization circuit of FIG. 1 according to aspects of the present invention; and

FIG. 9 is a schematic diagram of another embodiment of a pulse modulation circuit of FIG. 1 according to aspects of the present invention.

Various embodiments of the present invention will be described in detail with reference to the drawings. Reference to various embodiments does not limit the scope of the invention, which is limited only by the scope of the claims attached hereto. Additionally, any examples set forth in this specification are not intended to be limiting and merely set forth some of the many possible embodiments for the claimed invention.

Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context dictates otherwise. The meanings identified below do not necessarily limit the terms, but merely provide illustrative examples for the terms. The meaning of “a,” “an,” and “the” includes plural reference. References in the singular are made merely for clarity of reading and include plural reference unless plural reference is specifically excluded. The meaning of either “in” or “on” includes both “in” and “on.” The term “or” is an inclusive “or” operator, and is equivalent to the term “and/or” unless specifically indicated otherwise. The term “based on” or “based upon” is not exclusive and is equivalent to the term “based, at least in part, on” and includes being based on additional factors, some of which are not described herein. The term “coupled” means at least either a direct electrical connection between the items connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means at least either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function or functions. The term “signal” means at least one current, voltage, charge, temperature, data, or other signal. A “signal” may be used to communicate using active high, active low, time multiplexed, synchronous, asynchronous, differential, single-ended, or any other digital or analog signaling or modulation techniques. Where either a field effect transistor (FET) or a bipolar transistor may be employed as an embodiment of a transistor, the scope of the words “gate”, “drain”, and “source” includes “base”, “collector”, and “emitter”, respectively, and vice versa. The phrase “in one embodiment,” as used herein does not necessarily refer to the same embodiment, although it may.

Briefly stated, the invention relates to a half-bridge power converter controller that employs current mode control. The power converter controller includes pulse modulation circuitry, error circuitry, and stabilization circuitry. The stabilization circuitry stabilizes the voltage at the mid- point of a half-bridge power converter input capacitor circuit. The input capacitor circuit mid-point voltage is stabilized by selectively adjusting the on-times of the high-side switch and low-side switch of a half-bridge power converter. This adjustment tailors the current that is provided to the input capacitor circuit and thus maintains the mid-point voltage near a desired value.

FIG. 1 is a block diagram of an embodiment of power converter 190 . Power converter 190 includes switch circuit 192 , current sense circuit 194 , input capacitor circuit 196 , transformer T 1 , rectifier circuit 198 , and power converter controller 100 . Power converter 190 is arranged as a current mode half-bridge power converter. In one embodiment, power converter 190 is arranged to provide a substantially stable output voltage Vout from input voltage Vin.

Switch circuit 192 is arranged to selectively couple voltage supply Vin or ground to node N 1 under the control of switch control signals HO and LO. For example, node N 1 may be coupled to voltage supply Vin while switch control signal HO is asserted, and node N 1 may be coupled to ground while switch control signal LO is asserted. In other embodiments, switch circuit 192 may be arranged to selectively provide other voltages to node N 1 . For example, these other voltage supplies may provide positive or negative voltages.

Current sense circuit 194 is arranged to provide current sense signal I_sns to power converter controller 100 . In one embodiment, current sense circuit 194 is arranged to provide current sense signal I_sns based, at least in part, on an output current of switch circuit 192 . Current sense circuit 194 may include a current sense resistor, a current sense amplifier, filtering circuitry, and/or the like. In one embodiment, current sense circuit 194 also provides a relatively low impedance path between nodes N 1 and N 2 . In another embodiment, nodes N 1 and N 2 are, in fact, a single node.

Input capacitor circuit 196 includes capacitors C 1 and C 2 and is arranged to provide a voltage of approximately ½Vin to the primary coil of transformer T 1 at node N 3 . In addition, capacitor sense signal CAP_sns is provided to power converter controller 100 based, at least in part, on the capacitor circuit mid-point voltage at node N 3 . In one embodiment, input capacitor circuit 196 provides a bias such that the magnitude of voltage across the primary coil of transformer T 1 is approximately equal to ½Vin when switch circuit 192 initially couples either Vin or ground to node N 1 . Capacitors C 1 and C 2 may be of any types or values that are suitable for power converters.

Transformer T 1 may be any transformer that is suitable for half-bridge power conversion. In one embodiment, transformer T 1 is arranged to provide power to rectifier circuit 198 based, at least in part, on the changing current through the primary coil of transformer T 1 .

Rectifier circuit 198 is arranged to rectify the output of transformer T 1 to provide output voltage Vout. In one embodiment, error sense signal ERR_sns is also provided by rectifier circuit 198 based, at least in part, on the value of output voltage Vout. Error signal ERR_sns may be provided directly from output voltage Vout, via a buffer, via a voltage follower, via a voltage divider, and/or the like, and combinations thereof.

Power converter controller 100 is arranged to control the conversion of input voltage Vin to output voltage Vout and includes error circuit 110 , stabilization circuit 120 , and pulse modulation circuit 130 . Power converter controller 100 is further arranged to receive current sense signal I_sns, capacitor sense signal CAP_sns, and error sense signal ERR_sns and to provide switch control signals HO and LO to control power conversion and to maintain a mid-point voltage at node N 3 .

Error circuit 110 is arranged to receive error sense signal ERR_sns and reference voltage Vref. Error circuit 110 is further arranged to provide error signals HO_er and LO_er based, at least in part, on a difference between error sense signal ERR_sns and reference voltage Vref. Reference voltage Vref may be of any suitable value and may be provided by an external reference source or may be internally generated. For example, band-gap reference circuits, Zener diodes, digital-to-analog converters, and/or the like, may be suitably employed. In one embodiment, reference voltage Vref is provided by an internal band-gap circuit.

Stabilization circuit 120 is arranged to stabilize the midpoint voltage at node N 3 of input capacitor circuit 196 . In one embodiment, stabilization circuit 120 is arranged to receive capacitor sense signal CAP_sns and input voltage Vin and to provide stabilization signals HO_st and LO_st. For example, stabilization signals HO_st and LO_st may be provided based, at least in part, on a difference between capacitor sense signal CAP_sns and a predetermined value. For example, the predetermined value may be related to input voltage Vin. In one embodiment, the predetermined value is approximately equal to ½Vin.

Pulse modulation circuit 130 is arranged to provide switch control signals HO and LO to control the switching of switch circuit 192 . Switch control signals HO and LO are provided based, at least in part, on current sense signal I_sns, error signals HO_er and LO_er, and stabilization signals HO_st, and LO_st. Pulse modulation circuit 130 may perform pulse width modulation (PWM), pulse frequency modulation (PFM), and/or the like. In addition, pulse modulation circuit 130 may include PWM logic circuitry, PFM logic circuitry, pulse modulation comparators, clock sources, and/or the like, and combinations thereof.

FIG. 2 is a schematic diagram of an embodiment of power converter 290 . Power converter 290 may be employed as an embodiment of power converter 190 of FIG. 1 .

In one embodiment, switch circuit 292 includes N-channel MOSFET switching devices M 1 and M 2 . However, in other embodiments, P-channel MOSFET devices, BJT transistors, JFET transistors, relays, other electronically controlled switching devices, and/or the like, may be suitably employed. These variations are within the spirit and scope of the invention. Switch circuit 292 is also arranged to selectively couple voltage supply Vin or ground to node N 1 under the control of switch control signals HO and LO.

Error circuit 210 of power converter controller 200 includes error amplifier AMP 3 , resistors Rcomp and R 20 -R 22 , capacitor Ccomp, and transistors Q 20 -Q 22 . In one embodiment, error amplifier AMP 3 , resistor Rcomp, and capacitor Ccomp are arranged to provide error signal ER based, at least in part, on a difference between error signal ERR_sns and reference voltage Vref. Likewise, transistors Q 20 -Q 22 are arranged as a current mirror circuit to provide error signals HO_er and LO_er based, at least in part, on error signal ER. For example, the sizing and ratio of transistors Q 20 -Q 22 and the values of resistors R 20 -R 22 may be selected such that the error signals HO_er and LO_er are provided based on the value of error signal ER. Any suitable sizing, ratio, and/or values for transistors Q 20 -Q 22 and resistors R 20 -R 22 may be selected.

In one embodiment, error signals HO_er and LO_er are provided as separate error signals such that stabilization signal HO_st may be summed with error signal HO_er without substantially affecting error signal LO_er. Likewise, stabilization signal LO_st may be summed with error signal LO_er without substantially affecting error signal HO_er.

Stabilization circuit 220 includes voltage divider resistors R 23 and R 24 and amplifiers AMP 1 and AMP 2 . In one embodiment, voltage divider resistors R 23 and R 24 are arranged as a voltage divider to provide a predetermined voltage to the non-inverting input of amplifier AMP 1 and to the inverting input of amplifier AMP 2 . For example, the values of resistors R 23 and R 24 may be selected such that the predetermined voltage is related to a desired voltage of mid-point node N 3 of input capacitor circuit 296 . In one embodiment, this predetermined voltage is approximately equal to ½Vin. However, in other embodiments, other predetermined voltages may be selected.

In the illustrated embodiment, capacitor sense signal CAP_sns is provided to the inverting input of amplifier AMP 1 and to the non-inverting input of amplifier AMP 2 . However, in other embodiments, capacitor sense signal CAP_sns may be provided to amplifiers AMP 1 and AMP 2 via a voltage divider or other circuitry.

In one embodiment, stabilization circuit 220 is arranged to provide stabilization signals HO_st and LO_st such that they are proportional to the difference between the predetermined voltage and capacitor sense signal CAP_sns. For example, amplifier AMP 1 may be arranged such that stabilization signal HO_st is positive when capacitor sense signal CAP_sns is less than the predetermined voltage and is negative when capacitor sense signal CAP_sns is greater than the predetermined voltage. Likewise, amplifier AMP 2 may be arranged such that stabilization signal LO_st is positive when capacitor sense signal CAP_sns is greater than the predetermined voltage and is negative when capacitor sense signal CAP_sns is less than the predetermined voltage.

In one embodiment, amplifiers AMP 1 and AMP 2 are sink-only transconductance amplifiers. For example, in this embodiment, stabilization circuit 220 may be arranged to sink current away from error signals HO_er and LO_er based, at least in part, on the difference between the mid-point voltage at node N 3 and a predetermined voltage that is substantially equal to ½Vin. In this way, stabilization circuit 220 functions to modify the output of comparison circuits AMP 3 and AMP 4 and to adjust the lengths of the pulses provided on switch control signals HO and LO. In this way, switch control signals HO and LO are provided such that the mid-point voltage at node N 3 is maintained substantially at ½Vin.

Pulse modulation circuit 230 includes bias sources BIAS 1 and BIAS 2 , comparison circuits COMP 1 and COMP 2 , and pulse logic circuit 232 . In one embodiment, pulse modulation circuit 232 is arranged to provide switch control signals HO and LO to switch circuit 292 .

In one embodiment, bias sources BIAS 1 and BIAS 2 are arranged to provide bias voltages and/or offset voltages to the respective inverting inputs of comparison circuits COMP 1 and COMP 2 . In one embodiment, bias sources BIAS 1 and BIAS 2 are voltage sources that provide a fixed voltage across its terminals. For example, they may be employed to compensate for an offset voltage that is generated by transistors Q 21 -Q 22 of error circuit 210 . In one embodiment, bias sources BIAS 1 and BIAS 2 are arranged to provide an offset voltage of approximately 1.4 volts. In other embodiments, bias sources BIAS 1 and BIAS 2 may provide differing amounts of offset or may be omitted.

Comparison circuits COMP 1 and COMP 2 are arranged to provide comparison signals H and L to pulse logic circuit 232 . Comparison circuits COMP 1 and COMP 2 may be PWM comparators, other comparators, differential amplifiers, operational amplifiers, and/or the like. Also, comparison circuits COMP 1 and COMP 2 may provide hysteresis.

In one embodiment, pulse logic circuit 232 is arranged to provide switch control signals HO and LO based, at least in part, on comparison signals H and L. Pulse logic circuitry is discussed in further detail below, for one embodiment.

In other embodiments, embodiments of power converters and/or power converter controllers may differ from the embodiments of FIGS. 1 and 2 . For example, current sense signal I_sns, capacitor sense signal CAP_sns, and error sense signal ERR sns may be sensed from different nodes, through other sensing circuitry, voltage dividers, and/or the like. In addition, other embodiments of power converter controllers may be arranged such that stabilization signals HO_st and LO_st are employed to otherwise modify the timing of switch control signals HO and LO. For example, instead of being summed with error signals HO_er and LO_er, stabilization signals HO_st and LO_st may be summed with, offset, adjust, and/or the like, current sense signals, error sense signals, switch control signals, and/or the like. In yet another embodiment, current sense signal I_sns, capacitor sense signal CAP_sns, and error sense signal ERR_sns may be may be digitized by analog-to-digital converters, and the comparisons, summing, adjustments, offsets and/or the like, are performed by digital logic, delay lines, microcontrollers, microprocessors, digital signal processors, and/or the like, instead of or in conjunction with analog circuitry. These and other variations are within the spirit and scope of the invention.

FIG. 3 is a schematic diagram of an embodiment of pulse logic circuit 332 . Pulse logic circuit 332 may be employed as an embodiment of pulse logic circuit 232 of FIG. 2 . Pulse logic circuit 332 includes latches RS 1 and RS 2 , flip-flop FF 1 , inverter NOT 1 , and gates AND 1 and AND 2 , drivers DRV 1 and DRV 2 , and clock source CLK. In one embodiment, pulse logic circuit 332 is arranged as a PWM logic circuit. However, PFM logic circuits, other PWM logic circuits, and/or the like may also be suitably employed.

FIGS. 4A-4J are timing diagrams illustrating waveforms of embodiments of signals for an embodiment of the pulse logic circuit of FIG. 3 . FIGS. 4A-4J illustrate clock signal CLK, blanking signal NBLANK, high-output enable signal HO_en, high comparison signal H, high-latched signal PWMH, switch control signal HO, low-output enable signal LO_en, low comparison signal L, low-latched signal PWML, and switch control signal LO, respectively. Other embodiments of pulse logic circuit may operate differently without departing from the spirit and scope of the invention. FIGS. 4A-4J are not necessarily drawn to scale.

FIG. 5 is a schematic diagram of an embodiment of current sense circuit 594 . Current sense circuit 594 may be employed as an embodiment of current sense circuit 194 of FIG. 1 . Current sense circuit 594 includes sense transformer T 50 , sense rectification diodes D 50 - 53 , sense resistor R 50 , filter resistor R 51 , filter capacitor C 50 , and shunt device 595 .

In one embodiment, sense transformer T 50 is arranged to provide a low impendence path between nodes N 1 and N 2 and to provide current to nodes N 50 and N 51 based, at least in part, on the current between nodes N 1 and N 2 . In one embodiment, sense rectification diodes D 50 - 53 are arranged to rectify the output of the secondary coil of transformer T 1 . Also, filter resistor R 51 and filter capacitor C 50 are arranged to provide a filtered current sense signal I_sns based on the voltage across sense resistor R 50 . In one embodiment, shunt device 595 is arranged to selectively discharge filter capacitor C 50 between switching cycles. In one embodiment, an N-channel MOSFET switching device may be employed as shunt device 595 . Other switching devices, such as those discussed above, may also be suitably employed. A clock signal, such as from clock source CLK of pulse logic circuit 332 of FIG. 3 , may be employed to control shunt device 595 .

FIG. 6 is a schematic diagram of an embodiment of rectification circuit 698 . Rectification circuit 698 may be employed as an embodiment of rectification circuit 198 of FIG. 1 .

Rectification circuit 698 includes rectification diodes D 60 and D 61 , output inductor Lout, and output capacitor Cout. Rectification diodes D 60 and D 61 , output inductor Lout, and output capacitor Cout may be of any suitable type or value. In other embodiments, rectification circuit 698 may perform synchronous rectification. In one embodiment, N-channel MOSFET switching devices may be employed as synchronous rectification switches. Other switching devices, such as those discussed above, may also be suitably employed.

FIG. 7 is a schematic diagram of an embodiment of error circuit 710 . Error circuit 710 may be employed as another embodiment of error circuit 110 of FIG. 1 . In one embodiment, error circuit 710 includes error amplifier AMP 3 . In this embodiment, R 71 -R 74 and diodes D 70 and D 71 are arranged as a voltage divider and to block reverse current flow on error signals HO_er and

LO_er. This circuitry, in effect, isolates error signal HO_er from stabilization signal LO_st and isolates error signal LO_er from stabilization signal HO_st. Other comparator circuits, differential amplifier circuits, operational amplifier circuits, differential-to-single-ended converter circuits, and/or the like, may also be suitable employed to provide error signals HO_er and LO_er. These and other error circuits are within the spirit and scope of the invention.

FIG. 8 is a schematic diagram of an embodiment of stabilization circuit 820 . Stabilization circuit 820 may be employed as another embodiment of stabilization circuit 120 of FIG. 1 . As illustrated, stabilization circuit 820 is a sink-only embodiment of a stabilization circuit. However, the invention is not limited in this fashion. For example, stabilization circuits may be sink-only, source-only, or sink-source. Also, other comparator circuits, differential amplifier circuits, operational amplifier circuits, differential-to-single-ended converter circuits, and/or the like, may also be suitable employed to provide stabilization signals HO_st and LO_st. These and other stabilization circuits are within the spirit and scope of the invention.

FIG. 9 is a schematic diagram of an embodiment of pulse modulation circuit 930 . Pulse modulation circuit 930 may be employed as another embodiment of pulse modulation circuit 130 of FIG. 1 .

Pulse modulation circuit 930 is arranged such that error signals HO_er and LO_er are provided to the respective inverting inputs of comparison circuits COMP 1 and COMP 2 . Also, stabilization signals HO_st and LO_st are provided to comparison circuits COMP 1 and COMP 2 , respectively, as compensation signals or offset signals. In other embodiments, other pulse modulation circuits may also be employed. For example, stabilization signals HO_st and LO_st may be provided to pulse modulation logic circuit to adjust the timing of switch control signal outputs; a stabilization circuit may be arranged to provide source-only stabilization signals to a pulse modulation circuit for summing with respective current sense signals; and/or the like.

The above specification, examples and data provide a description of the method and applications, and use of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, this specification merely sets forth some of the many possible embodiments for the invention.