Inventor
Robert H. Bell, Jr.
Inventor
Austin, TX, US
Overview
Patents· 97 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing64%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%
H04LTransmission of digital information, e.g. telegraphic communication6%
G10LSpeech analysis techniques or speech synthesis3%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems3%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes2%
G01RMeasuring electric variables2%
G06KGraphical data reading2%
G11CStatic stores2%
PatentTitleYear
11,093,393System and method for early DRAM page-activation202110,726,833System and method for rapid customization of speech recognition models202010,635,736System, method and computer program product for data transfer management202010,169,087Technique for preserving memory affinity in a non-uniform memory access data processing system201910,025,590Multicore processor and method of use that configures core functions based on executing instructions20189,978,363System and method for rapid customization of speech recognition models20189,881,099'System, method and computer program product for data transfer management'20189,747,212'Virtual unifed instruction and data caches including storing program instructions and memory address in CAM indicated by store instruction containing bit directly indicating self modifying code'20179,727,469'Performance-driven cache line memory access'20179,679,561'System and method for rapid customization of speech recognition models'20179,626,294'Performance-driven cache line memory access'20179,582,284'Performance of processors is improved by limiting number of branch prediction levels'20179,563,559'Dynamic prioritization of cache access'20179,507,640'Multicore processor and method of use that configures core functions based on executing instructions'20169,325,233'DC to DC converter and PWM controller with adaptive compensation circuit'20169,323,527'Performance of emerging applications in a virtualized environment using transient instruction streams'20169,317,427'Reallocating unused memory databus utilization to another processor when utilization is below a threshold'20169,298,458'Performance of emerging applications in a virtualized environment using transient instruction streams'20169,247,003'Determining server write activity levels to use to adjust write cache size'20169,135,142'Workload performance projection for future information handling systems using microarchitecture dependent data'20159,098,351'Energy-aware job scheduling for cluster environments'20159,065,840'Determining server write activity levels to use to adjust write cache size'20159,009,406'Determining server write activity levels to use to adjust write cache size'20158,959,286'Hybrid storage subsystem with mixed placement of file contents'20158,943,272'Variable cache line size management'20158,935,478'Variable cache line size management'20158,898,674'Memory databus utilization management system and computer program product'20148,886,918'Dynamic instruction execution based on transaction priority tagging'20148,812,321'System and method for combining speech recognition outputs from a plurality of domain-specific speech recognizers via machine learning'20148,806,153'Partial line cache write injector for direct memory access write'20148,782,346'Dynamic prioritization of cache access'20148,769,210'Dynamic prioritization of cache access'20148,751,751'Method and apparatus for minimizing cache conflict misses'20148,745,362'Operating system aware branch predictor using a dynamically reconfigurable branch history table'20148,713,287'Off-loading of processing from a processor blade to storage blades based on processing activity, availability of cache, and other status indicators'20148,694,732'Enhanced coherency tracking with implementation of region victim hash for region coherence arrays'20148,688,960'Managing migration of a prefetch stream from one processor core to another processor core'20148,688,961'Managing migration of a prefetch stream from one processor core to another processor core'20148,645,673'Multicore processor and method of use that adapts core functions based on workload execution'20148,612,984'Energy-aware job scheduling for cluster environments'20138,544,006'Resolving conflicts by restarting execution of failed discretely executable subcomponent using register and memory values generated by main component after the occurrence of a conflict'20138,527,997'Energy-aware job scheduling for cluster environments'20138,527,956'Workload performance projection via surrogate program analysis for future information handling systems'20138,515,882'Efficient storage of individuals for optimization simulation'20138,495,636'Parallelizing single threaded programs by performing look ahead operation on the single threaded program to identify plurality of instruction threads prior to execution'20138,495,342'Configuring plural cores to perform an instruction having a multi-core characteristic'20138,463,662'Methods and apparatus for modeling relationships at multiple scales in ratings estimation'20138,438,334'Hybrid storage subsystem with mixed placement of file contents'20138,379,847'Data and control encryption'20138,352,712'Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted'20138,352,710'Off-loading of processing from a processor blade to storage blades'20138,347,124'Workload power consumption projection on information handling system'20138,327,126'Multicore processor and method of use that adapts core functions based on workload execution'20128,312,455'Optimizing execution of single-threaded programs on a multiprocessor managed by compilation'20128,245,084'Two-level representative workload phase detection'20128,229,798'Methods and apparatus for modeling relationships at multiple scales in ratings estimation'20128,205,136'Fault tolerant encoding of directory states for stuck bits'20128,193,798'Buck regulators with adjustable clock frequency to achieve dropout voltage reduction'20128,151,146'Tool for predicting fault-prone software files'20128,140,766'Enhanced coherency tracking with implementation of region victim hash for region coherence arrays'20128,091,073'Scaling instruction intervals to identify collection points for representative instruction traces'20128,010,334'Method and apparatus for evaluating integrated circuit design performance using basic block vectors, cycles per instruction (CPI) information and microarchitecture dependent information'20118,000,953'Augmenting of automated clustering-based trace sampling methods by user-directed phase detection'20118,001,132'Methods and apparatus for improved neighborhood based analysis in ratings estimation'20117,996,824'Benchmark synthesis using workload statistics'20117,996,346'Method for autonomic workload distribution on a multicore processor'20117,987,320'Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation'20117,962,770'Dynamic processor reconfiguration for low power without reducing performance based on workload execution characteristics'20117,904,870'Method and apparatus for integrated circuit design model performance evaluation using basic block vector clustering and fly-by vector clustering'20117,900,071'Apparatus and method to manage power in a computing device'20117,870,337'Power-aware line intervention for a multiprocessor snoop coherency protocol'20117,844,928'Method and apparatus for evaluating integrated circuit design performance using enhanced basic block vectors that include data dependent information'20107,840,758'Variable store gather window'20107,831,774'Pipelining D states for MRU steerage during MRU-LRU member allocation'20107,805,574'Method and cache system with soft I-MRU member protection scheme during make MRU allocation'20107,770,140'Method and apparatus for evaluating integrated circuit design model performance using basic block vectors and fly-by vectors including microarchitecture dependent information'20107,706,155'Current mode half-bridge power converter'20107,686,619'Apparatus, system, and method for a configurable blade card'20107,689,777'Cache member protection with partial make MRU allocation'20107,689,891'Method and system for handling stuck bits in cache directories'20107,568,076'Variable store gather window'20097,543,109'System and method for caching data in a blade server complex'20097,543,120'Processor and data processing system employing a variable store gather window'20097,533,321'Fault tolerant encoding of directory states for stuck bits'20097,401,189'Pipelining D states for MRU steerage during MRU/LRU member allocation'20087,366,851'Processor, method, and data processing system employing a variable store gather window'20087,363,433'Cache member protection with partial make MRU allocation'20087,343,592'Benchmark synthesis using workload statistics'20087,343,455'Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation'20087,319,232'Apparatus and method for high-bandwidth opto-coupler interface'20087,307,481'Minimum synchronization frequency discriminator'20076,950,892'Method and system for managing distributed arbitration for multicycle data transfer requests'20056,788,038'Apparatus and method for deactivating an on-switch of a circuit for a variable time interval'20046,606,666'Method and system for controlling information flow between a producer and a buffer in a high frequency digital system'20036,604,145'Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer and a shared data path'20036,601,105'Method and system for controlling information flow between a producer and multiple buffers in a high frequency digital system'20036,598,086'Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2020Patents assigned to IBM (82)· patent assignee history
2003–2021Based in Austin, TX, US· patent location history
2004–2010Based in Chandler, AZ, US· patent location history
2011–2013Based in Murray Hill, NJ, US· patent location history
2012–2019Patents assigned to BELL JR ROBERT H (37)· patent assignee history
2012–2018Patents assigned to CAPPS JR LOUIS BENNIE (7)· patent assignee history
2013–2019Patents assigned to HUA HONG L (9)· patent assignee history
2013–2016Patents assigned to SRINIVAS MYSORE S (7)· patent assignee history
2014–2020Based in Berkeley Heights, NJ, US· patent location history
2015–2017Based in Raleigh, NC, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 82 | 2003–2020 |
| BELL JR ROBERT Hself | 37 | 2012–2019 |
| HUA HONG L | 9 | 2013–2019 |
| CAPPS JR LOUIS BENNIE | 7 | 2012–2018 |
| SRINIVAS MYSORE S | 7 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 80 | 2003–2021 |
| Berkeley Heights, New Jersey, US | 4 | 2014–2020 |
| Murray Hill, New Jersey, US | 4 | 2011–2013 |
| Chandler, AZ, US | 4 | 2004–2010 |
| Raleigh, NC, US | 3 | 2015–2017 |