Determination of single-fix rectification function

The present application claims priority to U.S. Provisional Patent Application Ser. No. 60/938,129, filed on May 15, 2007 and entitled “Determination of Single-Fix Rectification Function”, the contents of which are incorporated herein by reference for all purposes.

Conventional integrated circuit design involves several complex steps. For example, a circuit designer may use software tools to define the operation of each functional element of an integrated circuit at each clock cycle. Such a definition is known as a Register Transfer Level (RTL) specification. A logic synthesis operation may then be applied to the RTL specification to generate a list of logic gates and interconnections between the logic gates. The list may be referred to as a netlist, and may be used to implement the RTL specification.

A modern netlist may comprise millions of logic gates and associated interconnections. Conventional design tools may parse the netlist and determine placement of the logic gates and routing of the interconnections on an integrated circuit based thereon. The placement and routing information may be used to generate photolithography masks, which in turn may be used to fabricate the integrated circuit. The photolithography masks may consist of gate masks used to fabricate the logic gates of the netlist and routing masks used to fabricate the interconnections therebetween.

It may be desirable to change an original netlist so that it is functionally equivalent to a new specification. For example, a designer may wish to change a functional aspect of an original netlist due to an Engineering Change Order and/or due to an error in the original netlist. The designer may therefore create a new RTL specification and synthesize the new netlist therefrom. Alternatively, the designer may directly edit the original netlist to create a new netlist. The latter alternative may be employed late in the design process, because doing so will reserve most of the engineering effort invested in the original netlist.

The specific changes required to the new netlist are dependent upon the logical difference between the original netlist and the new netlist. Since a logical difference between two logic functions may typically be expressed in many different forms, the details of the change may differ based on the form in which the logical difference is expressed.

FIG. 1 is a logical diagram of original netlist G 1 and “target” netlist G 2 . The present example will illustrate changes to netlist G 1 that result in functional equivalence with target netlist G 2 . Either of “single-fix” signals S 1 and S 2 may be changed to accomplish this goal. FIG. 2A illustrates netlist G 1 after changing signal S 1 . Specifically, signal S 1 has changed from (c^d)′ to (c^d)′+e′. The function (c^d)′+e′ may be called a rectification function because it rectifies a functional difference between original netlist G 1 and target netlist G 2 . FIG. 2B illustrates a change of signal S 2 from (ab)′ to rectification function (ab)′e. Both systems shown in FIG. 2A and FIG. 2B are functionally equivalent to netlist G 2 of FIG. 1 .

Systems have been proposed and for locating single-fix signals and deriving corresponding rectification functions. Such systems are typically not scalable, limited to simple correcting-models (e.g. gate type change, connection change, etc), and/or otherwise inefficient. Accordingly, further systems are desired for efficiently determining a change to an original netlist that will result in functional equivalence between the changed netlist and a target netlist exhibiting desired functionality.

Typically, a changed netlist will include some gates that were not present in the original netlist, will lack some gates that were present in the original netlist, and will reflect some different interconnections between the included gates. Accordingly, in order to fabricate an integrated circuit based on the changed netlist, new gate masks must be generated at a significant cost. Systems are therefore desired to implement a changed netlist using gate masks of an original netlist.

FIG. 1 comprises schematic diagrams of two netlists.

FIGS. 2A and 2B comprise schematic diagrams of a netlist that has been changed to achieve functional equivalence with another netlist.

FIGS. 3A and 3B comprise a flow diagram according to some embodiments.

FIG. 4 is a block diagram of a computer system according to some embodiments.

FIG. 5 comprises representation of overlapping logical cones for each of two netlists.

FIG. 6 is diagram illustrating classification of inputs according to some embodiments.

FIG. 7 illustrates iterative determination of a rectification function according to some embodiments.

FIG. 8 comprises pseudo code of an iterative process to determine a rectification function according to some embodiments.

FIG. 9 is a block diagram of a system to re-map a netlist based on a logical patch and available logic gates according to some embodiments.

FIGS. 3A and 3B illustrate a flow diagram of process 300 to determine a function to rectify a logical difference between a first netlist and a second netlist. According to some embodiments, the first netlist may be changed to implement the function and, as a result, the changed netlist and the second netlist will be functionally equivalent. Process 300 may therefore be used in some embodiments to derive rectification functions implementing an engineering change order without re-excuting logic synthesis, placement or routing design processes. Such embodiments may also allow most gate masks of the first netlist to be used to fabricate an integrated circuit reflecting on the changed netlist. Some embodiments may provide a scalable solution that is applicable to disparate types of engineering change order requirements.

Process 300 and the other processes described herein may be executed by any combination of hardware, software and/or manual implementations. For example, the processes may be executed by a microprocessor executing processor-executable program code of a software application.

FIG. 4 is a block diagram of an internal architecture of computer system 400 according to some embodiments of the invention. Computer system 400 may execute processes such as process 300 to be described herein. Computer system 400 may also or alternatively store data used in performance of these processes. According to some embodiments, computer system 400 comprises a desktop computer system.

Computer system 400 includes microprocessor 410 in communication with communication bus 420 . Microprocessor 410 may comprise a RISC-based or other type of processor. Microprocessor 410 executes program code to control the elements of computer system 400 to provide desired functionality.

Communication port 430 is also in communication with communication bus 420 . Communication port 430 may be used to transmit data to and to receive data from devices external to computer system 400 . Communication port 430 is therefore preferably configured with hardware suitable to physically interface with desired external devices and/or network connections. For example, communication port 430 may comprise an Ethernet connection to a local area network through which computer system 400 may receive netlists from a logic design platform.

Input device 440 , display 450 and printer 460 are also in communication with communication bus 420 . Any known input device may comprise input device 440 , including a keyboard, mouse, touch pad, voice-recognition system, or any combination of these devices. As mentioned above, information may also be input to computer system 400 from other devices via communication port 430 . Display 450 may be an integral or separate CRT display, flat-panel display or the like used to display graphics and text in response to commands issued by microprocessor 410 . Printer 460 may also present text and graphics to an operator, but in hardcopy form using ink-jet, thermal, dot-matrix, laser, or other printing technologies.

RAM 470 is connected to communication bus 420 to provide microprocessor 410 with fast data storage and retrieval. In this regard, processor-executable code being executed by microprocessor 410 is typically stored temporarily in RAM 470 and executed therefrom by microprocessor 410 . Any suitable random access memory may be used as RAM 470 . ROM 480 , in contrast, provides storage from which data can be retrieved but to which data cannot be stored. Accordingly, ROM 480 may be used to store invariant process steps and other data, such as basic input/output instructions and data used during boot-up of computer system 400 or to control communication port 430 .

Data storage device 490 stores, among other data, processor-executable code of logic design application 491 . Microprocessor 410 therefore executes the code of logic design application 491 in order to control computer system 400 to determine a rectification function according to some embodiments. In some embodiments, program code of logic design application 491 embodies process 300 .

The program code of logic design application 491 may be read from a computer-readable medium, such as a floppy disk, a CD-ROM, a DVD-ROM, a Zip™ disk, or a magnetic tape, and then stored in data storage device 490 in a compressed, uncompiled and/or encrypted format. In alternative embodiments, hard-wired circuitry may be used in place of, or in combination with, processor-executable code for implementation of processes according to some embodiments. Thus, embodiments are not limited to any specific combination of hardware and software.

Logic design application 491 may operate in conjunction with one or more of netlists 492 according to some embodiments. Netlists 492 may comprise lists of logic gates and interconnections, and/or may also include additional details. Netlists 492 may comprise one or more netlists generated according to some embodiments described herein.

Also stored in data storage device 490 may also be other unshown elements that may be necessary for operation of computer system 400 , such as an operating system, a database management system, and “device drivers” for allowing microprocessor 410 to interface with other elements of computer system 400 . Data storage device 490 may also include other applications and other data files to provide functionality such as Web browsing, calendaring, e-mail access, word processing, accounting, presentation development and the like. These elements are known to those in the art, and are therefore not described in detail herein.

Returning to process 300 , a set S of one or more signals of netlist G 1 is determined at 305 . Netlist G 1 may represent an original list of logic gates that was synthesized based on an RTL specification. The set S may be determined based on netlist G 2 , which in turn represents logic gates for performing a desired function that differs from the RTL specification of netlist G 1 . Netlist G 2 may be generated from a new RTL specification.

FIG. 5 represents netlist G 1 and netlist G 2 according to some embodiments. Netlist G 1 is comprised of logical cones f 1 , f 2 . . . f n having inputs V 1 and netlist G 2 is comprised of logical cones g 1 , g 2 . . . g n having inputs V 2 . The illustrated signal s belongs to each of logical cones f 1 , f 2 . . . f n of netlist G 1 . Inputs V 1 and V 2 may be different, but typically are substantially identical. Accordingly, inputs V 1 and V 2 will be described below as a single set of inputs V={V 1 , V 2 }. For example, if V 1 ={a, b, c} and V 2 ={b, c, d}, then V={a, b,c,d}.

Each of the signals s determined at 305 is a signal of netlist G 1 that can be re-synthesized so as to correct the functional differences between netlist G 1 and netlist G 2 . Accordingly, each of the determined signals s may be referred to as a “single-fix” signal. The existence and determination of single-fix signals are known in the art.

Generally, a single-fix signal s is a signal of netlist G 1 that, for every input vector V of netlist G 1 and netlist G 2 , can be assigned either a 0 or a 1 so as to cause the outputs of netlist G 1 and netlist G 2 to be identical. Symbolically, the single-fix signals s will be able to correct any functional differences between netlist G 1 and netlist G 2 if E 0 E 1 ≡0, where E 0 =G 1 (V,s=0)^G 2 (V)=Σf i (V,s=0)^g i (V), E 1 =G 1 (V,s=1)^G 2 (V)=Σf i (V,s=1)^g i (V), and “Σ” is the logic “OR” operation. Accordingly, in some embodiments of 305 , the equation E 0 E 1 ≡0 is evaluated for each signal within the shaded triangular area of netlist G 1 .

Next, at 310 , error functions E 0 (V) and E 1 (V) and care function Care(V) are evaluated for a signal s which belongs to the determined single-fix signal set S. The error function E 0 (V) reflects the difference between the outputs of netlist G 1 and netlist G 2 for each input vector V in a case that s equals 0. Similarly, the error function E 1 (V) reflects the difference between the outputs of netlist G 1 and netlist G 2 for each input vector V in a case that s equals 1. According to some embodiments, and based on the relationships set forth above, E 0 (V)=G 1 (s=0, V)^G 2 (V) and E 1 (V)=G 1 (s=1, V)^G 2 (V).

The care function Care(V) indicates whether or not the output of netlist G 1 depends on the value of the signal s for each input vector V. For example, for a particular input vector V, Care(V)=1 if the output of netlist G 1 is a first value (i.e., 0 or 1) for s=0 and the output of netlist G 1 is a different value (i.e., 1 or 0) for s=1. If the output of netlist G 1 is a same value (i.e., 0 or 1) for s=0 and for s=1, Care(V)=0. One symbolic representation of the care function according to some embodiments is Care(V)=δG 1 /δs=G 1 (s=0)^G 1 (s=1)=Σf i (V,s=0)^f i (V,s=1).

True inputs V t and other inputs V u associated with the single-fix signal s are determined at 315 from inputs V. Generally, the other inputs V u comprise a set of inputs which exist in Care(V) and in E 0 (V) or E 1 (V), and which theoretically can be optimized out of the rectification function by taking Care(V) into account during such optimization. Conventional symbolic methods may not exist to efficiently execute such an optimization due to the complexity of expressing E 0 , E 1 and Care symbolically. As will be seen below, some embodiments include a novel mechanism of optimization employing an input classification, constant assignment, and an iterative process to derive the rectification function. Some embodiments provide a mechanism which is scalable to the size of design, and in which the quality of the derived rectification function is optimal or near optimal.

In some embodiments, an input v is classified into other inputs V u at 315 if the following equation is True:

E 0 ( v =0) E 1 ( v =1)+ E 1 ( v =0) E 0 ( v =1)≡0

FIG. 6 is a diagram describing the determination of true inputs V t and other inputs V u according to some embodiments. All inputs V={v 0 , v 1 , v 2 , . . . v n } are subject to the determination, which begins by evaluating the above equation. As shown, the inputs v for which the equation is True are assigned to other inputs V u , and the inputs v for which the equation is False are assigned to true inputs V t .

Next, the other inputs V u are further classified into a first set of inputs and a second set of inputs at 320 . The first set of inputs includes those inputs V u that may be assigned a static value during the below-described iterative determination of the rectification function. The second set of inputs includes those inputs V u which will be associated with dynamically-assigned values during the iterative determination.

Continuing with the example of FIG. 6 , the following equations are evaluated at 320 with respect to each of the other inputs V u , vεV u :

Care( v =0)≧Care( v =1)

Care( v =1)≧Care( v =0)

The input vεV u for which either of these equations is True is classified into the first set of inputs, denoted in FIG. 6 as V u1 . The second set of inputs (i.e., V u2 ) comprises the inputs in V u for which both of these equations are False. Every input of V u is subject to the determination by evaluating the above equations and is classified into either first (V u1 ) or the second (V u2 ) set of inputs.

The determination at 315 and the classification at 320 may be performed using symbolic methods to evaluate the equations and therefore may provide inconclusive results due to computing limitations or other reasons. If the evaluation of an equation provides an inconclusive result, the evaluation may be considered “aborted”. FIG. 6 also provides for classification of inputs in case that any of its equations are aborted (i.e., A. For example, some inputs v of V u may be classified as inputs V u3 if the determination at 315 and the classification at 320 are aborted with respect to those inputs. The inputs of V u3 will be treated the same as the inputs in V u2 and be associated with dynamically-assigned values during the iterative determination of the rectification function. The only difference between V u3 and V u2 is that some inputs in V u3 may be re-classified into true inputs V t later based on some determinations.

A respective static value is assigned to each of the first set of inputs (e.g., V u1 ) at 325 . In some embodiments of 325 , a first input v of V u1 is assigned a value of 0 if Care(v=0)≧Care(v=1) is True and a value of 1 if Care(v=1)≧Care(v=0) is True. The assignment is also performed with respect to each other v of V u1 . The determined set of values for V u1 is denoted as α u1 .

At 330 , a respective initial value is assigned to each of the second set of inputs V u2 and the inputs V u3 based on Care(V). Since values were statically assigned to V u1 at 325 , inputs V u2 and V u3 remain unassigned prior to 330 . The initial values assigned to inputs V u2 and V u3 cause the netlist G 1 to output one value (e.g., 0 or 1) if s=0 and to output a different value (e.g., 1 or 0) if s=1. Stated symbolically, a set of values is assigned to inputs V t , V u2 and V u3 (together with the static value assignment to inputs V u1 at 325 ) to result in Care(V)=G 1 (s=0)^G 1 (s=1)=1. The values thusly assigned to inputs V u2 and V u3 will be the desired respective initial value of inputs V u2 and V u3 . The values assigned to inputs V t during the determination of the initial values for inputs V u2 and V u3 are simply discarded and therefore inputs V t will be treated symbolically during determination of initial function F s .

330 - 365 describe an iterative process to compute the function F s which is to be substituted for the single-fix signal s so as to correct the functional difference between netlist G 1 and netlist G 2 . Theoretically, F s can be computed based on either E 0 (V) or E 1 (V). Because of the difficulty in precisely predicting whether an E 0 (V)-based or an E 1 (V)-based computation is more desirable, in terms of the solution convergence in the iteration process or the quality of F s , F s may be computed in parallel. One of the parallel computations may be based on E 0 (V), with the resulting F s being denoted as F s — on. The other computation may be based on E 1 (V) and the resulting F s may be is denoted as F s — off. F s — on and F s — off are updated in each iteration until it is determined at 340 to terminate the iterations.

At 335 , two initial functions are first computed for F s — on and F s — off respectively based on the static and initial values assigned to the inputs V u (denoted as αu — 0):

F s — on= E 0 ( V ))| Vu=αu — 0

F s — off= E 1 ′ ( V )| Vu=αu — 0

Since all non-V t inputs have been assigned a static or initial value, the only variables of functions F s — on and F s — off are inputs V t .

FIG. 7 includes logical diagrams of G 1 and G 2 for the purpose of describing one example of 335 . Signal s of FIG. 7 has been identified as a single-fix signal of netlist G 1 . For this particular example, because input b is shadowed by s in G 1 and also not used in G 2 , it is ignored from the input list and V is comprised of inputs {a, x, y}. At 335 , two initial rectification functions will be determined for F s — on and F s — off respectively. Turning to logic table 700 , input a has been classified as an element of V u2 , and inputs x and y have been classified as elements of V t . As shown, an initial value of 1 was determined for input a at 330 based on Care(V).

Netlists G 1 and G 2 are evaluated for each combination of inputs (x, y) while a=1. For each combination of inputs (x, y), values of E 0 and E 1 are determined and listed in the columns labeled “E0” and “E1”. The initial functions of F s — on and F s — off are determined accordingly based on the first four rows of table 700 :

F s — on= E 0 | a=1 =xy

F s — off= E 1 ′| a=1 =x′+y

At 340 , it is determined whether either of the initial functions F s — on or F s — off actually corrects the functional difference between G 1 and G 2 . Symbolically, 340 comprises the evaluation of the following expressions:

G 1 ( V u1 =α u1 , V, s=F s — on )≡ G 2 ( V u1 =α u1 )

G 1 ( V u1 =α ul , s=F s — off )≡ G 2 ( V u1 =α u1 )

The evaluation may result in one of three scenarios: (1) one of the expressions is true, in which case the corresponding initial function (i.e., F s — on or F s — off) is the desired F s and flow proceeds directly to 365 ; (2) both of the expressions are true, in which case the smaller one of Fs_on and Fs_off is selected to be the desired F s and flow goes to 365 directly; or (3) neither of these expressions are true, in which case flow proceeds to 345 .

Two input vectors α_on and α_off are generated at 345 . The vectors may be generated during the evaluation of the above two expressions at 340 . The vectors may be expressed symbolically as:

α_on=(α t — on, α u — on)

α_off=(α t — off, α u — off),

for which

G 1 ( V=α _on, s=F s — on)≠ G 2 ( V=α _on)

G 1 ( V=α _off, s=F s — off))≠ G 2 ( V=α _off)

Here, α t — on and α t — off are values for inputs of V t , α u — on and αu_off are values for the other inputs V u including the statically-assigned values (α u1 ) to V u1 which were determined at 325 .

Next, at 350 , it is determined whether to adjust the set of true inputs V t . In this regard, inconclusive evaluations at 315 and 320 of the above-mentioned classification-related equations may have caused some “true” inputs to be erroneously classified into V u3 . Such misclassification may prevent F s — on and/or F s — off from achieving the goal of correcting the functional difference between G 1 and G 2 no matter how many iterations are performed. This scenario may be considered at 350 by evaluation of the following expressions:

F s — on( V t =α t — on)=1

F s — off( V t =α t — off)=0

If either of the above expressions are evaluated to be true, flow goes to 360 to re-classify at least one of the inputs in V u3 into V t .

In some embodiments of 360 , the currently-assigned value of each input V u3 is toggled independently and it is determined whether F s — on or F s — off still corrects the difference for the particular input vector (i.e., α_on or α_off). If the difference remains corrected, the toggled input is re-classified as an input V t . Reclassification may comprise selection of a random (e.g., the first) input in V u3 as an input V t if the above-described attempt to identify and re-classify an input V u3 is unsuccessful. After reclassifying an input from V u3 to V t , flow returns to 330 for another iteration to derive the rectification functions for the current single-fix signal s.

If, at 350 , it is determined that no reclassification is required, flow will proceed to 355 . At 355 , a new F s — on and F s — off are computed as follows:

F s — on= F s — on+ E 0 | vu=αu — on

F s — off= F s — off· E 1 ′| vu=αu — off

F s — on and F s — off on the right-hand side of the above equations represent the previously-determined F s functions, which are either the initial functions F s or functions F s obtained from a previous iteration. αu_on and αu_off represent the static values originally assigned to the first set of inputs V u1 and the next values assigned to the second set of inputs V u2 .

With respect to the FIG. 7 example, it is determined at 340 that neither of the previously-determined F s — on and F s — off fixes the functional difference between netlist G 1 and netlist G 2 . Therefore, at 345 , input vector a is generated to demonstrate the functional difference (a=0, x=0, y=0). Next, it is determined to not adjust V t at 350 , and, at 355 , the new Fs_on and Fs_off are derived based on the previous F s — on and F s — off. The derivation may be based on the new value (i.e., 0) assigned to the input a as follows:

F s — on= F s — on+ E 0 | a=0 =xy +( x+y )′= x XNOR y

F s — off= F s — off· E 1 ′| a=0 ( x+y ′)·( x^y )′= x XNOR y

After derivation of the new Fs_on and Fs_off, flow returns to 340 from 355 to determine whether any of the newly-derived functions (Fs_on and Fs_off) corrects the functional difference between G 1 and G 2 . In the present example, both of the new derived functions (F s — on and F s — off) are determined at 340 to fix the functional difference and therefore one of the derived functions is selected to be F s . Accordingly, flow proceeds to 365 .

If, at 330 , the initial value derived and assigned to input a is 0 instead of 1 as described above, the initial function F s — off determined at 335 will fix netlist G 1 of FIG. 7 . Flow would therefore proceed from 340 to 365 directly without performing an iteration. The respective determinations of F s based on E 0 and E 1 may approach a desired F s at different rates, which are related to the sequence of values assigned to V u2 and V u3 .

At 365 , it is determined if any existing logic in netlist G 1 may be used to further reduce the size of the determined rectification function F s . Some embodiments of 365 include exploring logic-equivalent signals in netlist G 1 and F s . If such signals are identified, F s may be re-formatted to utilize the existing logic. Since F s is constructed iteratively by E 0 or E 1 , which are actually derived from netlist G 1 and netlist G 2 , quite a number of signals in netlist G 1 may include logic that can be used in F s . A logic patch implementing the resulting F s is created 365 .

FIG. 8 comprises pseudo code 800 according to some embodiments. Pseudo code 800 roughly corresponds to 315 through 365 of process 300 . For example, line 810 of pseudo code 800 describes determining V t and V u at 315 , classifying V u into V u1 , V u2 and V u3 at 320 , and assigning static values (i.e., C 1 ) to V u1 at 325 .

Loop 820 includes determination of initial function F s (i.e., F s — on and F s — off) at 335 , determination of whether G 1 (S=F s )≡G 2 at 340 , assignment of next values (i.e., u1, u2) to V u2 and V u3 at 345 , determination at 350 of whether reclassification is needed, and determination at 355 of a new F s based on the previous F s and on the next values (i.e., Fs_on=Fs_on+E 0 (Vu=u1), Fs_off=Fs_off·E1′(Vu=u2)). Loop 830 corresponds to 360 of process 300 to identify an input classified into V u3 and to re-classify the input into V t .

Returning to process 300 , it is determined at 370 whether any other single-fix signal s of netlist G 1 remains to be analyzed per 310 through 365 . If so, flow returns to 310 and proceeds as described above with respect to a next single-fix signal s. One or more logic patches are therefore determined during successive iterations of 365 , with each logic patch being associated with a respective single-fix signal s.

Flow continues from 370 to 375 if no other single-fix signal s of netlist G 1 remains to be analyzed. One logic patch is selected from the one or more determined logic patches at 365 . According to some embodiments, the selected logic patch comprises the smallest (e.g., in number of gates) of the logic patches determined at 365 . The selected logic patch may comprise one of the logic patches that would be most-easily incorporated into netlist G 1 .

In this regard, signal s associated with the selected logic patch is re-mapped based on the selected patch at 380 . The re-mapping may depend on available logic gates. For example, netlist G 1 may include unused logic gates that may be used to implement the logical patch. Alternatively or additionally, the logic patch may be implemented using gates that are no longer needed in the synthesis of signal s. 380 thereby generates a new netlist which is functionally equivalent to netlist G 2 and is identical to netlist G 1 but for the logic used to resynthesize signal s.

FIG. 9 illustrates system 900 according to some embodiments. System 900 may implement process 300 according to some embodiments. System 900 includes RTL specification RTL 1 which is synthesized to produce netlist G 1 . RTL specification RTL 2 differs from RTL 1 in order to change a functional aspect and/or correct an error of RTL 1 . Netlist G 2 is synthesized from RTL 2 .

Equivalence check 910 receives netlists G 1 and G 2 and determines logic patch 920 therefrom. Logic patch 920 resynthesizes one signal s of netlist G 1 . The resynthesized signal s may comprise a single-fix signal netlist G 1 as described above. Accordingly, equivalence check 910 may embody 305 through 375 of process 300 .

Re-map 930 may comprise a module to receive netlist G 1 and patch 920 . Re-map 930 may re-map signal s within netlist G 1 according to patch 920 . Re-map 930 may use freed and/or spare gates of netlist G 1 to implement patch 920 . Such re-mapping creates new netlist G 1 (s*), which is functionally equivalent to netlist G 2 . Moreover, the gate masks of netlist G 1 (s*) may be identical to the gate masks of netlist G 1 , thereby sparing expensive re-masking steps. Routing between the gates of netlist G 1 (s*) may of course differ from the routing of netlist G 1 .

The several embodiments described herein are solely for the purpose of illustration. Embodiments may include any currently or hereafter-known versions of the elements described herein. Therefore, persons in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.