Emitter area trim scheme for a PTAT current source

This application is a divisional of application Ser. No. 11/284,583, filed Nov. 22, 2005, now U.S. Pat. No. 7,236,048, issued Jun. 26, 2007, entitled “Self-Regulating Process-Error Trimmable PTAT Current Source,” of the same inventors hereof, which application is incorporated herein by reference in its entirety.

The invention relates to a current source for generating a current proportional to absolute temperature (PTAT) and, in particular, to a self-regulating PTAT current source that is process-error trimmable.

A current proportional to absolute temperature (PTAT) or a PTAT current is a current with a known, fixed, positive temperature coefficient. PTAT currents are commonly used to bias transistors, amplifiers and other circuits when a PTAT current is desirable for compensating for performance variations due to temperature. Current sources for generating PTAT currents are known. FIG. 1 is a circuit diagram illustrating a conventional PTAT current source.

Referring to FIG. 1 , current source 10 utilizes bipolar transistors Q 2 and Q 3 operating at unequal current densities to generate a voltage difference between the base-to-emitter voltages V BE of the two bipolar transistors. The difference in the base-to-emitter voltages, denoted as ΔV BE , is intrinsically PTAT in nature. Specifically, bipolar transistor Q 3 is a unit size transistor while bipolar transistor Q 2 has a size A times transistor Q 3 . A base-to-emitter voltage V BEH is generated at the base/collector terminal of transistor Q 3 (node 16 ) while a base-to-emitter voltage V BEL is generated at the base/collector terminal of transistor Q 2 (node 13 ).

The PTAT voltage ΔV BE , which is given as ΔV BE =V BEH −V BEL , is super-imposed across a resistor R 0 to produce a current that is also PTAT (denoted as I PTAT ) when resistor R 0 has a negligible TC (Temperature Coefficient). When resistor R 0 has a constant TC, the resulting current will have a temperature coefficient having a proportionally factor somewhat less than (i.e. sub-PTAT) or greater than (i.e. super-PTAT) 100% relative to absolute temperature. Specifically, a current mirror, formed by PMOS transistors M 2 and M 3 and controlled by a gate voltage Vgate, is coupled to supply currents to bipolar transistors Q 3 and Q 2 , respectively. An operational amplifier (op-amp) 12 is coupled to the bipolar transistors to provide feedback control. Voltage V BEH (on node 16 ) is coupled to the inverting input terminal as the input voltage Vin_n of the op-amp 12 . Resistor R 0 is coupled between the drain terminal of transistor M 3 (node 14 ) and voltage V BEL (on node 13 ). The voltage at node 14 , which is the top terminal of resistor R 0 , is coupled to the non-inverting input terminal of op-amp 12 as the input voltage Vin_p.

In operation, operational amplifier 12 generates an output voltage V OUT (node 18 ) that is coupled to drive a PMOS transistor M 4 and fed back as the gate voltage Vgate to drive the current mirror of transistors M 2 and M 3 . Op-amp 12 generates output voltage V OUT to cause the voltage difference between voltages Vin_p and Vin_n to go to zero. In this manner, the voltage at the top terminal (node 14 ) of resistor R 0 is driven to voltage V BEH and voltage ΔV BE is thus super-imposed on resistor R 0 .

In the present illustration, operational amplifier 12 generates a voltage signal V OUT as the output signal and the voltage output signal is converted into a current value through PMOS transistor M 4 . Thus, output voltage V OUT is coupled to the gate and drain terminals of PMOS transistor M 4 to generate a reference current I REF which is absorbed by operation amplifier 12 . It is assumed that operational amplifier 12 is a low output impedance amplifier. Because the output voltage V OUT driving the gate terminal of transistor M 4 is also coupled to drive the gate terminals of transistors M 2 and M 3 , transistors M 2 , M 3 and M 4 , being nominally equal in area, have the same gate-to-source voltages and thus these transistors provide the same drain current output. Therefore, the reference current I REF is equal to the PTAT current I PTAT generated at the drain terminal (node 14 ) of transistor M 3 . The ratio between reference current I REF and PTAT current I PTAT remains fixed over process and power supply voltage variations.

The equation which gives the relationship between resistor R 0 , the reference current I REF , and the chosen area ratio A of the two NPN bipolar transistors Q 2 and Q 3 is:

I REF = N f ⁢ KT ⁢ ⁢ ln ⁢ ⁢ A qR 0 , Eq . ⁢ ( 1 )

where q is the electron charge; K is the Boltzmann's constant; T is absolute temperature; N f is emission coefficient; A is the area ratio of transistors Q 2 to Q 3 (A:1).

The conventional PTAT current source 10 of FIG. 1 has many shortcomings. In particular, the current mirror of the current source is sensitive to device mismatches and fabrications process variations, leading to poor power supply rejection and thus poor PTAT current accuracy.

In particular, one property of current source 10 that affects the accuracy of the PTAT current generated by the current source is the emitter resistance from the input terminals (nodes 14 , 16 ) of operational amplifier looking into bipolar transistors Q 2 and Q 3 . For a given bias condition, the emitter resistance r e is defined as follows:

r e = N f ⁢ KT qI REF , Eq . ⁢ ( 2 )

where reference current I REF has the same current value as PTAT current I PTAT . More specifically, the emitter resistance r e is a function of temperature T and the collector current I C of the bipolar transistor. In the present illustration, the collector current I C has the same current value as the reference current I REF , i.e. I C =I REF . Thus, the emitter resistance r e as given in equation (2) is a function of temperature T and the reference current I REF . By combining equations (1) and (2), the resistance of resistor R 0 can be expressed as:

Thus, the impedance seen at the unit area transistor Q 3 has a value of r e while the impedance seen at the A-ratio-area transistor Q 2 has a value of r e *[1+lnA]. The fact that the impedances looking into transistor Q 3 is non-zero prevents perfect PSSR (power supply rejection ratio) cancellation and also creates sensitivity to device mismatches between PMOS transistors M 2 and M 3 that is undesirable.

In particular, in the control loop formed by op-amp 12 , the output voltage V OUT is fed back to the gate terminal of transistor M 3 where transistor M 3 acts as a common source inverting amplifier, thereby forming the primary negative feedback path. If there is anything that tends to change the currents at transistors M 2 and M 3 together, such as a change in the power supply voltage Vdd, there will be a change in the voltages at both the non-inverting and inverting input terminals (voltages Vin_p and Vin_n) of op-amp 12 . Changes in the voltage Vin_n tend to subtract from the feedback signal at voltage Vin_p and in fact, perfect subtraction occurs but for the presence of resistor R 0 at the non-inverting input terminal. The presence of resistor R 0 reduces the negative feedback signal so that only a portion of the feedback signal appears at input voltage Vin_p of op-amp 12 . This reduction in the feedback signal is undesirable.

Furthermore, when transistors M 2 and M 3 suffer from device mismatches due to fabrication process variations, such mismatches will disturb the ratio of their drain currents and will create a change in voltage V BEH . The control loop of op-amp 12 will adjust the voltage at the non-inverting input terminal (node 14 ) to a point where the voltage Vin_p equals the changed voltage V BEH . The PTAT current I PTAT flowing through resistor R 0 is thus changed due to device mismatches.

The PTAT current sensitivity to device mismatches can be analyzed by introducing a voltage, denoted as voltage V OS , between the gate terminals of transistor M 2 and M 3 . A range of non-zero voltage offset values can be applied to voltage V OS to simulate all processing non-uniformities which affect the matching between transistors M 2 and M 3 . FIG. 3 illustrates the response of the reference current I REF for the conventional PTAT current source of FIG. 1 as the offset voltage V OS is varied from −5 mV to 5 mV. The top curve 52 of FIG. 3 illustrates the response of the reference current I REF in current source 10 of FIG. 1 . The simulation result shows that a peak-to-peak current variation of up to 128 nA. Such large variations in the reference current I REF , which translates into variations in the PTAT current I PTAT , is highly undesirable.

A current source for generating a PTAT current that can overcome the disadvantages of the conventional current sources is desired.

According to one embodiment of the present invention, a current source for generating a current proportional to absolute temperature (PTAT) uses a split resistor architecture. The current source includes a first bipolar transistor having an emitter terminal connected to a first power supply voltage, a base terminal coupled to a first node, and a collector terminal coupled to a second node where the first bipolar transistor has a first emitter area, and a second bipolar transistor having an emitter terminal connected to the first power supply voltage, a base terminal and a collector terminal coupled to a third node where the second bipolar transistor has a second emitter area being A times the first emitter area.

The current source further includes a first resistor coupled between the first node and the second node where the first resistor has a resistance value indicative of the emitter resistance r e of the first or second bipolar transistor at a preselected temperature T 0 and a preslected collector current I C and a second resistor coupled between a fourth node and the third node where the second resistor has a resistance value satisfying the equation re*(lnA−1). The current source further includes a current mirror electrically coupled to a second power supply voltage where the current mirror has a first current output terminal coupled to the first node to provide a first current and a second current output terminal coupled to the fourth node to provide a second current, and an operational amplifier having an inverting input terminal coupled to the second node, a non-inverting input terminal coupled to the fourth node and an output terminal providing an output signal being coupled to control the current mirror. The second current provided at the second current output terminal of the current mirror and flowing through the second resistor is the current proportional to absolute temperature and the preslected collector current I C is equal to the second current.

According to another aspect of the present invention, an emitter area trim scheme is applied to the PTAT current source of the present invention employing a split resistor architecture or to conventional PTAT current sources using bipolar transistors of unequal areas to generate a PTAT current. Thus, in one embodiment, the trim scheme is implemented by including in the PTAT current source a set of bipolar transistors having gradually increasing emitter areas and being switchably connected in parallel with the second bipolar transistor in response to a set of programming signals. In operation, one or more of the set of programming signals are asserted to connect one or more of the set of bipolar transistors in parallel with the second bipolar transistor to modify the effective emitter area of the second bipolar transistor. The base terminals of at least the one or more connected bipolar transistors are connected to the respective collector terminals and to the collector terminal of the second transistor. The emitter terminals of at least the one or more connected bipolar transistors are connected to the first power supply voltage.

The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.

FIG. 1 is a circuit diagram illustrating a conventional PTAT current source.

FIG. 2 is a circuit diagram illustrating a PTAT current source according to one embodiment of the present invention.

FIG. 3 illustrates the response of the reference current I REF for the conventional PTAT current source of FIG. 1 and the PTAT current source of the present invention in FIG. 2 as the offset voltage V OS is varied from −5 mV to 5 mV.

FIG. 4 is a circuit diagram of the PTAT current source of FIG. 2 incorporating the emitter area trim scheme according to one embodiment of the present invention.

FIG. 5 , which includes FIGS. 5A and 5B , is a detailed circuit diagram illustrating a PTAT current source according to a third embodiment of the present invention.

FIG. 6 , which includes FIGS. 6A and 6B , is a detailed circuit diagram illustrating a PTAT current source according to a fourth embodiment of the present invention.

In accordance with the principles of the present invention, a current source for providing a current proportional to absolute temperature (a PTAT current) includes two bipolar transistors operating at unequal current densities to create a delta-V BE (ΔV BE ) voltage which is intrinsically PTAT. In general, the ΔV BE voltage is super-imposed across a resistor to produce a PTAT current. In accordance with the present invention, the current source implements a split resistor architecture where the current source includes a first resistor coupled to the unit area bipolar transistor and a second resistor coupled to the A-ratio-area bipolar transistor to form a zero gain amplifier. A voltage indicative of the ΔV BE voltage is super-imposed across the first and the second resistors to provide the PTAT current. The first resistor has a resistance value indicative of the emitter resistance r e of the bipolar transistors while the second resistor has a resistance value satisfying the equation r e *(lnA−1). The first and second resistors operate to significantly reduce output current inaccuracies due to mismatch errors in the current mirror devices supplying the bipolar transistors.

According to another aspect of the present invention, an emitter area trim scheme is applied to a PTAT current source to correct for current source inaccuracies due to fabrication process variations. In particular, the emitter area trim scheme of the present invention enables the simultaneous correction of fabrication process errors that arise from both resistor sheet resistance variations and the bipolar transistor area mismatches. In one embodiment, the emitter area trim scheme is applied to a PTAT current source includes two bipolar transistors having unequal emitter areas and thus operating at unequal current densities. The emitter area trim scheme utilizes an area-DAC (digital-to-analog converter) or ADAC which is programmed to modify the effective emitter area of the A-ratio-area bipolar transistor in the pair of bipolar transistors having 1:A emitter area ratio.

In another embodiment, the ADAC is applied to a PTAT current source of the present invention implementing the split resistor architecture. When trimming is applied to such a PTAT current source using the ADAC, the transconductance (g m ) at the intended operating point of the two bipolar transistors is not affected so that the zero gain amplifier aspect of the two split resistor embodiment preserves its effectiveness in canceling mismatch errors for any choice of target trim values and at any temperature.

Furthermore, according to another aspect of the present invention, when the emitter area trim scheme is applied in a PTAT current source to modify the effective emitter area of the A-ratio-area bipolar transistor, a compensation scheme is applied to the unit area bipolar transistor to reduce errors caused by the resistance introduced due to the coupling of the ADAC to the A-ratio-area bipolar transistor. Specifically, the compensation scheme includes a dummy transistor device or a dummy transistor array coupled to the unit area bipolar transistor where the dummy transistor device or array matches or duplicates the resistance introduced by the ADAC on the A-ratio-area bipolar transistor. The compensation technique substantially reduces the second order errors arising from the base contact resistance and spreading resistances and from the “on” resistances of the switches in the ADAC. These resistances create a voltage error when base current of bipolar transistors in the ADAC flows through them. The matching dummy transistor device or array operates to cancel out errors due to these resistances so that a highly accurate current output can be achieved.

Split Resistor Architecture

FIG. 2 is a circuit diagram illustrating a PTAT current source according to one embodiment of the present invention. In the present embodiment, a PTAT current source 100 utilizes a split resistor architecture for reducing current inaccuracies due to mismatch errors in devices forming the current source. Referring to FIG. 2 , PTAT current source 100 includes NPN bipolar transistors Q 2 and Q 3 of unequal emitter area operating at unequal current densities to generate a voltage difference between the base-to-emitter voltages V BE of the two bipolar transistors. Specifically, bipolar transistor Q 3 is a unit area transistor while bipolar transistor Q 2 is an A-ratio-area transistor having an emitter area that is A times that of transistor Q 3 . The transistors Q 3 to Q 2 are said to have an area ratio of 1:A.

The emitter terminals of NPN bipolar transistors Q 2 and Q 3 are both connected to the negative power supply voltage, that is, the Vss or ground voltage. The base terminal of transistor Q 3 is connected to its collector terminal through a resistor R 2 . The base terminal of transistor Q 2 is connected to its collector terminal. As thus configured, transistor Q 3 generates a V BEH voltage at node 107 while transistor Q 2 generates a V BEL voltage at a node 103 . The difference in the base-to-emitter voltages, given as ΔV BE =V BEH −V BEL , is intrinsically PTAT in nature. A substantially PTAT current can be generated by super-imposing the PTAT voltage ΔV BE across a resistor with low or moderate, fixed temperature coefficient. In the present embodiment, the PTAT voltage ΔV BE is super-imposed across resistor R 2 and R 3 to generate the PTAT current.

PTAT current source 100 further includes a current mirror for supplying currents to bipolar transistors Q 2 and Q 3 . In the present embodiment, the current mirror is implemented as a PMOS cascode current mirror including PMOS transistors M 2 , M 3 , M 47 and M 48 . PMOS transistor M 2 and PMOS transistor M 47 are connected in series between the positive power supply voltage VDD and node 107 for supplying a current to transistor Q 3 . PMOS transistor M 3 and PMOS transistor M 48 are connected in series between the positive power supply voltage VDD and node 104 for supplying a current to transistor Q 2 . Cascode devices M 47 and M 48 have their gate terminals coupled to receive a V bias voltage. Transistors M 2 and M 3 are equally sized PMOS transistors and are driven by a Vgate signal which is a feedback signal in the current source control loop. Transistors M 2 and M 3 are controlled by the Vgate signal to provide currents to bipolar transistors Q 3 and Q 2 .

One of ordinary skill in the art would appreciate that transistors M 47 and M 48 are cascode devices included to improve the power supply rejection characteristics of current source 100 . Transistors M 47 and M 48 may be omitted in other embodiments of the present invention and the drain terminals of transistors M 2 and M 3 can be connected directly to nodes 107 and 104 , respectively, to supply current to bipolar transistors Q 3 and Q 2 . The use of a cascode current mirror in current source 100 is illustrative only and is not intended to be limiting.

In PTAT current source 100 , a split resistor architecture is implemented where, instead of using a single resistor at the A-ratio-area transistor Q 2 as is the case in the conventional current source, two resistors are used with one resistor coupled to each of the pair of bipolar transistors. Thus, in the present embodiment, a resistor R 2 is connected between the base terminal (node 107 ) and the collector terminal (node 106 ) of unit area bipolar transistor Q 3 and a resistor R 3 is connected between the current output node (node 104 ) of the current mirror and the base/collector terminal (node 103 ) of A-ratio-area transistor Q 2 . Resistors R 2 and R 3 have specific resistance values to enable the proper cancellation of mismatch errors in current source 100 , as will be described in more detail below.

In operation, a voltage indicative of the PTAT voltage ΔV BE is super-imposed across resistor R 2 and R 3 to produce a desired output current. The current flowing through resistor R 3 is PTAT (denoted as I PTAT ) when the resistor R 2 and R 3 have a negligible TC (Temperature Coefficient). The exact temperature coefficient of resistor R 2 and R 3 is not critical to the practice of the current source of the present invention. While resistors with low or negligible TC is preferred for resistors R 2 and R 3 when a PTAT output current is desired, resistors having a constant TC can also be used as resistors R 2 and R 3 with the resulting output current having a current vs. temperature slope that is not exactly PTAT. Specifically, when resistor R 3 has a constant TC, the resulting current will have a temperature coefficient having a proportionally factor somewhat less than (sub-PTAT) or greater than (super-PTAT) 100% relative to absolute temperature.

An operational amplifier (op-amp) 102 implements the feedback control loop in current source 100 . The voltage at node 106 , which equals the V BEH voltage (on node 107 ) decreased by the voltage across resistor R 2 , is coupled to the inverting input terminal as the input voltage Vin_n of op-amp 102 . The voltage at node 104 is coupled to the non-inverting input terminal as the input voltage Vin_p of op-amp 102 . Operational amplifier 102 generates an output voltage V OUT (node 108 ) that is coupled to drive the gate and drain terminals of a PMOS transistor M 4 . PMOS transistor M 4 provides a reference current I REF which is absorbed by op-amp 102 , assuming that op-amp 102 is a low output impedance amplifier.

Op-amp 102 generates output voltage V OUT having a voltage value to cause the voltage difference between voltages Vin_p and Vin_n to go to zero. The output voltage V OUT forms the control voltage Vgate which is fed back to drive transistors M 2 and M 3 of the current mirror to cause transistors M 2 and M 3 to provide a certain amount of drain currents. In this manner, the voltage at the top terminal (node 104 ) of resistor R 3 is driven to a voltage value equaling to the voltage on node 106 , which is the V BEH voltage decreased by the voltage across resistor R 2 . A voltage indicative of the ΔV BE voltage is thus super-imposed on resistor R 2 and R 3 . A current flowing through resistor R 3 is thus a PTAT current I PTAT . The operation of the split resistor architecture in current source 100 will be described in detail below.

Because the output voltage V OUT driving the gate terminal of transistor M 4 is also coupled to drive the gate terminals of transistors M 2 and M 3 , transistors M 2 , M 3 and M 4 have the same gate-to-source voltages and thus transistors M 2 , M 3 and M 4 provide the same drain current output. Therefore, the reference current I REF is equal to the PTAT current I PTAT generated at the drain terminal of transistor M 3 and also equal to the current at the drain terminal of transistor M 2 . The drain currents from transistors M 2 and M 3 passes through respective transistors M 47 and M 48 to respective resistors R 2 and R 3 . The ratio between reference current I REF and PTAT current I PTAT remains fixed over process and power supply voltage variations.

The resistance values for resistors R 2 and R 3 satisfy the equation: R 2 +R 3 =R 0 where the resistance value R 0 is defined by equation (3) above and repeated below:

The operation of op-amp 102 is to servo the voltages Vin_p and Vin_n at its input terminals to a null by generating an output voltage V OUT as the control voltage Vgate which operates to force the drain currents of transistors M 2 and M 3 to satisfy the condition:

V BEH −I 2 *R 2 =V BEL +I 3 *R 3   Eq. (4)

where I 2 denotes the drain current from transistor M 2 and I 3 denotes the drain current from transistor M 3 . As discussed above, control voltage Vgate forces transistors M 2 , M 3 and M 4 to the same gate-to-source voltage and thus the transistors provide the same drain currents. Thus, the drain currents of transistors M 2 , M 3 and M 4 satisfy the condition: I 2 =I 3 =I REF and equation (4) can be rewritten as:

V BEH −I REF *R 2= V BEL +I REF *R 3  Eq. (4)

By rearranging terms and substituting V BEH −V BEL =ΔV BE , equation (4) can be used to derive the reference current I REF as follows:

I REF = Δ ⁢ ⁢ V BE R 2 + R 3 = Δ ⁢ ⁢ V BE R 0 = N f ⁢ KT ⁢ ⁢ ln ⁢ ⁢ A qR 0 . Eq . ⁢ ( 5 )

A comparison of equations (1) and (5) reveals that current source 100 generates the same PTAT current as the conventional current source of FIG. 1 . That is, by using the split resistor architecture, the PTAT current generated by current source 100 has not changed from the conventional circuit. However, the resistance values for resistors R 2 and R 3 are advantageously selected to allow careful reduction and balancing of the impedance seen at the input terminals of op-amp 102 .

Specifically, the resistance values for resistors R 2 and R 3 are selected as:

R 2 = r e = N f ⁢ KT 0 qI C , where ⁢ ⁢ I C = I REF ⁢ ⁢ and Eq . ⁢ ( 6 ) R 3 =R 0 −R 2 , where R 0 =r e *ln A   Eq. (7a) R 3 =r e (ln A− 1).  Eq. (7b)

By the above equations, the resistance value for resistor R 2 is selected to be equal to the emitter resistance r e for a given bias condition. Specifically, the resistance value for resistor R 2 is equal to the emitter resistance r e at a temperature of T 0 and a collector current of I C where the collector current I C is equal to the reference current I REF . The temperature T 0 and the current value of current I REF are design parameters for the PTAT current source and desired values can be selected to define the desired emitter resistance value r e for resistor R 2 and, accordingly, the resistance value for resistor R 3 .

When the resistance values for resistors R 2 and R 3 are chosen using the above equations, bipolar transistor Q 3 operates as an inverter with a negative gain of approximately unity. The equivalent impedance seen at the inverting input terminal ( 106 ) of op-amp 102 is (r e −R 2 ) or about zero. When the effective impedance at the inverting input terminal ( 106 ) of op-amp 102 is near zero, device mismatch errors between transistors M 2 and M 3 in the current mirror will have no incremental effect on the voltage Vin_n at the inverting input terminal. Thus, by using a resistor R 2 having a resistance value matching the emitter resistance r e , a major contributor to the current source's operating point inaccuracies is eliminated.

In the conventional current source of FIG. 1 , the effective impedance seen at the inverting input terminal (node 16 ) of op-amp is r e while the effective impedance seen at the non-inverting input terminal (node 14 ) is r e *[1+lnA]. When the split resistor architecture is applied, current source 100 realizes a reduction in the impedance seen by op-amp 102 at both input terminals. Specifically, in current source 100 of the present invention, the effective impedance seen at the inverting input terminal (node 106 ) is nominally zero while the effective impedance seen at the non-inverting input terminal (node 104 ) is: r e +r e [lnA−1] or r e *lnA. Thus, it can be readily observed that the impedances at both input terminals of op-amp 102 have been reduced as compared to the conventional circuit. Current source 100 has zero impedance instead of an impedance of r e at the inverting input terminal while an impedance of r e *lnA instead of an impedance of r e *[1+lnA] at the non-inverting input terminal of op-amp 102 .

In the present embodiment, resistors R 2 and R 3 are chosen to have a very low temperature coefficient (TC<75 ppm/° C.). Thus, the resulting PTAT currents flowing through resistors R 2 and R 3 are about 98.7% PTAT. Bipolar transistor Q 3 together with resistor R 2 in the current source core is called a “zero gain amplifier” because the amplifier's sensitivity to incremental changes in the current supplied to the circuit branch is suppressed by a large amount as compared to the conventional case where the circuit branch includes only a diode-connected bipolar transistor. In one embodiment, a 50× improvement is realized. The high degree of error cancellation realized by the zero gain amplifier of resistor R 2 and transistor Q 3 is maintained well over a large temperature range because, in equation (6) above, the ratio of the absolute temperature term in the numerator to the temperature dependent current in the denominator (I C or I REF ) remains nearly constant. This condition, in turn, maintains r e nearly constant with changes in temperature, preserving the desired result of (r e −R 2 ) being nearly equal to zero.

FIG. 3 illustrates the response of the reference current I REF for the conventional PTAT current source of FIG. 1 and the PTAT current source of the present invention in FIG. 2 as the offset voltage V OS is varied from −5 mV to 5 mV. The improvement provided by the PTAT current source 100 of the present invention can be readily observed from the simulation plots in FIG. 3 where an offset voltage is introduced between the gate terminals of transistors M 2 and M 3 in the PMOS current mirror to simulate mismatch errors between the two transistors. In the simulation plots of FIG. 3 , the offset voltage V OS is varied about ±5.0 mV.

The top simulation plot (curve 52 ) illustrates the variation in the reference current I REF over variations of the offset voltage between transistors M 2 and M 3 in the conventional current source of FIG. 1 . The simulation plot shows that a total variation in the reference current of about 128 nA from end to end of the offset voltage range is observed. The bottom simulation plot (curve 54 ) illustrates the variation in the reference current I REF over variations of the offset voltage between transistors M 2 and M 3 in current source 100 of FIG. 2 of the present invention. The simulation plot shows that the total variation in the reference current is only about 2.6 nA from peak to peak. The current variation range achieved by the current source of the present invention represents an approximately 50× reduction in sensitivity to offset voltage mismatch between the transistors in the PMOS current mirror as compared to the conventional PTAT current source.

Another characteristic of the PTAT current source of the present invention that can be observed from FIG. 3 is that the variation in the reference current due to offset voltages is centered about the zero volt offset. Thus, the PTAT current source of the present invention utilizing a split resistor architecture is capable of nearly perfect rejection of small perturbation around a zero voltage offset. When the offset voltage is larger, the matching of resistor R 2 to the emitter resistance r e is disturbed because the resistance of resistor R 2 is not a function of current as is the emitter resistance r e .

Emitter Area Trim Scheme

According to another aspect of the present invention, an emitter area trim scheme is implemented in a PTAT current source to effectively compensate for both area mismatch errors and for sheet resistance variations in the PTAT current source. By applying the trim scheme to cancel out both types of fabrication process variation errors, a more accurate PTAT current source can be realized. Furthermore, the trim scheme can be implemented with minimal increase in circuit complexity and circuit area.

The trim scheme of the present invention is particularly applicable to the PTAT current source where a pair of unequal sized bipolar transistors, biased by an equal sized, unity ratioed current mirror, is used to generate a PTAT current. In one embodiment, the trim scheme of the present invention is implemented as an emitter area trim scheme where an area-DAC (digital-to-analog converter) or ADAC is used to modify the effective emitter area of the A-ratio-area bipolar transistor in the pair of bipolar transistors having 1:A emitter area ratio.

The emitter area trim scheme of the present invention can be applied to the conventional PTAT current source of FIG. 1 as well as the inventive PTAT current source of the present invention employing a split resistor architecture, such as that shown in FIG. 2 . In the following description, the trim scheme of the present invention is described as being applied to the PTAT current source of FIG. 2 using a split resistor architecture. However, the description is illustrative only and is not intended to limit the use of the emitter area trim scheme of the present invention to the PTAT current source of FIG. 2 only. One of ordinary skill in the art would appreciate that the emitter area trim scheme of the present invention can be applied to other PTAT current source including a pair of unequal sized bipolar transistors.

FIG. 4 is a circuit diagram of the PTAT current source of FIG. 2 incorporating the emitter area trim scheme according to one embodiment of the present invention. The construction of the basic PTAT current source cell is the same as that of FIG. 2 and will not be further described. In the embodiment shown in FIG. 4 , PTAT current source 200 includes a pair of unequal size NPN bipolar transistors Q 3 and Q 2 having a size ratio of 1:11. That is, the area ratio A is 11 in the present embodiment. The emitter area trim scheme is implemented by using a bank of NPN bipolar transistors Q 8 to Q 10 , switchably coupled in parallel with the A-ratio-area bipolar transistor Q 2 , to modify the effective emitter area of transistor Q 2 .

The emitter area trim scheme of the present invention is effective in correcting for both the bipolar device area mismatch errors and the sheet resistance variation errors in a PTAT current source. Specifically, due to fabrication process variations, the pair of bipolar transistors may not have the ideal area ratio of 1:A due to mismatches in the emitter area of transistors Q 2 and Q 3 . Furthermore, due to fabrication process variations, the sheet resistance of the resistors R 2 and R 3 will vary. These errors and variations introduce inaccuracies in the reference current generated by the PTAT current source. However, by inspection of equation (5) above and rewritten below, the reference current I REF is given as:

I REF = N f ⁢ KT ⁢ ⁢ ln ⁢ ⁢ A q ⁡ ( R 2 + R 3 ) . Eq . ⁢ ( 5 )

Thus, in order to compensate for errors in reference current I REF , only the area ratio A needs to be adjusted and the area adjustment can account for both sources of DC errors discussed above (i.e. bipolar device mismatch and sheet resistance variation). In accordance with the present invention, an area DAC (digital-to-analog converter) is implemented in the PTAT current source to allow the emitter area ratio to be trimmed or fine tuned. In this manner, first order DC errors caused by bipolar device mismatch and sheet resistance variations can be effectively removed to greatly improve the accuracy and performance of the PTAT current source.

Referring to FIG. 4 , bipolar transistors Q 8 , Q 9 and Q 10 form an area DAC controlled by digital input signals d 1 to d 3 . One or more of bipolar transistors Q 8 to Q 10 are successively brought in to be connected in parallel with bipolar transistor Q 2 by programming the trim code defined by signals d 1 to d 3 . Bipolar transistors Q 8 to Q 10 are provided with different emitter areas to allow a variety of possible emitter areas to be obtained from the parallel combination of transistors Q 2 and one or more of transistors Q 8 to Q 10 . In the present embodiment, bipolar transistor Q 2 has an emitter area of 11 units. Bipolar transistor Q 8 has the same emitter area of 11 units while bipolar transistors Q 9 and Q 10 have successively decreasing emitter areas. Specifically, bipolar transistor Q 9 has an emitter area of 8 units while bipolar transistor Q 10 has an emitter area of 5 units.

By using the emitter areas in the ADAC as described above, with only transistor Q 2 being selected and with each programming bipolar transistor being successively brought in, the following sequence of effective/modified emitter area A′ for transistor Q 2 can be obtained: 11, 16, 24 and 35. As the effective emitter area A′ of transistor Q 2 varies, the ΔV be voltage between nodes 207 and 203 varies, at +25° C., in a sequence approximately equal to: 61.93 mV, 71.61 mV, 82.08 mV and 90.3 mV. Those skilled in the art will realize that other switching schemes to control independent transistors Q 8 , Q 9 , Q 10 and Q 2 would result in more choices for the effective emitter area A′. With the area values denoted above for these 4 transistors, 12 unique values for the effective emitter area A′ are possible and up to 16 unique combinations are ultimately possible if the emitter area of Q 8 is itself unique.

In the present embodiment, the ADAC formed by bipolar transistors Q 8 , Q 9 and Q 10 is switchably connected in parallel with bipolar transistor Q 2 through a set of PMOS transistors M 50 , M 52 , and M 54 . A set of NMOS transistors M 51 , M 53 , and M 55 are provided to disable the ADAC bipolar transistors when the transistors are not selected by the trim code. As thus constructed, a PMOS transistor and an NMOS transistor form an inverter receiving a programming signal. The output signal of each inverter formed by a pair of PMOS and NMOS transistors drives the base terminal of a respective bipolar transistor. For instance, PMOS transistor M 50 and NMOS transistor M 51 form an inverter to drive bipolar transistor Q 8 having an emitter area of 11 units, PMOS transistor M 52 and NMOS transistor M 53 form an inverter to drive bipolar transistor Q 9 having an emitter area of 8 units, and finally, PMOS transistor M 54 and NMOS transistor M 55 form an inverter to drive bipolar transistor Q 10 having an emitter area of 5 units.

Each of bipolar transistors Q 8 to Q 10 has collector terminal connected to node 203 which is the collector terminal of transistor Q 2 and has emitter terminal connected to the Vss or ground node where the emitter terminal of transistor Q 2 is also connected. When a programming signal d 1 to d 3 is asserted (active low), the corresponding PMOS transistor is turned on and the corresponding NMOS transistor is turned off, the base terminal of the respective bipolar transistor Q 8 to Q 10 is then connected to node 203 , activating the bipolar transistor and connecting the bipolar transistor in parallel with transistor Q 2 . When a programming signal d 1 to d 3 is deasserted (active high), the corresponding PMOS transistor is turned off and the corresponding NMOS transistor is turned on, the base terminal of the respective bipolar transistor Q 8 to Q 10 is thus grounded and the bipolar transistor is thus deactivated.

In the present embodiment, a dummy inverter formed by PMOS transistor M 56 and NMOS transistor M 57 is provided at bipolar transistor Q 2 . The input signal to the inverter is connected to the Vss voltage so that the PMOS transistor M 56 is always turned on and the NMOS transistor M 57 is always turned off. In this manner, bipolar transistor Q 2 is permanently turned on with the base terminal being connected to the collector terminal through PMOS transistor M 56 . The provision of dummy inverter in current source 200 ensures symmetry between bipolar transistor Q 2 and the programming bipolar transistors Q 8 to Q 10 . When one or more of programming bipolar transistors Q 8 to Q 10 are brought in to modify the effective emitter area of transistor Q 2 , the base terminals of the connected programming bipolar transistors are connected to node 203 through their respective PMOS transistors. The base current of the programming bipolar transistor flowing through the associated PMOS transistor results in a voltage drop across the PMOS transistor due to the PMOS transistor's “on” resistance. Thus, in the ADAC, a voltage drop is present between the collector and base terminals of each connected programming bipolar transistor. To ensure symmetry, the dummy PMOS transistor M 56 is coupled to bipolar transistor Q 2 to ensure that the same voltage drop is seen across the base and collector terminals of transistor Q 2 .

Furthermore, in the present embodiment, the widths of PMOS transistors M 50 , M 52 , M 54 and M 56 are selected to be proportional to the emitter area of the associated bipolar transistors. That is, PMOS transistor M 50 , associated with bipolar transistor Q 8 having an emitter area unit of 11, has a width of 11 units. PMOS transistor M 52 , associated with bipolar transistor Q 9 having an emitter area unit of 8, has a width of 8 units. PMOS transistor M 54 , associated with bipolar transistor Q 10 having an emitter area unit of 5, has a width of 5 units. Finally, PMOS transistor M 56 , associated with bipolar transistor Q 2 having an emitter area unit of 11, has a width of 11 units. The use of proportionally sized PMOS transistors M 50 , M 52 , M 54 and M 56 has the effect of equalizing the voltage drop across the PMOS transistors so that the same voltage drop is seen by the bipolar transistors Q 2 and Q 8 to Q 10 . Specifically, because each bipolar transistors Q 2 and Q 8 to Q 10 is unevenly sized, each transistor carries a different base current. By matching the width of the PMOS transistor to the emitter area of the associated bipolar transistor, the voltage drop across all of the PMOS transistors can be kept close to the same voltage value. For example, since bipolar transistor Q 10 has a small emitter area, the base current for transistor Q 10 is decreased. By flowing the smaller base current of transistor Q 10 through PMOS transistor M 54 having a smaller width, the same voltage drop is obtained across transistor M 54 as in the other PMOS transistors.

An important advantage of the emitter area trim scheme of the present invention is that the trim scheme can be applied to correct for both bipolar transistor area mismatch errors and resistor sheet resistance variations at once without need to know the individual contribution of each error to the overall inaccuracy. Essentially, if there is a combination of errors from area mismatch between transistors Q 2 and Q 3 and from sheet resistance variations in the resistance of resistors R 2 and R 3 , there will be some choice of the area DAC that will bring the output current I REF closest to the target value. This results in a precise PTAT current output is generated.

In other words, voltages V BEH and V BEL will be affected by effective area mismatches between all five NPN bipolar transistors (Q 2 , Q 3 , Q 8 to Q 10 ). But as far as the PTAT current source core is concerned, there will be one best choice out of all of the programming possibilities that will yield a reference current that is closest to an absolute target value. Thus, by selecting none or one or more of the programming bipolar transistors, the PTAT current output of current source 200 can be effectively trimmed.

In current source 200 of FIG. 4 , the emitter area trim scheme is applied to a PTAT current source using a split resistor architecture for PMOS current mirror mismatch cancellation. An important characteristic of the split resistor architecture employed in the PTAT current source of FIGS. 2 and 4 is that the operation of the current mirror mismatch cancellation scheme using split resistors depends only on the matching of resistors R 2 and R 3 and matching of the 1/ gm of transistors Q 2 , Q 3 to work. The current mirror mismatch cancellation scheme does not depend on the effective emitter area A′ of the bipolar transistor Q 2 . This is because the g m of a bipolar transistor depends only on its collector current. Thus, the current mirror mismatch cancellation scheme using split resistors is trim area independent and furthermore, it is temperature independent. Therefore, the use of the area DAC in the PTAT current source 200 of FIG. 4 does not affect the operation of the current mirror mismatch cancellation scheme using split resistors.

The current mirror mismatch cancellation scheme using split resistors is temperature independent for the following reasons. The 1/g m term of bipolar transistor Q 2 or Q 3 is given as:

1 / g m = N f ⁢ KT q ⁡ ( I C ⁡ ( T ) ) , Eq . ⁢ ( 8 )

where I C (T) is the collector current of the bipolar transistor and is normally constant over temperature. 1/g m thus becomes PTAT (temperature dependent) because of the temperature T term in the numerator of equation (8). In actual operation, it is desirable that 1/g m tracks the resistance of resistor R 2 over temperature. Thus, by making the collector current I C (T) PTAT (temperature dependent), which naturally occurs in a PTAT current source bias cell, the term [R(T)−1/g m (T)] will nearly equal zero for all temperatures, thus maintaining the zero gain amplifier's ability to cancel PMOS current mirror device mismatch errors.

Thus, the emitter area trim scheme and the current mirror mismatch cancellation scheme can be applied to improve the accuracy of the PTAT current source. Once trimming is applied by selecting a value for the ADAC, there is no remaining temperature dependent error caused by the trimming. The temperature independent characteristics of the trim scheme represent a marked improvement over conventional trim schemes. The conventional trim schemes often have the result that the trimmed behavior is not guaranteed to be effective over all temperature range. Thus, when the conventional trim scheme is performed at one temperature, there is no guarantee that the accuracy of the trim result holds at other temperatures. However, the emitter area trim scheme of the present invention provides a trim result that is consistent over all temperatures. Thus, it is immaterial at which temperature the emitter area trim scheme is applied. When the best trim is applied at one temperature, the same accuracy of trim result will be guaranteed at other temperatures.

ADAC Compensation Scheme

In current source 200 of FIG. 4 , when the ADAC is incorporated in the current source to implement emitter area trimming, the base terminal of transistor Q 2 , and that of any connected programming bipolar transistors, is connected to the collector terminal through a PMOS transistor. Because the base current of transistor Q 2 is non-zero and the “on” resistance of PMOS transistor M 56 is also non-zero, there is a finite voltage drop across PMOS transistor M 56 . This finite voltage drop between the collector and base terminals, if left uncorrected, introduces a voltage error in the ΔV BE voltage of PTAT current source 200 .

According to one aspect of the present invention, an ADAC compensation scheme is implemented in PTAT current source 200 which applies symmetry to cancel out the voltage error caused by the “on” resistance of the PMOS transistors in the ADAC. Basically, symmetry between bipolar transistors Q 2 and Q 3 is achieved by using one or more dummy PMOS transistors to introduce the same voltage drop between the collector terminal (node 207 ) and the base terminal of transistor Q 3 so that transistors Q 2 and Q 3 experience the same collector-to-base voltage drop.

The cancellation of the voltage drop by using symmetry can be illustrated by inspecting the equation for the actual PTAT current generated by current source 200 which is given as follows:

I actual = N f ⁢ KT q ⁢ ln ⁡ ( A + β 3 ⁡ ( β 2 - 1 ) β 2 ⁡ ( β 3 - 1 ) ) R 0 + ( r bb2 + R on2 1 + β 2 - r bb3 + R on3 1 + β 3 ) Eq . ⁢ ( 9 )

where β 2 , β 3 are the ratio of the collector current to base current of bipolar transistors Q 2 and Q 3 ; rbb 2 , rbb 3 are base resistances of transistors Q 2 and Q 3 ; and R on2 , R on3 are on-resistance of the PMOS transistors associated with transistors Q 2 and Q 3 . As observed from equation (9) above, cancellation of the voltage drop due to the PMOS transistors used for emitter trimming can be realized by providing the same on-resistance at transistor Q 3 to achieve symmetry.

In the embodiment shown in FIG. 4 , the ADAC compensation scheme is implemented by adding a single PMOS transistor, such as PMOS transistor M 49 , between the collector terminal (node 207 ) and the base terminal of transistor Q 3 . PMOS transistor M 49 has its control terminal connected to the Vss voltage so that the transistor is always on. Thus, PMOS transistor M 49 is a dummy transistor and is added to the unit area transistor Q 3 only for the purpose of compensating for the voltage drop error at the A-ratio-area transistor Q 2 . The width of M 49 is selected in a way so as to compensate for the “on” resistance error due to any combinations of PMOS transistors M 50 , M 52 , M 54 and M 56 as transistor M 56 alone or one or more of PMOS transistors M 50 , M 52 and M 54 can be turned on by the trimming process. In one embodiment, an optimum value for the size of PMOS transistor M 49 is one where the “on” resistance of transistor M 49 matches the geometric mean of the “on” resistance of all of the possible parallel combinations of PMOS transistors in the ADAC, including PMOS transistor M 56 . In the present embodiment, the width for transistor M 49 is 20 units.

In another embodiment, instead of using a single dummy PMOS transistor having a specific size coupled to transistor Q 3 , a dummy transistor array can be used for the ADAC voltage drop compensation. FIG. 5 , which includes FIGS. 5A and 5B , is a detailed circuit diagram illustrating a PTAT current source according to a third embodiment of the present invention. FIG. 6 , which includes FIGS. 6A and 6B , is a detailed circuit diagram illustrating a PTAT current source according to a fourth embodiment of the present invention. FIGS. 5 and 6 illustrate implementation of the ADAC compensation scheme using a duplicate DAC array at the unit area bipolar transistor Q 3 . The duplicate DAC array can be a static array with all transistors being permanently turned on or the duplicate DAC array can be a dynamic array with each transistor in the duplicate DAC array being turned on in response to the programming signal. The dynamic duplicate DAC array perfectly matches the trim scheme DAC with perfect symmetry and error cancellation, while the static duplicate DAC array usefully approaches the same level of performance as a dynamic duplicate DAC array.

Referring to FIG. 5A , a duplicate DAC array including PMOS transistors M 60 , M 61 and M 62 , connected in parallel, is coupled between the V BEH node (node 307 ) and the base terminal of bipolar transistor Q 3 . PMOS transistors M 60 , M 61 and M 62 have sizes matching the sizes of PMOS transistors M 56 , M 54 and M 52 in the ADAC. Thus, transistor M 60 has a width of 11, transistor M 61 has a width of 5 and transistor M 62 has a width of 8, matching transistors M 56 , M 54 and M 52 respectively. PMOS transistors M 60 , M 61 and M 62 in the duplicate DAC array have their gate terminals connected to the Vss voltage so that they are always on. The duplicate DAC array of transistors M 60 , M 61 and M 62 is configured to duplicate the PMOS transistors in the ADAC that are turned on when the trim code is in the center of the trim range. That is, when the trim code d 1 to d 3 has a value of “001” which is in the center of the trim range, transistors M 56 , M 54 and M 52 in the ADAC coupled to bipolar transistor Q 2 are turned on. The duplicate DAC array of transistors M 60 , M 61 and M 62 matches the three transistors that are turned on for the trim code “001”. By using the duplicate DAC array as shown in FIG. 5A , symmetry between transistors Q 2 and Q 3 is made as close as possible to eliminate voltage errors caused by the PMOS transistors in the ADAC.

Referring to FIG. 6A , a duplicate DAC array including PMOS transistors M 81 , M 82 , M 83 and M 84 , connected in parallel, is coupled between the V BEH node (node 307 ) and the base terminal of bipolar transistor Q 3 . As in the case of the duplicate DAC array in FIG. 5A , PMOS transistors M 81 , M 82 , M 83 and M 84 have sizes matching the sizes of the PMOS transistors in the ADAC. Thus, transistor M 81 has a width of 11, transistor M 82 has a width of 11, transistor M 83 has a width of 8 and transistor M 84 has a width of 5, matching transistors M 56 , M 50 , M 52 and M 54 respectively. The duplicate DAC array of FIG. 6A is a dynamic array. PMOS transistor M 81 duplicates M 56 and has its gate terminal connected to the Vss voltage so that transistor M 81 is always turned on as in the case of transistor M 56 . The gate terminals of PMOS transistors M 82 , M 83 and M 84 are connected to programming signals d 3 , d 2 and d 1 , respectively. Thus, when a programming signal is asserted to select one of the programming bipolar transistors Q 8 to Q 10 in the ADAC, the corresponding one or more PMOS transistors in the duplicate DAC array are also turned on to introduce an on-resistance at the base terminal of transistor Q 3 to realize perfect symmetry between transistors Q 2 and Q 3 .

FIGS. 5 and 6 also illustrate the detail implementation of the operational amplifier in one embodiment of the PTAT current source of the present invention. The implementation of operational amplifier in FIGS. 5 and 6 is identical and thus the description below is made with reference to FIG. 5 only.

Referring to FIG. 5B which illustrates the op-amp circuitry in PTAT current source 300 , all of the transistors in the op-amp operate at fixed ratios to the PTAT core current, which is very nearly supply voltage and process independent while being linearly dependent on temperature (PTAT). In a conventional PTAT current source, at least some of the transistors are biased from independent bias generating circuitry, mitigating the ability to have all drain currents and drain-to-source voltages of the operational amplifier to be highly symmetrical and thus reducing performance capability of the conventional PTAT current source.

To further enhance the performance of the PTAT current source of the present invention, the input topology of the differential amplifier of the op-amp input stage is designed with a high degree of symmetry so that nominally equal error sources are cancelled. The PTAT current I REF generated at the output of the op-amp is routed through transistors M 76 to M 77 to bias the tail current of the differential amplifier of the operational amplifier. In this manner, first order symmetry for all PMOS drain currents is achieved. The op-amp load cells (M 4 , M 75 , M 76 , M 79 and M 78 ) are both current mirrors. The current mirrors' equal area construction combined with a topology where each PMOS drain voltage is terminated by an essentially equal, Vdd independent value, makes for extreme symmetry of operation in the operating points of all of the critical op-amp devices.

The operational amplifier in FIG. 5B includes a start-up circuit for properly biasing the op-amp during circuit start-up. PMOS transistors M 65 and M 66 in the start-up circuit are of different size and thus have different threshold voltages. In operation, PMOS transistors M 65 and M 66 form a differential pair for sensing the voltage difference between the V BE voltages and the gate-to-source voltage of transistor M 77 providing the tail current to the differential amplifier. The width-to-length ratio of PMOS transistor M 65 is made higher than that of PMOS transistor M 66 in order to turn on PMOS transistor M 65 first during the initial startup. A long channel PMOS transistor M 63 provides the start-up current. When the V BE voltage is low and the op-amp has not started up, then the start-up circuit provides a start-up current through transistor M 65 that flows into the diode connected NMOS transistor M 76 , which then controls the tail current of the differential pair and the bias voltage (Vbias) for the PMOS cascode current mirror. When the gate voltage at transistor M 77 is very low, transistor M 65 will direct all the current from transistors M 63 and M 64 to transistor M 76 . The current flow raises the voltage at drain terminal of transistor M 75 so that current flows in M 4 and M 75 .

Once the input voltage to the differential amplifier raises to a normal operating value, the start-up current is not steered into transistor M 76 through transistor M 65 , but instead is steered through transistor M 66 to ground so that the start-up current does not contribute a current error in normal operation.

In the present illustration, PMOS transistor M 64 is controlled by a reset_lo signal which is turned off to cut off the start-up current when “reset_lo” goes high.

In the differential amplifier input stage of the operational amplifier, a highly symmetrical topology is used that allows for the maximum cancellation of like errors when the op-amp is biased as described above. The symmetrical topology is further enhanced by the application of well known chopping techniques to both the op-amp input transistors M 67 , M 68 and the first stage current mirror transistors M 69 , M 70 . The chopping technique essentially eliminates op-amp offset voltage errors, further improving the performance of the PTAT current source.

Due to mismatches in the differential pair in the op-amp, the accuracy and stability of the reference current is adversely affected. The mismatch errors can arise from the NMOS input pair or the PMOS current mirror in the differential pair. The chopping scheme, implemented by transistors M 71 - 74 and M 92 - 95 , operates to transpose the mismatched PMOS current mirror and the mismatched NMOS differential pair half of the time, thus canceling the effect of these mismatches at the system level.

In current source 300 of FIG. 5 , the reference current I REF is provided at the drain terminal of PMOS transistor M 75 . The gate voltage “Idrive” of PMOS transistor M 4 is the gate voltage driving the PMOS current mirror transistors M 2 , M 3 of the PTAT current source core.

A key characteristic of the PTAT current source 300 of the present invention is a very high power supply rejection ratio (PSRR) over process variations and over the entire operating power supply voltage range. The high PSRR is achieved by the use of cascode devices M 47 and M 48 in the PMOS current mirrors and by ensuring that the termination voltages of all the current mirrors in the PTAT current source are nearly equal in magnitude wherever possible.

As described above, the PTAT current source 300 operates at a scaled replica of the basic PTAT reference current I REF . Additional current outputs can be added simply by replicating the master reference cell (PMOS transistors M 3 , M 48 ) and connecting current mirrors in parallel with the master reference cell. For example, in PTAT current source 300 , PMOS transistors M 41 and M 42 are connected in parallel with transistors M 3 and M 48 to provide a PTAT current output I PTAT .

By using one or more of the techniques described above, a PTAT current source achieving a high level of performance is realized while consuming minimal operating current and requiring little added complexity or area to implement.

The above detailed descriptions are provided to illustrate specific embodiments of the present invention and are not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is defined by the appended claims.