LexDanaLexDanabeta
Inventor

Jun Wan

Inventor
San Jose, CA, US

Overview

98→
Patents
2004–2021
Patent span
Physics
Primary field (CPC G)

Patents· 98 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores39%
G06FElectric digital data processing11%
G01KMeasuring temperature4%
G05FSystems for regulating electric or magnetic variables4%
H03MCoding4%
G06TImage data processing or generation, in general3%
H01LSemiconductor devices3%
H03KPulse technique3%
H10BElectronic memory devices3%
G01RMeasuring electric variables2%
PatentTitleYear
11,055,350Method and system for abstracting information for use in link analysis202110,908,331Display substrate, manufacturing method thereof and display panel202110,353,598System and method for refreshing data in a memory device201910,229,744First read countermeasures in memory201910,115,737Charge storage region in non-volatile memory201810,034,414Modular data center201810,026,486First read countermeasures in memory201810,007,311Adaptive temperature and memory parameter throttling20189,899,410'Charge storage region in non-volatile memory'20189,785,719'Generating synthetic data'20179,734,705'Logo assembly of an electronic device'20179,710,325'On chip dynamic read level scan and error detection for nonvolatile storage'20179,564,233'Open block source bias adjustment for an incompletely programmed block of a nonvolatile storage device'2017RE046264'Verification process for non-volatile storage'20179,530,504'Memory cells using multi-pass programming'20169,455,531'Electric connector for flat conductor'20169,355,713'Systems and methods for lower page writes'2016D0757769'Display screen or portion thereof with a graphical user interface'20169,237,293'Remote control system, remote controller, display device and remote control method'20169,214,009'Image registration device and method, image segmentation device and method and medical image apparatus'20159,134,327'STAT3 and TYK2 as drug targets for neurodegenerative diseases'20159,070,762'Lead frame support plate and window clamp for wire bonding machines'20159,047,970'Word line coupling for deep program-verify, erase-verify and read'20159,041,863'Electronic device and method for displaying resources'20159,036,417'On chip dynamic read level scan and error detection for nonvolatile storage'2015RE045515'Built in on-chip data scrambler for non-volatile memory'20158,937,835'Non-volatile storage with read process that reduces disturb'20158,902,652'Systems and methods for lower page writes'20148,880,964'Block and page level bad bit line and bits screening methods for program algorithm'20148,843,693'Non-volatile memory and method with improved data scrambling'20148,792,729'Image processing apparatus and method'20148,752,751'Lead frame support plate and window clamp for wire bonding machines'20148,737,125'Aggregating data latches for program level determination'20148,693,259'Wordline-to-wordline stress configuration'20148,570,810'Intelligent control of program pulse for non-volatile storage'20138,472,266'Reducing neighbor read disturb'20138,473,809'Data coding for improved ECC efficiency'20138,453,726'Corrugated settling cup and a multi-cup uniform flux gas anchor'20138,429,330'Method for scrambling data in which scrambling data and scrambled data are stored in corresponding non-volatile memory locations'20138,416,624'Erase and programming techniques to reduce the widening of state distributions in non-volatile memories'20138,379,454'Detection of broken word-lines in memory arrays'20138,368,137'Dual bit line metal layers for non-volatile memory'20138,218,367'Verification process for non-volatile storage'20128,145,855'Built in on-chip data scrambler for non-volatile memory'20128,097,504'Method for forming dual bit line metal layers for non-volatile memory'20128,036,044'Dynamically adjustable erase and program levels for non-volatile memory'20117,978,527'Verification process for non-volatile storage'20117,652,918'Retention margin program verification'20107,630,249'Intelligent control of program pulse duration'20097,616,499'Retention margin program verification'20097,606,074'Word line compensation in non-volatile memory erase operations'20097,580,290'Non-volatile storage system with intelligent control of program pulse duration'20097,577,034'Reducing programming voltage differential nonlinearity in non-volatile storage'20097,512,014'Comprehensive erase verification for non-volatile memory'20097,508,720'Systems for comprehensive erase verification in non-volatile memory'20097,495,956'Reducing read disturb for non-volatile storage'20097,474,230'RFID temperature logger incorporating a frequency ratio digitizing temperature sensor'20097,463,532'Comprehensive erase verification for non-volatile memory'20087,457,178'Trimming of analog voltages in flash memory devices'20087,454,319'System, method, and computer program product for determining wall thickness in graphic model'20087,452,231'Portable electronic device'20087,450,435'Systems for comprehensive erase verification in non-volatile memory'20087,450,433'Word line compensation in non-volatile memory erase operations'20087,447,065'Reducing read disturb for non-volatile storage'20087,447,086'Selective program voltage ramp rates in non-volatile memory'20087,443,226'Emitter area trim scheme for a PTAT current source'20087,440,318'Reducing read disturb for non-volatile storage'20087,385,426'Low current offset integrator with signal independent low input capacitance buffer circuit'20087,372,392'Charge balancing method in a current input ADC'20087,349,258'Reducing read disturb for non-volatile storage'20087,331,708'Frequency ratio digitizing temperature sensor with linearity correction'20087,299,165'System, method, and computer program product for identifying manufacturing-specific regions in object models'20077,295,478'Selective application of program inhibit schemes in non-volatile memory'20077,295,473'System for reducing read disturb for non-volatile storage'20077,262,994'System for reducing read disturb for non-volatile storage'20077,254,071'Flash memory devices with trimmed analog voltages'20077,236,048'Self-regulating process-error trimmable PTAT current source'20077,230,854'Method for programming non-volatile memory with self-adjusting maximum program loop'20077,218,552'Last-first mode and method for programming of non-volatile memory with reduced program disturb'20077,206,231'System for programming non-volatile memory with self-adjusting maximum program loop'20077,170,788'Last-first mode and apparatus for programming of non-volatile memory with reduced program disturb'20077,161,836'Method for programming non-volatile memory with self-adjusting maximum program loop'20077,119,612'Dual-channel instrumentation amplifier'20067,075,360'Super-PTAT current source'20067,075,475'Correlated double sampling modulation system with reduced latency of reference to input'20067,075,353'Clock generator circuit stabilized over temperature, process and power supply variations'20067,023,737'System for programming non-volatile memory with self-adjusting maximum program loop'20067,015,744'Self-regulating low current watchdog current source'20067,015,732'Power-on reset circuit with low standby current and self-adaptive reset pulse width'20067,009,889'Comprehensive erase verification for non-volatile memory'20066,962,436'Digitizing temperature measurement system and method of operation'20056,957,910'Synchronized delta-VBE measurement system'20056,930,495'Digitizing ohmmeter system'20056,903,558'Digitizing ohmmeter system'20056,869,216'Digitizing temperature measurement system'20056,831,504'Constant temperature coefficient self-regulating CMOS current source'20046,750,796'Low noise correlated double sampling modulation system'20046,736,540'Method for synchronized delta-VBE measurement for calculating die temperature'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2009Patents assigned to NAT SEMICONDUCTOR CORP (20)· patent assignee history
2004–2006Based in Haverhill, MA, US· patent location history
2006–2010Patents assigned to SANDISK CORP (27)· patent assignee history
2006–2010Based in Sunnyvale, CA, US· patent location history
2006–2009Based in Wilmington, MA, US· patent location history
2008–2016Patents assigned to WAN JUN (19)· patent assignee history
2009–2019Based in San Jose, CA, US· patent location history
2011–2019Patents assigned to SANDISK TECHNOLOGIES INC (27)· patent assignee history
2014–2021Based in Beijing, CN· patent location history
2016–2019Patents assigned to SANDISK TECHNOLOGIES LLC (10)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SANDISK CORP272006–2010
SANDISK TECHNOLOGIES INC272011–2019
NAT SEMICONDUCTOR CORP202004–2009
WAN JUNself192008–2016
SANDISK TECHNOLOGIES LLC102016–2019
Locations
LocationPatentsSpan
San Jose, California, US342009–2019
Sunnyvale, California, US252006–2010
Wilmington, Massachusetts, US102006–2009
Haverhill, Massachusetts, US102004–2006
Beijing, CN82014–2021