Frequency divider monitor of phase lock loop

This patent application is a continuation in part of U.S. patent application Ser. No. 11/276,410, filed Feb. 28, 2006 now U.S. Pat. No. 7,362,184, which is assigned to the present assignee.

The present invention relates to the field of frequency divider circuits; more specifically, it relates to a design structure comprising circuits for monitoring the operation frequency of the divider circuits.

In modern integrated circuits and electronic systems, clock signals are generated using phase lock loop circuits that use frequency feedback to generate a clock signal with stable frequency value and constant phase performance. Frequency dividers are one of the most prone to failure components of the high speed phase lock loops. In one failure mode, the output frequency of the frequency divider changes from design or drifts. In such a case, the integrated circuit or electronic system to which the clock signal is supplied can malfunction. Therefore, there is a need for methods and circuits for monitoring operation of the frequency dividers of integrated circuits and electronic systems.

A first aspect of the present invention is a design structure for designing, manufacturing, and/or testing a circuit, the circuit comprising: a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of the voltage controlled oscillator connected to an input of the feedback frequency divider, an output of the feedback frequency divider coupled to an input of the voltage controlled oscillator; and a frequency divider monitor having a first input, a second input and an output, the first input of the frequency divider monitor connected to the output of the voltage controlled oscillator and the second input of the frequency divider monitor coupled to an output of the feedback frequency divider.

A second aspect of the present invention is a method, comprising: providing a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of the voltage controlled oscillator connected to an input of the feedback frequency divider, an output of the feedback frequency divider coupled to an input of the phase detector; providing a frequency divider monitor having a first input, a second input and an output, the first input of the frequency divider monitor connected to the output of the voltage controlled oscillator and the second input of the frequency divider monitor coupled to an output of the feedback frequency divider; measuring a frequency ratio of a frequency of a signal on the output of the voltage controlled oscillator and of a frequency of a signal on the output of the feedback frequency divider; and generating a alert signal in response to the frequency ratio falling outside an upper or a lower limit around a specified value of the frequency ratio.

The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is block circuit diagram of a first frequency generator and monitor circuit according to a first embodiment of the present invention;

FIG. 2 is block circuit diagram of a second frequency generator and monitor circuit according to a second embodiment of the present invention;

FIG. 3 is block circuit diagram of a third frequency generator and monitor circuit according to a third embodiment of the present invention;

FIG. 4 is a timing diagram of various signals of the circuits of FIGS. 1 , 2 and 3 ;

FIG. 5 is a circuit diagram of a first type of programmable period to voltage converter of FIGS. 1 , 2 and 3 ;

FIG. 6 is a circuit diagram of a second type of programmable period to voltage converter of FIGS. 1 , 2 and 3 ;

FIG. 7 is a circuit diagram of a third type of programmable period to voltage converter of FIGS. 1 , 2 and 3 ;

FIG. 8 is a additional timing diagram of various signals of the circuits of FIGS. 1 , 2 and 3 ;

FIG. 9 is a circuit diagram a first type of error amplifier circuit of FIGS. 1 , 2 and 3 ;

FIG. 10 is a circuit diagram of a second type of error amplifier circuit of FIGS. 1 , 2 and 3 ;

FIG. 11 is a circuit diagram a comparator of FIGS. 1 , 2 and 3 ;

FIG. 12 is a circuit diagram a logic unit of FIGS. 1 , 2 and 3 ;

FIG. 13 illustrates a block diagram of a general-purpose computer system which can be used to implement the circuit and circuit design structure described herein; and

FIG. 14 shows a block diagram of an example design flow process for designing the circuit design structure described herein.

An external frequency divider is defined as a frequency divider not physically present on the integrated circuit chip containing the phase lock loop, but it is a part of the feedback frequency divider.

A clock signal is defined as a signal having a regular repeating pattern of a time period of high voltage and a time period of low voltage. The duty cycle of a clock signal is the time duration of a high period divided by the time period of the clock signal. The voltage level of the low periods is often denoted as a “0” and the voltage level of the high periods is often denoted as “1.” Hereinafter, the signals denoted as f IN , f VCOO , f B , f OUT and f EXT are clock signals.

A frequency divider is a circuit that generates an output signal having a frequency that is less than the frequency of the input signal. The divide ratio of a frequency divider is defined as the frequency of the output signal divided by the frequency of the input signal and is never greater than 1. For example, a divide by 3 frequency divider has a output frequency that is ⅓ that of the input frequency. It is common for the divide ratio to be expressed as a ratio of positive whole numbers greater than zero.

The term identically designed is defined to mean devices (e.g. capacitors, transistors, diodes, resistors, current sources) or circuits that are intended to be as close to identical when fabricated as permitted by the fabrication process used to fabricate the devices or circuits.

FIG. 1 is the block circuit diagram of a first frequency generator and monitor circuit 100 A according to a first embodiment of the present invention. In FIG. 1 , frequency generator and monitor circuit 100 A includes a phase locked loop circuit which includes a phase detector 105 , a charge pump 110 , a voltage controlled oscillator 115 which generates a clock signal f VCOO , a forward frequency divider 120 (which is optional) which generates a clock signal f OUT and a feedback frequency divider 125 which generates a clock signal f B .

A first input of phase detector 105 is connected to clock signal f IN and a second input of the phase detector is connected to an output (f B ) of feedback frequency divider 125 . An output of phase detector 105 is connected to an input of charge pump 110 . An output of charge pump 110 is connected to and input of voltage controlled oscillator 115 . An output (f VCOO ) of voltage controlled oscillator 115 is connected to an input of forward frequency divider 120 and an input of feedback frequency divider 125 .

Frequency generator and monitor circuit 100 A also includes a frequency divider monitor 130 . Frequency divider monitor 130 includes a first period generator 135 A which generates a tg 1 o signal and a second period generator 135 B which generates a tg 2 o signal, a first period to voltage converter 145 A which generates a ptv 1 o from the tg 1 o signal and a plurality of bn/dj bit inputs and a second period to voltage converter 145 B which generates a ptv 2 o from the tg 2 o signal and the plurality of bn/dj bit inputs, a decoder 150 which generate bd/djA and bd/djB bits from a bit control signal, an error amplifier 155 , a comparator 160 having a plurality of threshold voltage inputs Vthn, and a logic unit 165 generating alert signals WARN and ALARM.

Alternatively, first and second period to voltage converters 145 A and 145 B may be designed for specific R ratios (see equation 1) and decoder 150 eliminated.

An input of first period generator 135 A is connected to the output (f VCOO ) of voltage controlled oscillator 115 . An input of second period generator 135 B is connected to the output (f B ) of feedback frequency divider 125 . An input of first period to voltage converter 145 A is connected to the output (tg 1 o ) of first period generator 135 A. An input of second period to voltage converter 145 B is connected to the output (tg 2 o ) of second period generator 135 B. First and second period generators 135 A and 135 B are identically designed. First and second period to voltage converters 145 A and 145 B are identically designed. Bits bn/djA and bn/djB are supplied to first and second period to voltage converters 145 A and 145 B respectively.

The operation of frequency divider monitor 130 is based on the fact that the ratio (R) of the frequency of the output signal (f VCOO ) of voltage controlled oscillator and the frequency of the output signal (f B ) of feedback frequency divider 125 is designed to be a constant and preset value as expressed by:

f VCOO /f B =R   (1)

Frequency divider monitor 130 measures f VCOO /f B in real time and when f VCOO /f B exceeds limits set on R (i.e. exceeds R+HL or R−LL where HL is the maximum increase in R allowed and LL is the maximum decrease in R allowed). A warning signal (WARN) or an alarm signal (ALARM) is generated when the limits on R are exceeded.

In FIG. 1 , the value R includes only the divide ratio of feedback frequency divider 125 . So the only frequency divider monitored by frequency divider monitor 130 is feedback frequency divider 125 .

FIG. 2 is block circuit diagram of a second frequency generator and monitor circuit 110 B according to a second embodiment of the present invention. Frequency generator and monitor circuit 110 B is similar to frequency generator and monitor circuit 110 A (see FIG. 1 ) except the input of feedback frequency divider 125 is connected to the output of forward frequency divider 120 instead of the output of voltage controlled oscillator 115 (see FIG. 1 ).

Operation of frequency generator and monitor circuit 110 B is similar to the operation of frequency generator and monitor circuit 110 A (see FIG. 1 ), but because the output (f VCOO ) of forward frequency divider 120 is presented to the input of feedback frequency divider 125 , the value R includes the divide ratio of forward frequency divider 120 and the divide ratio of feedback frequency divider 125 . So both forward frequency divider 120 and feedback frequency divider 125 are monitored by frequency divider monitor 130 .

FIG. 3 is block circuit diagram of a third frequency generator and monitor circuit 110 C according to a third embodiment of the present invention. Frequency generator and monitor circuit 110 C is similar to frequency generator and monitor circuit 110 B (see FIG. 2 ) except the input of feedback frequency divider 125 is connected to the output of external frequency divider 170 instead of to the output of forward frequency divider 120 (see FIG. 2 ) and the input of external frequency divider 170 is connected to the output of forward frequency divider 120 .

Operation of frequency generator and monitor circuit 110 B is similar to the operation of frequency generator and monitor circuit 110 B (see FIG. 2 ), but because the output (f VCOO ) of forward frequency divider 120 is presented to the input of forward frequency divider 120 , the output (f OUT ) of forward frequency 120 is presented to the input of external frequency divider 170 and the output (f EXT ) of external frequency divider 170 is presented to the input of feedback frequency divider 125 , the value R includes the divide ratio of forward frequency divider 120 , the divide ratio of feedback frequency divider 125 and the divide ratio of external frequency divider 170 . So forward frequency divider 120 , feedback frequency divider 125 and external frequency divider 170 are monitored by frequency divider monitor 130 .

Referring to FIGS. 1 , 2 and 3 , first and second period generators 135 A and 135 B are one bit counters so that the half period of the generator output is the period of the input regardless the duty cycle of the input. The counter can be rising edge trigged or falling edge trigged. This is illustrated in FIG. 4 .

FIG. 4 is a timing diagram of various signals of the circuits of FIGS. 1 , 2 and 3 . In FIG. 4 , the input (f VCOO ) to first period generator 135 A (see FIG. 1 ) has an exemplary duty cycle of 50% and the half period of the output (tg 1 o ) of first period generator 135 A is equal to a period of f VCOO . The input (f B ) to second period generator 135 B (see FIG. 1 ) has an exemplary duty cycle of 12.5% and the half period of the output (tg 2 o ) of second period generator 135 A is equal to a period of f B . In FIG. 4 , feedback frequency generator 125 (see FIG. 3 ) is an exemplary divide by four (has divide ratio of 1/4) frequency divider. The period of tg 2 o is four times the period of tg 1 o . In general, since frequency dividers can only divide down the input frequency (a divide by 1 or divide by less than 1 frequency divider, by definition can not exist), f VCOO is equal to or higher than f B and the period of f VCOO is always equal to or shorter than that of f B .

FIG. 5 is a circuit diagram of a first type of programmable period to voltage converter of FIGS. 1 , 2 and 3 . In FIG. 5 , programmable period to voltage converter 145 A/ 145 B includes a current mirror having a primary side and a secondary side including a set of programmable current fingers. Current source I 0 and PFET P 0 form the primary side of the current mirror. PFETs P 1 to Pn, P 1 - 1 to Pn- 1 and NFETs N 1 to Nn form the programmable current fingers of the secondary side of the current mirror. Each programmable current finger is identically designed. Each programmable current finger is connected to a corresponding control bit b 1 to bn. When a control bit bk (k=1, 2, . . . n) is at logic high, PFET Pk- 1 is turned off, NFET Nk is turned on and the PFET Pk is turned on and has contribution of current I 0 to the total current of Is. When tg 1 o /tg 2 o is at logic low, PFET Pm is turned on, NFET Nm is turned off, capacitor C (includes the parasitic capacitance on the ptv 1 o /ptv 2 o ) is charged through PFET Pm by the current Is. The maximum voltage across capacitor C, VCmax, is given by:

where I 0 is the current level supplied by current source I 0 , Nif is the number of the programmable current fingers turned on, T is the period time of logic low of tg 1 o /tg 2 o and C is the total capacitance on ptv 1 o /ptv 2 o . When tg 1 o /tg 2 o is at logic high, PFET Pm is turned off and NFET Nm is turned on, capacitor C is discharged. Since the discharge current of capacitor C is much larger than the charge current I 0 so the voltage level on ptv 1 o /ptv 2 o drops to zero very fast.

Returning to FIGS. 1 , 2 and 3 , the frequency ratio R, see equation (1) supra, and the period ratio is 1/R. R programmable current fingers are turned on in programmable period to voltage converter 145 A while one programmable current finger is turned on in programmable period to voltage converter 145 B. More generally,

where NifA is the number of the programmable current fingers turned on in programmable period to voltage converter 145 A and NifB is the number of the programmable current fingers turned on in programmable period to voltage converter 145 B. The VCmax of each of programmable period to voltage converters 145 A and 145 B is the same.

FIG. 6 is a circuit diagram of a second type of programmable period to voltage converter of FIGS. 1 , 2 and 3 . In FIG. 6 , programmable period to voltage converter 145 A/ 45 B includes a current mirror having a primary side and a secondary side including a set of programmable capacitor fingers. Current source I 0 and PFET P 0 form the primary side of the current mirror. PFET P 1 is the secondary side of the current mirror. NFETs N 1 - 1 to Nj- 1 , NFETs N 1 - 2 to Nj- 2 and capacitors C 1 to Cj form the programmable capacitor fingers. Each programmable capacitor finger is identically designed. Each programmable capacitor finger is connected to a corresponding control bit d 1 to dj. When the control bit dk(k=1, 2, j) is at logic high, the finger is selected, when dk is at logic low, the finger is disabled. When tg 1 o /tg 2 o is at logic low, PFET Pm is turned on, NFET Nk- 1 is turned off and capacitor Ck is charged through PFET Pm by the current I 0 . The maximum voltage VCmax across the capacitors of all turned on programmable capacitor fingers is given by:

where I 0 is the current level supplied by current source I 0 , T is the period time of logic low of tg 1 o /tg 2 o , C is the capacitance value the capacitor of each finger and Ncf is the number of programmable capacitor fingers turned on. When tg 1 o /tg 2 o is at logic high, PFET Pm is turned off and NFET Nk- 1 (k=1, 2, . . . j) is turned on, the capacitor Ck is discharged. Since the discharge current of C*Ncf is much larger than the charge current I 0 , the voltage level on ptv 1 o /ptv 2 o drops to zero very fast.

Returning to FIGS. 1 , 2 and 3 , the frequency ratio R, see equation (1) supra, and the period ratio is 1/R. R programmable capacitor fingers are turned on in programmable period to voltage converter 145 B while one programmable capacitor finger is turned on in programmable period to voltage converter 145 A. More generally,

where NcfA is the number of the programmable capacitor fingers turned on in programmable period to voltage converter 145 A and NcfB is the number of the programmable capacitor fingers turned on in programmable period to voltage converter 145 B. The VCmax of each of programmable period to voltage converters 145 A and 145 B is the same.

FIG. 7 is a circuit diagram of a third type of programmable period to voltage converter of FIGS. 1 , 2 and 3 . Programmable period to voltage converter 145 A/ 145 B of FIG. 7 is a combination of programmable period to voltage converters 145 A/ 145 B of FIG. 5 and of FIG. 6 and operates similarly. In FIG. 7 , programmable period to voltage converter 145 A/ 145 B includes a current mirror having a primary side and a secondary side. The secondary side has a first section including a set of programmable current fingers and a second section including a set of programmable capacitor fingers. Current source I 0 and PFET P 0 form the primary side of the current mirror. PFETs P 1 to Pn, P 1 - 1 to Pn- 1 . NFETs N 1 to Nn form the programmable current fingers of the first section of the secondary side of the current mirror. Each programmable current finger of the first section is identically designed. Each programmable current finger of the first section is connected to a corresponding control bit b 1 to bn. NFETs N 1 - 1 to Nj- 1 , NFETs N 1 - 2 to Nj- 2 and capacitors C 1 to Cj form the programmable capacitor fingers of the second section of the secondary side of the current mirror. Each programmable capacitor finger of the second section is identically designed. Each programmable capacitor finger of the second section is connected to a corresponding control bit d 1 to dj. The maximum voltage VCmax across the capacitors of all turned on programmable capacitor fingers is given by:

where I 0 is the current level supplied by current source I 0 , Nif is the number of the programmable current fingers turned on, T is the period time of logic low of tg 1 o /tg 2 o , C is the capacitance value a capacitor of a programmable capacitor finger and Ncf is the number of programmable capacitor fingers turned on.

Returning to FIGS. 1 , 2 and 3 , the frequency ratio R, see equation (1) supra, and the period ratio is 1/R. R programmable fingers are turned on in programmable period to voltage converter 145 A while one current finger is turned on in programmable period to voltage converter 145 B. More generally,

where NcfA is the number of the programmable capacitor fingers turned on in programmable period to voltage converter 145 A, NcfB is the number of the programmable capacitor fingers turned on in programmable period to voltage converter 145 B, NifA is the number of the programmable current fingers turned on in programmable period to voltage converter 145 A and NcfB is the number of the programmable current fingers turned on in programmable period to voltage converter 145 B. The VCmax of each of programmable period to voltage converters 145 A and 145 B is the same.

Decoder 150 (see FIG. 1 ) is a logic circuit that sets the bit values b 1 through bn (0 or 1) and d 1 through dj (0 or 1) using a Bit Control signal based on the frequency divider ratios of each frequency divider in the clock paths, feedback frequency divider 125 in FIG. 1 , forward frequency divider 120 and feedback frequency divider 125 in FIG. 2 and forward frequency divider 120 , feedback frequency divider 125 and external frequency divider 170 in FIG. 3 .

FIG. 8 is an additional timing diagram of various signals of the circuits of FIGS. 1 , 2 and 3 . In FIG. 8 waveforms for ptv 1 o and ptv 2 o have been added to those previously shown in FIG. 4 and described supra. When equation (3) or (5) or (7) (depending on the type of programmable period to voltage converter used) is met, the maximum voltage of ptv 1 o is equal to the maximum voltage of ptv 2 o and the average voltage of ptv 1 o is equal to the average voltage of ptv 2 o the same period of time. For example, in FIG. 8 , the areas a 1 +a 2 +a 3 +a 4 equal the area b. However, when equation (3) or (5) or (7) is not met, then VCmax of ptv 1 o and ptv 2 o is not the same, the areas a 1 +a 2 +a 3 +a 4 are not equal to area b, and a probable malfunction of a frequency divider has occurred.

The function of error amplifier 155 (see FIG. 1 ) is to magnify the voltage difference of signals ptv 1 o and ptv 2 o described supra. There are two types of amplifiers that may be used for error amplifier 155 , a peak voltage operational amplifier illustrated in FIG. 9 and an average voltage operational amplifier illustrated in FIG. 10 .

FIG. 9 is a circuit diagram a first type of error amplifier circuit of FIGS. 1 , 2 and 3 . In FIG. 9 , an exemplary error amplifier 155 includes operational amplifiers A 1 , A 2 , A 3 , A 4 and A 5 , diodes D 1 and D 2 , capacitors C 1 , C 2 and C 3 and resistors R 1 - 1 , R 1 - 2 , R 1 - 3 , R 2 - 1 , R 2 - 2 and R 2 - 3 . Operational amplifier A 1 , diode D 1 and capacitor C 1 form a first peak detector for ptv 1 o . Operational amplifier A 2 , diode D 2 and capacitor C 2 form a second peak detector for ptv 2 o . Amplifiers A 3 and A 4 are high input impedance voltage followers. Resistors R 1 - 1 and R 2 - 1 are leakage resistors which provide a small leakage from the capacitors C 1 and C 2 respectively so that the outputs of the peak detectors are a little bit lower than the peak voltages (quasi peak) and work to dynamically update the peak voltages detected. Resistor R 1 - 1 and R 2 - 1 can be resistors with large resistance or small sink-current current sources. The operational amplifier A 5 , and resistors R 1 - 2 , R 1 - 3 , R 2 - 2 and R 2 - 3 form a difference amplifier whose output (ERR) is the difference of the two peak voltages detected. Capacitor C 3 is used to filter out the voltage ripple of the quasi detectors.

FIG. 10 is a circuit diagram of a second type of error amplifier circuit of FIGS. 1 , 2 and 3 . In FIG. 10 , an exemplary error amplifier 155 includes operational amplifier A 5 , capacitor C 3 and resistors R 1 - 2 , R 1 - 3 , R 2 - 2 and R 2 - 3 . The operational amplifier A 5 with large capacitance C 3 has much lower forward operating frequency (positive input of A 5 to ERR) than a feedback frequency (ERR to the negative input of A 5 ) so that the output (ERR) of operational amplifier A 5 is proportional to the average of the voltage difference between ptv 1 o and ptv 2 o.

FIG. 11 is a circuit diagram the comparator 160 of FIGS. 1 , 2 and 3 . In FIG. 11 , comparator 160 includes four voltage comparators VC 1 , VC 2 , VC 3 and VC 4 having corresponding negative inputs Vth 1 , Vth 2 , Vth 3 and Vth 4 for settable threshold voltages having the relationship Vth 3 >Vth 1 >Vth 2 >Vth 4 , and corresponding outputs Vout 1 , Vout 2 , Vout 3 and Vout 4 . ERR is connected to the positive inputs of each of voltage comparators VC 1 , VC 2 , VC 3 and VC 4 .

FIG. 12 is a circuit diagram logic unit 165 of FIGS. 1 , 2 and 3 . In FIG. 12 , logic unit comprises XNOR gate X 1 and XNOR gate X 2 . The inputs to XNOR gate X 1 are Vout 1 and Vout 2 . The inputs to XNOR gate X 2 are Vout 3 and Vout 3 . The output of XNOR gate X 1 is warning signal WARN. The output of XNOR gate X 2 is alarm signal ALARM. When Vout 1 and Vout 2 are the same logic level, WARN goes high. When Vout 3 and Vout 4 are the same logic level, ALARM goes high.

The threshold voltages Vth 1 , Vth 2 , Vth 3 and Vth 4 are selected to provide the following function when comparator 160 is connected to logic circuit 165 .

(1) When ERR is lower than Vth 1 and higher than Vth 2 , it is normal. (2) When ERR is higher than Vth 1 or lower than Vth 2 , a pre warning signal is sent out. (3) When ERR is higher than Vth 3 or lower than Vth 4 , a alarm signal is sent out. This is detailed in Truth Table I:

Referring to FIG. 1 , a variation of the first embodiment of the present invention may be used to monitor the duty cycle of feedback frequency divider 125 . If the duty cycle of feedback frequency divider 125 is to be monitored, period generators 135 A and 135 B are omitted and the output (f VCOO ) of voltage controlled oscillator 115 is connected to the input of first period to voltage converter 145 A and the output (f B ) of feedback frequency divider 125 is connected to the input of second period to voltage converter 145 B. The operation of now modified frequency generator and monitor circuit 100 A is similar to that of unmodified frequency generator and monitor circuit 100 A.

FIG. 13 illustrates a block diagram of a general-purpose computer system which can be used to implement the circuit and circuit design structure described herein. The design structure may be coded as a set of instructions on removable or hard media for use by general-purpose computer. FIG. 13 is a schematic block diagram of a general-purpose computer for practicing the present invention. FIG. 13 shows a computer system 1300 , which has at least one microprocessor or central processing unit (CPU) 1305 . CPU 1305 is interconnected via a system bus 1320 to machine readable media 1375 , which includes, for example, a random access memory (RAM) 1310 , a read-only memory (ROM) 1315 , a removable and/or program storage device 1355 and a mass data and/or program storage device 1350 . An input/output (I/O) adapter 1330 connects mass storage device 1350 and removable storage device 1355 to system bus 1320 . A user interface 1335 connects a keyboard 1365 and a mouse 1360 to system bus 1320 , and a port adapter 1325 connects a data port 1345 to system bus 1320 and a display adapter 1340 connect a display device 1370 . ROM 1315 contains the basic operating system for computer system 1300 . Examples of removable data and/or program storage device 1355 include magnetic media such as floppy drives, tape drives, portable flash drives, zip drives, and optical media such as CD ROM or DVD drives. Examples of mass data and/or program storage device 1350 include hard disk drives and non-volatile memory such as flash memory. In addition to keyboard 1365 and mouse 1360 , other user input devices such as trackballs, writing tablets, pressure pads, microphones, light pens and position-sensing screen displays may be connected to user interface 1335 . Examples of display device 1370 include cathode-ray tubes (CRT) and liquid crystal displays (LCD).

A machine readable computer program may be created by one of skill in the art and stored in computer system 1300 or a data and/or any one or more of machine readable medium 1375 to simplify the practicing of this invention. In operation, information for the computer program created to run the present invention is loaded on the appropriate removable data and/or program storage device 1355 , fed through data port 1345 or entered using keyboard 1365 . A user controls the program by manipulating functions performed by the computer program and providing other data inputs via any of the above mentioned data input means. Display device 1370 provides a means for the user to accurately control the computer program and perform the desired tasks described herein.

FIG. 14 shows a block diagram of an example design flow 1400 . Design flow 1400 may vary depending on the type of IC being designed. For example, a design flow 1400 for building an application specific IC (ASIC) will differ from a design flow 1400 for designing a standard component. Design structure 1420 is an input to a design process 1410 and may come from an IP provider, a core developer, or other design company. Design structure 1420 comprises at least one of circuits 100 in the form of schematics or HDL, a hardware-description language, (e.g., Verilog, VHDL, C, etc.). Design structure 1420 may be on one or more of machine readable medium 1375 as shown in FIG. 13 . For example, design structure 1420 may be a text file or a graphical representation of circuit 100 A. Design process 1410 synthesizes (or translates) at least one of circuits 100 into a netlist 1480 , where netlist 1480 is, for example, a list of fat wires, transistors, logic gates, control circuits, I/O, models, etc. and describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium 1375 .

Design process 1410 includes using a variety of inputs; for example, inputs from library elements 1430 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g. different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 1440 , characterization data 1450 , verification data 1460 , design rules 1470 , and test data files 1485 , which may include test patterns and other testing information. Design process 1410 further includes, for example, standard circuit design processes such as timing analysis, verification tools, design rule checkers, place and route tools, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process 1410 without deviating from the scope and spirit of the invention.

Ultimately design process 1410 translates at least one of circuits 100 , along with the rest of the integrated circuit design (if applicable), into a final design structure 1490 (e.g., information stored in a GDS storage medium). Final design structure 1490 may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, test data, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce at least one of circuits 100 . Final design structure 1490 may then proceed to a stage 1495 of design flow 1400 ; where stage 1495 is, for example, where final design structure 1490 : proceeds to tape-out, is released to manufacturing, is sent to another design house or is sent back to the customer.

Thus, the embodiments of the present invention provide design structures comprising circuits for monitoring operation of the frequency dividers integrated circuits and electronic systems.

The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.