High-gain multicolor pixel sensor with reset noise cancellation

1. Field of the Invention

The present invention relates to CMOS pixel sensors and to multicolor CMOS pixel sensors. More particularly, the present invention relates to a high-gain multicolor pixel sensor having reset noise cancellation.

2. The Prior Art

CMOS pixel sensors have become more prevalent in the art. Such pixel sensors typically employ a photodiode to collect charge and a select transistor and source-follower amplifier to read the charge out of the pixel sensor.

Multicolor versions of these pixel sensors are also known. Early examples of such sensors used an array of detectors formed in a pattern such as a Bayer pattern. Recently, vertical-color-filter CMOS pixel sensors have been disclosed, in which multiple pixel sensors (such as blue, green, and red) are positioned at different depths in a semiconductor body to take advantage of the fact that the penetration depth is a function of photon energy. Contact to the detectors disposed beneath the surface of the silicon body is made through deep contact structures.

According to one aspect of the present invention, an active CMOS pixel sensor comprises a red photodiode, a green photodiode and a plurality of blue photodiodes. Each of the blue photodiodes coupled to a blue sense node through a different n-channel MOS blue-select transistor through a different blue-select line. An n-channel MOS blue reset transistor has a drain coupled to a supply node, a source coupled to the blue sense node, and a gate coupled to a reset control line. An n-channel MOS blue source-follower transistor has a gate coupled to the blue sense node, a drain coupled to a blue source-follower supply node, and a source. A blue row-select transistor has a drain coupled to the source of the blue source-follower transistor, a source coupled to a blue column output line and a gate coupled to a blue row-select line. A MOS capacitor is coupled to the blue sense node through a capacitor-select transistor having a gate coupled to a capacitor select line. The red photodiode is coupled to a red sense node. An n-channel MOS red amplifier transistor has a gate coupled to the red sense node, a drain, and a source. A p-channel MOS red amplifier transistor has a source coupled to a supply node, a drain coupled to the drain of the n-channel MOS red amplifier transistor, and a gate coupled to a reset1 control line. A n-channel MOS red reset transistor has a drain coupled to the drain of the n-channel MOS red reset transistor, a source coupled to the red sense node, and a gate coupled to a reset2 control line. A red feedback capacitor is coupled between the red sense node and the drain of the n-channel MOS red reset transistor. A red row-select transistor has a drain coupled to the source of the n-channel MOS red amplifier transistor, a source coupled to a red column output line and a gate coupled to a red-green row-select line. The green photodiode is coupled to a green sense node. An n-channel MOS green amplifier transistor has a gate coupled to the green sense node, a drain, and a source. A p-channel MOS green amplifier transistor has a source coupled to a supply node, a drain coupled to the drain of the n-channel MOS green amplifier transistor, and a gate coupled to the reset1 control line. A n-channel MOS green reset transistor has a drain coupled to the drain of the n-channel MOS green reset transistor, a source coupled to the green sense node, and a gate coupled to the reset2 control line. A green feedback capacitor is coupled between the green sense node and the drain of the n-channel MOS green reset transistor. A green row-select transistor has a drain coupled to the source of the n-channel MOS green amplifier transistor, a source coupled to a green column output line and a gate coupled to the red-green row-select line. The blue, red, and green column output lines are each coupled, respectively, to a blue, red, and green column-line bias transistor. The gate of the blue column-line bias transistor is coupled to a blue column line bias control line. The gates of the red and green column-line bias transistor are coupled to a R/G column line bias control line.

FIG. 1 is a schematic diagram of an illustrative multicolor CMOS active pixel sensor according to one aspect of the present invention.

FIG. 2 is a timing diagram that illustrates one method for operating the pixel sensor of FIG. 1 .

FIG. 3 is a timing diagram that illustrates another method for operating the pixel sensor of FIG. 1 .

Persons of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.

Referring now to FIG. 1 , a schematic diagram providing an example of such a pixel sensor 10 is shown. Pixel sensor 10 is configured so that the entire array can be reset at once. A pixel sensor of this type is usefully employed in an SLR-shutter type of pixel sensor array.

A red photodiode 12 r is coupled to a sense node 14 r comprising the gate of n-channel MOS amplifier transistor 16 r . The source of n-channel MOS amplifier transistor 16 r is coupled to the drain of an n-channel MOS row-select transistor 18 r . The gate of n-channel MOS red row-select transistor 18 r is coupled to R/G row-select line 20 . The source of n-channel MOS red row-select transistor 18 r is coupled to column output line 22 r.

The drain of n-channel MOS amplifier transistor 16 r is coupled to the drain of p-channel MOS amplifier transistor 24 r . The source of p-channel MOS amplifier transistor 24 r is coupled to supply potential V pix — red . The gate of p-channel MOS amplifier transistor 24 r is coupled to a reset1 line 26 .

An n-channel MOS reset transistor 28 r is coupled between the gate of n-channel MOS amplifier transistor 16 r and the common connection of the drain of p-channel MOS amplifier transistor 24 r and the drain of n-channel MOS amplifier transistor 16 r . The gate of n-channel MOS reset transistor 28 r is coupled to a reset2 line 30 . A capacitor 32 r is coupled between the red sense node 14 r and the common connection of the drain of n-channel MOS amplifier transistor 16 r and the drain of p-channel MOS amplifier transistor 24 r.

Similarly, a green photodiode 12 g is coupled to a green sense node 14 g comprising the gate of n-channel MOS amplifier transistor 16 g . The source of n-channel MOS amplifier transistor 16 g is coupled to the drain of an n-channel MOS row-select transistor 18 g . The gate of n-channel MOS red row-select transistor 18 g is coupled to R/G row-select line 20 . The source of n-channel MOS red row-select transistor 78 g is coupled to a column output line 22 g.

The drain of n-channel MOS amplifier transistor 16 g is coupled to the drain of p-channel MOS amplifier transistor 24 g . The source of p-channel MOS amplifier transistor 84 g is coupled to supply potential V pix — green . The gate of p-channel MOS amplifier transistor 24 g is coupled to reset1 line 26 .

An n-channel MOS reset transistor 28 g is coupled between the gate of n-channel MOS amplifier transistor 16 g and the common connection of the drain of p-channel MOS amplifier transistor 24 g and the drain of n-channel MOS amplifier transistor 16 g . The gate of n-channel MOS reset transistor 28 g is coupled to reset2 line 30 . A capacitor 32 g is coupled between the sense node 14 g and the common connection of the drain of n-channel MOS amplifier transistor 16 g and the drain of p-channel MOS amplifier transistor 84 g.

Blue photodiodes 34 , 36 , 38 , and 40 are coupled to a blue sense node 42 through blue-select transistors 50 , 48 , 46 , and 44 , respectively. The gate of blue-select transistor 44 is coupled to a blue1 select line 52 ; the gate of blue-select transistor 106 is coupled to a blue1 select line 114 ; the gate of blue-select transistor 48 is coupled to a blue1 select line 56 ; and the gate of blue-select transistor 40 is coupled to a blue1 select line 58 .

N-channel MOS amplifier transistor 60 has its gate coupled to blue sense node 42 . The drain of n-channel MOS amplifier transistor 60 is coupled to supply potential V sfd — blue . The source of n-channel MOS amplifier transistor 60 is coupled to the drain of n-channel MOS blue row select transistor 62 . The source of n-channel MOS blue row select transistor 62 is coupled to column output line 22 b . The gate of n-channel MOS blue row select transistor 62 is coupled to blue row select line 64 .

N-channel MOS reset transistor 66 has its source coupled to blue sense node 42 and its drain coupled to supply potential V pix — blue . Its gate is coupled to reset_blue line 68 . Blue sense node 42 is also coupled to MOS capacitor 70 through n-channel MOS capacitor transistor 72 . The gate of n-channel MOS capacitor transistor 72 is coupled to capacitor line 74 .

The red, green, and blue column output lines 22 r , 22 g , and 82 b are each coupled to the drain of a respective n-channel MOS column output load transistor 76 r , 76 g , and 76 b . The gates of n-channel MOS column output load transistors 76 r and 76 g , are coupled together to a column_bias line R/G 78 . The gate of n-channel MOS column output load transistor 76 b is coupled to a column_bias line BL 80 . The sources of n-channel MOS column output load transistors 76 r , 76 g , and 76 b are coupled together to ground.

Referring now to FIG. 2 , a timing diagram illustrates a method of operating the pixel sensor 10 of FIG. 1 . First, the signal reset 2 is asserted. Then the n-channel MOS column output load transistors 76 r , 76 g , and 76 b are turned on. The red and green row-select signals are asserted. The reset1 line is biased to a voltage level just slightly higher than the V t of the p-channel MOS amplifier transistors 24 r and 24 g to just barely turn them on. At this point in time, transistor pairs 16 r and 84 r and 16 g and 24 g each form an amplifier. The reset2 signal is ramped down and negative feedback through capacitors 32 r and 32 g act to cancel any reset noise in the amplifiers.

Next, photocharge is integrated on the red, green, and blue photodiodes. The signal reset 1 is turned on hard to place the potential V pix at the drains of transistors 16 r and 16 g to cause them to operate as source-follower amplifiers. The red, green, and blue row select transistors are turned on and the red, green and blue bias transistors are tuned on as current source loads.

According to one aspect of the present invention, depicted in FIG. 2 , the four blue signals are read out individually. The blue row select transistor is turned on and the blue column line bias transistor is turned on to provide a bias level and the blue1, blue2, blue3, and blue4 signals are individually asserted. The reset_blue signal is asserted in between each of the blue1, blue2, blue3, and blue4 signals in order to clear the previous signal from the common node.

As shown in FIG. 2 , the red and green channels may also be read prior to the start of photointegration to generate a red dark and a green dark signal. The red dark signal and the green dark signal may then be subtracted from the red and green signals that are read after photo integration in order to cancel any effects due to the variation in the reset levels of the red and green channels.

According to another aspect of the present invention depicted in FIG. 3 , the pixel sensor is operated in a mode in which the four blue signals are read out simultaneously. In this mode, the signal “cap” is asserted on line 74 to add the capacitance of MOS capacitor 70 to the capacitance of sense node 42 in order to prevent the combined blue signals from overwhelming the capacitance of the blue sense node 42 . As shown in FIG. 3 , “dark” readings may also be taken in the red and green channels to compensate for the variation in the reset levels of the red and green channels.

While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.