Moment-based method and system for evaluation of metal layer transient currents in an integrated circuit

1. Technical Field

The present invention relates generally to circuit design and evaluation software, and more particularly, to a methodology and computer program that uses circuit moments to compute currents in a metal layer of an integrated circuit.

2. Description of the Related Art

Metal layer currents or “wire currents” in an integrated circuit must typically be evaluated for each design for a number of reasons. The metal layer interconnects must be properly sized to handle both peak current levels and power dissipation due to ohmic losses. Further, as design technology is scaled to decrease the circuit area, current densities in the interconnects increase, dramatically increasing problems due to electromigration. Electromigration causes movement of metal ions in the metal layer, deforming the conductors over time and potentially causing circuit failure. Voids formed in the conductors cause increased resistance and open circuits, and in particular, the reduced cross-section further increases current density and ohmic heating. Migration of the conductors toward other conductors can cause short circuits between conductors, and consequent failure of the integrated circuit. Both the peak and average values of current through a conductor are important factors in analysis of electromigration effects, and present reliability models typically require computation of the peak, root-mean-square (rms) and average current values for each conductor.

Complete determination of all currents in all interconnects in an integrated circuit is possible by simulating the circuit using a simulation program such as SPICE, but is time-consuming and requires an extensive amount of computing resources. Other techniques approximate the currents from timing models as triangular waveforms at each transient switching event and/or attempt to prune the set of interconnects for which currents are calculated, by selecting which interconnects are most likely to fail. However, for an analysis of potential electromigration failures and reliability values (mean time to failure), a full simulation is typically required. The timing model analyses will typically under or over-predict peak current values, depending on whether a conservative model is used. Pruning of the set of interconnects may miss conductors that have a high current stress vs. size and/or spacing.

It is therefore desirable to provide a method and system for accurately determining peak, average and rms current levels for all interconnects in metal layers of an integrated circuit without excessive computational burden.

The objective of accurately determining peak, average and rms current levels for all interconnects in metal layers of an integrated circuit is provided in a method, a computer system carrying out steps of the method, and a computer program product for carrying out the steps of the method on a computer system.

The method computes current moments representing coefficients of powers-of-s in a Laplacian representation of the interconnect current at each segment node in the model of the interconnect, which may be a resistor-capacitor (RC) tree model. The current moments are obtained from expressions in terms of the overlap resistance in the unique paths from the source node to each segment mode and differences from circuit moments for the nodes for a particular voltage waveform model, such as a source-saturated ramp applied to an end of the interconnect. The circuit moments can either be computed on-the-fly, or obtained from a previous interconnect delay analysis. The average current is then calculated from the lowest-order current moment and the rms and peak currents are calculated from closed-form expressions in terms of the current moments that are based on a distribution function current waveshape assumption, such as a lognormal distribution shape. The resulting values can be used in subsequent reliability analysis of the interconnect, which can then be combined to determine a reliability factor for the metal layer and/or can be used to inform design changes to interconnects having low reliability.

The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein like reference numerals indicate like components, and:

FIG. 1 is a circuit diagram illustrating a circuit model as used in a method in accordance with an embodiment of the invention.

FIGS. 2A-2B and FIGS. 3A-3B are graphs depicting results of computations by modeling methods in accordance with embodiments of the present invention.

FIG. 4 is a flowchart depicting a method in accordance with an embodiment of the present invention.

FIG. 5 is a block diagram depicting a computer system in which a method in accordance with an embodiment of the present invention is performed.

The present invention concerns a technique for modeling transient current magnitudes, including peak, average and rms current values, within a metal layer of an integrated circuit. The results can be used in determining reliability of the integrated circuit metal layer, in particular, an evaluation of the reliability of the integrated circuit with respect to the effects of electromigration. The method, which is embodied in a computer system executing program instructions that carry out the method, may also be embodied in a computer program product, such as an optical disk containing the program instructions for loading into the computer's program memory.

Referring now to FIG. 1 , a circuit model implemented by a computer-performed method in accordance with an embodiment of the invention is shown. The input to the depicted network is represented by a voltage source v in (t) and the interconnect is modeled as a set of resistors R ik between nodes representing endpoints of segments of the interconnect and shunt capacitances, e.g., C i , C k at corresponding nodes node i, node k. The model is an AC model, and there is no DC current leakage path. Moment modeling for transient voltage analysis, for example for interconnect delay computations, has been used for circuit timing verification. The method of the present invention may further use the moments computed for a previous or contemporaneous voltage transient analysis, or may compute the circuit moments independently. In circuit moment transient voltage analysis, the voltage at the i th node is computed in the s-domain according to:

V i ( s )= H i ( s )× V in ( s )

where V i (s) is the voltage at the i th circuit node and V in (s) is the input voltage. H i (s) is the Laplace transform of the impulse response h(t) at the i th node and is given by

H i ⁡ ( s ) = m 0 i + m 1 i ⁢ s + m 2 i ⁢ s 2 + m 3 i ⁢ s 3 + … = ∑ k = 0 0 ⁢ u ⁢ m k i ⁢ s k

according to the circuit moment model. m p i is the p th moment of the transformed impulse response H i (s) at node i, which can be expressed as:

m p i = ∑ k ⁢ ( - R ik ⁢ C k ⁢ m p - 1 i )

for an RC tree, where C k is the shunt capacitance at node k as shown in the Figure, and R ik is the total overlap resistance in the unique paths from the source node to nodes i and k. The above equations are used in transient voltage analyses to obtain the voltage waveforms and in models that determine delay times using functions that are fit to the waveforms using the moment values.

In the present invention, current moments are computed to obtain the distribution of current through a metal layer interconnect Since the current flowing through a path from node i to node k, I ik (s), is given by

I ik ⁡ ( s ) = V i ⁡ ( s ) - V k ⁡ ( s ) R ik ⁢ ⁢ then ⁢ ⁢ I ik ⁡ ( s ) = V i ⁢ ⁢ n ⁡ ( s ) R ik ⁢ ( H i ⁡ ( s ) - H k ⁡ ( s ) )

which can be expanded in terms of the circuit moments as

I ik ⁡ ( s ) = V i ⁢ ⁢ n ⁡ ( s ) R ik ⁢ ( Δ ⁢ ⁢ m 1 ik ⁢ s + Δ ⁢ ⁢ m 2 ik ⁢ s 2 + Δ ⁢ ⁢ m 3 ik ⁢ s 3 ⁢ … )

where each term

Δ ⁢ ⁢ m p ik = ( m p i - m p k )

represents the difference between the p th circuit moments of nodes i and k.

For a saturated ramp (constant source current) input voltage with rise-time T r and unit voltage, the input voltage in the s-domain is represented by

V in ⁡ ( s ) = 1 - ⅇ - sT r s 2 ⁢ T r

The transient current between node i and node k can be expressed as

j ik ( s )= m 0 ik +m 1 ik s+m 2 ik s 2

in which m p ik is the p-th moment of the current wave form through the model resistance R ik between nodes i and k. The first three current moments through an element R ik for the linear ramp waveform above can be computed in terms of only higher-order moments

m 0 ik = ⁢ Δ ⁢ ⁢ m 1 ik R ik m 1 ik = ⁢ 1 R ik ⁢ ( Δ ⁢ ⁢ m 2 ik - T r 2 ⁢ Δ ⁢ ⁢ m 1 ik ) m 2 ik = ⁢ 1 R ik ⁢ ( Δ ⁢ ⁢ m 3 ik - T r 2 ⁢ Δ ⁢ ⁢ m 2 ik + T r 2 6 ⁢ Δ ⁢ ⁢ m 1 ik )

Although in the embodiment described herein, a linear ramp input voltage is used to derive the moments as expressed above, any time-varying voltage input to the circuit can be easily analyzed and expressions for the moments derived in a similar manner. The current moment value can then be easily calculated for any resistive element in an arbitrary RC tree. In general, the current moment calculation has minimal impact on the computational overhead, because the circuit moments for each node are generally already available from an earlier-performed interconnect delay analysis on the same circuits.

Once the current moments according to the model have been computed, the shape of the current waveform between two nodes can be determined, and the peak, average and rms current values obtained. However, computation time can be further reduced by providing a closed-form solution for the peak, average and rms current values and computing the values by a method according to an embodiment of the invention. The definition of a Laplace transform indicates that

I ik ⁡ ( s ) = ∫ 0 ∞ ⁢ I ik ⁡ ( t ) ⁢ ⅇ - kt ⁢ ⁢ ⅆ t = ∑ n = 0 ∞ ⁢ ⁢ ( - 1 ) n n ! ⁢ s n ⁢ ∫ 0 ∞ ⁢ t n · I ik ⁡ ( t ) ⁢ ⁢ ⅆ t

and the individual current moments are terms of the above summation according to their corresponding power of s. For example, the first three individual current moments are given by

∫ 0 ∞ ⁢ I ik ⁡ ( t ) ⁢ ⁢ ⅆ t = m 11 ik ∫ 0 ∞ ⁢ t · I ik ⁡ ( t ) ⁢ ⁢ ⅆ t = - m 1 ik ∫ 0 ∞ ⁢ t 2 · I ik ⁡ ( t ) ⁢ ⁢ ⅆ t = m 2 ik

The zero-order moment is the total charge transfer from node i to node k due to the input ramp signal, and therefore the average current can be approximated as

I ik inz = 1 T C ⁢ ∫ 11 T C ⁢ I ik ⁡ ( t ) ⁢ ⁢ ⅆ t = 1 T C ⁢ ∫ 11 ∞ ⁢ I ik ⁡ ( t ) ⁢ ⁢ ⅆ t = m n ik T C

where the integration limit T c is changed to infinity, since nodes i and k have substantially settled to their steady-state values after the current transient caused by the input ramp signal. Thus, the average current is readily available in a closed-form solution once the 0 th order current moment has been obtained.

However, the peak and rms values of the current require more information about the shape of the current waveform. Normalizing the current waveform according to the average value of the current provides a waveform that satisfies the following conditions, which are sufficient conditions to use a probability density function (pdf) to model the current waveform:

x ik ⁡ ( t ) ≥ 0 ⁢ ⁢ for ⁢ ⁢ all ⁢ ⁢ t ∫ 0 ∞ ⁢ x ik ⁡ ( t ) ⁢ ⁢ ⅆ t = 1

The first condition is satisfied for the first-order nature of the RC circuit assumption, (i.e., there is no current undershoot), and the second is satisfied by the condition of normalization. The normalized current waveform can be expressed in the s-domain as

=

The shape of the waveform has been found to be modeled very accurately using a lognormal distribution function, which also provides closed-form solutions for the rms and peak values of current. The two-parameter lognormal density function is given by

f ⁡ ( t ) = 1 tS ⁢ 2 ⁢ π ⁢ ⅇ - 1 2 ⁢ ( ln ⁢ ⁢ t ⁢ ⁢ M S ) 2

where S>0 and is known as the shape parameter, and where M>0 and is known as the scale parameter. The first two moments of a lognormal distribution are given by

∫ 0 ∞ ⁢ t · f ⁡ ( t ) ⁢ ⁢ ⅆ t = ⅇ M + S 2 λ ∫ 0 ∞ ⁢ t 2 · f ⁡ ( t ) ⁢ ⁢ ⅆ t = ⅇ 2 ⁢ ( M + S 2 )

The above relations provide that corresponding integrals of the normalized current x ik (t) in the time domain can be expressed in terms of current moments from the above-given s-domain expression for current X ik (s) in terms of moments, thus:

∫ 0 ∞ ⁢ t · x ik ⁡ ( t ) ⁢ ⁢ ⅆ t = - m 1 ik m 0 ik ∫ 0 ∞ ⁢ t 2 · x ik ⁡ ( t ) ⁢ ⁢ ⅆ t = 2 ⁢ m 2 ik m 0 ik

From the above expression, the parameters M and S of the lognormal distribution approximating the current waveform can be computed from

M = ln ⁡ ( ( m 1 ik ) 2 m 0 ik ⁢ 2 ⁢ ⁢ m 2 ik ⁢ m 0 ik ) S = ln ⁡ ( 2 ⁢ ⁢ m 2 ik ⁢ m 0 ik ( m 1 ik ) 2 )

which can be derived by equating the expressions for M and S and the s-domain expression for current X ik (s) in the integral equations above and taking the natural logarithm of both sides of the resulting equalities. Even though the above expressions only include the first three current moments, the higher-order moments on which the currents depend can also be computed and included in the model.

Once the shape and scale parameters of the lognormal distribution are known in terms of current moments, the current waveform I ik (t) can be modeled as

I ik ⁡ ( t ) = m 0 ik × x ik ⁡ ( t ) = in 0 ik iS ⁢ 2 ⁢ π ⁢ ⅇ - 1 2 ⁢ ( ln ⁢ ⁢ t - M S ) 2

according to the lognormal distribution. The root-mean-square current value is

I ik rms = 1 T C ⁢ ∫ 0 T C ⁢ I ik 2 ⁡ ( t ) ⁢ ⁢ ⅆ t ≈ 1 T C ⁢ ∫ 0 ∞ ⁢ I ik 2 ⁡ ( t ) ⁢ ⁢ ⅆ t

which can be approximated by an integral over [0:∞] as described above for the average current computation. The above integral can be solved in a closed-form manner yielding the following expression for the root-mean-square current:

I

ik

rms

=

Finally, the peak current is the maximum value of the current during a switching event (modeled by the ramp input voltage above) and can also be calculated in closed-form with respect to the lognormal distribution model. From the probabilistic interpretation of the lognormal distribution, the peak value refers to the “mode” of the distribution. Using the analytical expression of the mode of a lognormal function, the following expression is obtained for the peak current:

I ik peak = m 0 ik ⁢ ⅇ - M + S 2 2 2 ⁢ π ⁢ S

The set of expressions for peak, average and rms current given above can then be used to calculate the average, root-mean-square and peak current densities required for electromigration-based reliability analysis of signal interconnects. Further, the techniques disclosed above can be used to study the effects of the line resistance by varying R ik and slew rate by varying T r .

Referring now to FIG. 2A , results of a waveform reconstruction of the above-described lognormal distribution approximation are shown. The dashed line indicates a substantially ideal SPICE model result, and the solid line indicates the analytical result from a lognormal distribution embodiment of a method in accordance with the present invention as described above. The analytical current results shows close conformity with the SPICE model current results for both ends i(near), i(far) of the interconnect as well as the midpoint i(mid). Other simulations have confirmed that the result is a very close approximation to the actual current waveshape over the entire interconnect. FIG. 2B shows a fit between the analytical results for rms I rms , average I avg and peak I peak current values, where the triangles show SPICE calculations, and crosses show the current values obtained from the analytical expressions in terms of current moments as detailed above.

FIG. 3A shows results of a use of the analytical model to study the effects of variation in T r . Again, SPICE simulation results are shown using triangles alongside the crosses indicating the analytical results for variations in the input voltage slew rate. FIG. 3B shows results of a use of the analytical model to study the effects of variation in total interconnect resistance. SPICE simulation results are shown again using triangles alongside the crosses indicating the analytical results for variations in the input voltage slew rate.

Referring now to FIG. 4 , a workstation computer system 40 is shown in which the methods of the present invention are carried out in accordance with an embodiment of the present invention, according to program instructions that may be embodied in a computer program product in accordance with a present invention, for example program instructions stored on a CD-ROM disc CD. Workstation computer system includes a processor 42 for executing the program instructions coupled to a memory 44 for storing the program instructions, data and results used in performing methods in accordance with embodiments of the present invention. Workstation computer system 40 also includes peripheral devices such as CD-ROM drive 45 for reading discs such as CD in order to load the program instructions into workstation computer 45 . Input devices, such as a keyboard 47 A and a mouse 47 B are coupled to workstation computer system 40 for receiving user input. A graphical display 46 for displaying results such as the waveforms shown above in FIG. 2A and/or graphical/textual data such as is illustrated in FIG. 2B and FIGS. 3A-3B , along with other values determined in conformity with modeling methods in accordance with embodiments of the present invention. The depicted workstation computer 40 is only exemplary and illustrates one type of computer system and arrangement suitable for carrying out the methods of the present invention, and it is understood that program embodiments of the present invention may be remotely located and/or executed on a remote system such as an application server coupled to a local workstation that displays and/or uses the results of the above-described methods.

Referring now to FIG. 5 , a method in accordance with an embodiment of the present invention is illustrated. First, an interconnect segment is selected between nodes i,k and the circuit moments m p are retrieved (from prior analyses) or computed for node i and node k (step 50 ). Next, n current moments m p ik are computed for the segment between node i and node k from the difference between circuit moments m p i −m p k for the nodes and the overlap resistance R ik in conformity with a particular input voltage model, e.g. a saturated ramp as described above (step 51 ). The average current is then calculated from the zero-order current moment m 0 ik (step 52 ) and the rms and peak current values are calculated from the analytical expressions according to the assumption of lognormal (or other) distribution shape (step 53 ). The results are stored (step 54 ) and until the last node is traversed (decision 55 ), steps 50 - 54 are repeated after the next nodes i,k are selected (step 56 ). After the last node is traversed (decision 55 ), the reliability factors can be computed and the results displayed and/or used in further reliability computations (step 57 ).

While the invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form, and details may be made therein without departing from the spirit and scope of the invention.