CPU frequency regulating circuit

1. Field of the Invention

The present invention relates to regulating circuits, and particularly to a central processing unit (CPU) frequency regulating circuit.

2. Description of Related Art

Conventionally, working frequency of a computer is set by manipulating jumpers or other switches on a motherboard of the computer. The jumpers are changed in accordance with instructions in a user guide of the motherboard so as to change a CPU multiple frequency factor and to control the frequency generation of a frequency generator. This, however, may be troublesome to ordinary consumers since most people are not familiar with such a technique, and thus, although the user may follow the instructions of the user guide, it is still possible and very often that the computer user cannot perform the frequency modification operation correctly.

An incorrect setting of the working frequency may result in damage to the CPU. Therefore to overcome such a problem, some of the computer motherboard manufacturers provide a solution which allows the computer user to set the multiple frequency factor directly on the computer screen, similar to the general setting operation of the computer BIOS.

The conventional way of setting the working frequency is to perform the operation under the condition that the computer is already booted. The setting operation provides frequency information and a frequency switching address signal, which after being decoded, is stored in a storage device. In response to the frequency information, the storage device generates a corresponding multiple frequency factor signal and a frequency selection signal, which are applied to the CPU, and a frequency generator signal and a reset signal are sent from a resetting unit to the CPU and the system chipset to enter a hardware-resetting mode. After the resetting operation, the system chip supplies a reset feedback signal to clear the previous status of the resetting unit which permits the CPU and the system chipset to operate based on the newly selected multiple frequency factor and working frequency. Although this way provides an effective switching operation between different frequencies, it requires additional parts, such as the resetting unit and the storage device. This device and unit may constitute a substantial cost loss to the computer main board manufacturers who usually mass produce computer main boards so that even a tiny increase of the cost for each piece of computer main board would eventually result in a major loss of money for the computer main board manufacturers.

What is needed, therefore, is a CPU frequency regulating circuit for selecting a frequency of the CPU automatically at a low cost.

An exemplary CPU frequency regulating circuit includes a detecting circuit, and a comparing circuit. The detecting circuit receives a pulse width modulation (PWM) signal from a super I/O chipset, and converts the PWM signal to a load voltage responsive to workload of a CPU. The comparing circuit is coupled to the detecting circuit for receiving the load voltage, and compares the load voltage with a reference voltage, and adjusts a frequency of the CPU according to the comparison.

Other advantages and novel features will become more apparent from the following detailed description when taken in conjunction with the accompanying drawing, in which:

The drawing is a circuit diagram of one embodiment of a CPU frequency regulating circuit in accordance with the present invention.

Referring to the drawing, a CPU frequency regulating circuit in accordance with a preferred embodiment of the present invention includes a detecting circuit 20 , and a comparing circuit 30 . The detecting circuit 20 receives a pulse width modulation (PWM) signal with a fixed frequency output from a super I/O chipset 40 . Generally, a duty cycle of the PWM signal increases according to a workload of a CPU in a computer system. The detecting circuit 20 converts the PWM signal to a smooth and stable load voltage OC_V. The comparing circuit 30 receives the load voltage OC_V and generates a control signal EN_OC according to the load voltage OC_V. The super I/O chipset 40 receives the control signal EN_OC and adjusts a frequency of the CPU.

The detecting circuit 20 includes an amplifier 14 and a transistor Q. The PWM signal is applied to an inverting terminal of the amplifier 14 via a resistor R 1 , and a node between the resistor R 1 and the inverting terminal of the amplifier 14 is connected to ground via a capacitor C 1 . A power terminal of the amplifier 14 is connected to a 12V power source, and a ground terminal of the amplifier 14 is grounded. An output of the amplifier 14 is connected to a base of the transistor Q via a resistor R 2 . An emitter of the transistor Q is connected to the base of the transistor Q via a resistor R 3 , and connected to the 12V power source. A collector of the transistor Q is grounded via a second capacitor C 2 . A node between the collector of the transistor Q and the capacitor C 2 is connected to ground via a resistor R 4 and a resistor R 5 . A node between the resistors R 4 and R 5 is connected to a non-inverting terminal of the amplifier 14 . The resistors R 4 and R 5 form a feedback circuit of the amplifier 14 .

The comparing circuit 30 includes a comparator U having a non-inverting terminal connected to a node between the resistor R 4 and the capacitor C 2 , and an inverting terminal connected to the 12V power source via a resistor R 8 . Two logic signals OC_CTL 1 and OC_CTL 2 are applied to the inverting terminal of the comparator U via a resistor R 6 and a resistor R 7 respectively. The two logic signals OC_CTL 1 and OC_CTL 2 are generated in the super I/O chipset 40 . A power terminal of the comparator U is connected to the 12V power source, and a ground terminal of the comparator U is grounded. An output of the comparator U is connected to ground via two resistors R 9 and R 10 . The control signal EN_OC generated at a node between the resistors R 9 and R 10 is applied to the super I/O chipset 40 .

The load voltage OC_V at the non-inverting terminal of the comparator U is a sampling voltage of the workload of the CPU. A reference voltage Vref at the inverting terminal of the comparator U is determined by the state of the two logic signals OC_CTL 1 and OC_CTL 2 .

In the preferred embodiment, a low voltage signal is represented as “0” and a high voltage signal is represented as “1.” Therefore a combination of the two logic signals OC_CTL 1 and OC_CTL 2 is represented by a two-digit binary sequence. For example, if both signals are low voltage signals, the combination of the logic signals OC_CTL 1 and OC_CTL 2 is represented as “00.” If both logic signals of are high voltage signals, the combination of the logic signals OC_CTL 1 and OC_CTL 2 is represented as “11.” The preferred resistances of the resistors R 6 , R 7 , and R 8 are 130 ohm, 330 ohm, and 90 ohm respectively.

When the combination of the logic signals OC_CTL 1 and OC_CTL 2 is represented as “00”, the resistors R 6 and R 7 are all connected to ground. At this moment, the reference voltage Vref at the inverting terminal of the comparator U is determined by the following equation:

Vref

=

when the combination of the logic signals OC_CTL 1 and OC_CTL 2 is represented as “01”, the resistor R 6 is connected to ground, and the resistor R 7 is not connected in the circuit. At this moment, the reference voltage Vref at the inverting terminal of the comparator U is determined by the following equation:

Vref

=

when the combination of the logic signals OC_CTL 1 and OC_CTL 2 is represented as “10”, the resistor R 6 is not connected in the circuit, and the resistor R 7 is connected to ground. At this moment, the reference voltage Vref at the inverting terminal of the comparator U is determined by the following equation:

Vref

=

When the combination of the logic signals OC_CTL 1 and OC_CTL 2 is represented as “11”, the resistors R 6 and R 7 are not connected in circuit. At this moment, the reference voltage Vref at the inverting terminal of the comparator U is 12V. Table 1 shows signal levels of the two logic signals OC 13 CTL 1 and OC_CTL 2 and corresponding reference voltages.

The example presented below is designed to illustrate how to adjust the CPU frequency when the combination of the logic signals OC 13 CTL 1 and OC_CTL 2 is represented as “00”. The reference voltage Vref is 6V. At the instant the computer system is turned on, the computer system involving the CPU frequency regulating circuit is started, the PWM signal is converted into an analog output signal by the resistor R 1 and the capacitor C 1 to be applied to the non-inverting terminal of the amplifier 14 , a voltage at the inverting terminal of the amplifier 14 is nearly 0V at the moment of starting, and a voltage at the output terminal of the amplifier 14 is also 0V. The transistor Q is turned on, a high voltage at the collector of the transistor Q is applied to the non-inverting terminal of the amplifier 14 via the feedback circuit (R 4 and R 5 ), so the voltage at the non-inverting terminal of the amplifier 14 increases. When the voltage at the non-inverting terminal of the amplifier 14 increases to equal the voltage at the inverting terminal of the amplifier 14 , the load voltage OC 13 V is a stable voltage and compared with the reference voltage Vref, and the CPU works at a normal frequency.

When the load of the CPU increases, for example, a 3D game is running in the computer system, a duty cycle of the PWM signal increases, the voltage at the inverting terminal of the amplifier 14 increases, because of the feedback circuit, the voltage at the non-inverting terminal of the comparator 14 increases. Accordingly, the load voltage OC_V increases to a higher stable voltage and compared with the reference voltage Vref. If the load voltage OC_V is higher than the reference voltage Vref, the comparator U outputs the EN_OC signal to the super I/O chipset 40 to adjust a clock circuit of the CPU to provide a higher frequency to the CPU. If the load voltage OC_V is lower than the reference voltage Vref, the frequency of the CPU remains unchanged.

The operation of adjusting frequency of the CPU of other combinations of the logic signals OC_CTL 1 and OC_CTL 2 is similar to the previous example. The CPU frequency regulating circuit detects the load voltage of the CPU for selecting an appropriate frequency to the CPU according to a working condition.

It is believed that the present invention and its advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the invention or sacrificing all of its material advantages, the example hereinbefore described merely being a preferred or exemplary embodiment of the invention.