Semiconductor memory

This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2005-339445 filed on Nov. 24, 2005; the entire contents of which are incorporated by reference herein.

1. Field of the Invention

The present invention relates to a semiconductor memory and in particular to a static random access memory (SRAM).

2. Description of the Related Art

As described in Japanese Patent Laid-Open Publication No. 2003-132684, the SRAM cell can be classified into two types. One is a single port SRAM cell including an input/output port for a single data transfer. Another is a multi port SRAM cell including a plurality of input/output ports for a plurality of data transfers. Further, the multi port SRAM cell can be classified into two types. One is a one read and one write SRAM cell including a single write port and a single read port. Another is a one read and two write SRAM cell including the two write ports and the single read port.

The typical semiconductor memory includes the plurality of SRAM cells arranged in an array. Therefore, when the start row address of sequential data to be written is even and the end row address of the sequential data is odd, the sequential data are written in the plurality of SRAM cells disposed over a plurality of rows. If the plurality of one read and one write SRAM cells are used for the semiconductor memory, the data associated with even row address are unintentionally written in the SRAM cell of which the row address is odd. Or, the data associated with odd row address are unintentionally written in the SRAM cell of which the row address is even. Accordingly, the semiconductor memory, such as the buffer memory, used for storing such sequential data has necessarily used the plurality of one read and two write SRAM cells or the plurality of two read and two write SRAM cells. However, the one read and two write SRAM cell and the two read and two write SRAM cell are more expensive than the one read and one write SRAM cell.

An aspect of present invention inheres in a semiconductor memory according to an embodiment of the present invention. The semiconductor memory includes a plurality of memory cells for even addresses arranged in a memory array for even addresses and configured to store even addressed data, the even addressed data being associated with even row addresses, a plurality of write word lines for even addresses arranged parallel to a row direction of the memory array for even addresses and configured to select the plurality of memory cells for even addresses in the row direction of the memory array for even addresses to write the even addressed data, a plurality of write bit lines for even addresses arranged parallel to a column direction of the memory array for even addresses and configured to transfer the even addressed data to the plurality of memory cells for even addresses in the column direction of the memory array for even addresses, a plurality of memory cells for odd addresses arranged in a memory array for odd addresses and configured to store odd addressed data, the odd addressed data being associated with odd row addresses, a plurality of write word lines for odd addresses arranged parallel to a row direction of the memory array for odd addresses and configured to select the plurality of memory cells for odd addresses in the row direction of the memory array for odd addresses to write the odd addressed data, and a plurality of write bit lines for odd addresses arranged parallel to a column direction of the memory array for odd addresses and configured to transfer the odd addressed data to the plurality of memory cells for odd addresses in the column direction of the memory array for odd addresses.

FIG. 1 is a diagram of a semiconductor memory in accordance with a first embodiment of the present invention;

FIG. 2 is a circuit diagram of memory arrays of the semiconductor memory in accordance with the first embodiment of the present invention;

FIG. 3 is a circuit diagram of a memory cell of the semiconductor memory in accordance with the first embodiment of the present invention;

FIG. 4 is a diagram of a semiconductor memory according to a comparative example;

FIG. 5 is a circuit diagram of a memory array of the semiconductor memory according to the comparative example;

FIG. 6 is a circuit diagram of a memory cell of the semiconductor memory according to the comparative example;

FIG. 7 is a diagram of the semiconductor memory in accordance with a second embodiment of the present invention;

FIG. 8 is a first circuit diagram of a memory array of the semiconductor memory in accordance with the second embodiment of the present invention; and

FIG. 9 is a second circuit diagram of the memory array of the semiconductor memory in accordance with the second embodiment of the present invention.

Embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified.

First Embodiment

With reference to FIG. 1 , a semiconductor memory, according to the first embodiment, includes a memory array 20 for even addresses and a memory array 21 for odd addresses. It is possible to write any 24 bit of 144 bit address space in the semiconductor memory, for example. With reference to FIG. 2 , a plurality of memory cells M 001 , . . . , M 009 , M 010 , . . . , M 024 , M 201 , . . . , M 209 , M 210 , . . . , M 224 , M 401 , . . . , M 409 , M 410 , . . . , M 424 for even addresses are disposed in the memory array 20 for even addresses. The plurality of memory cells M 001 -M 424 for even addresses are arranged in an array of three rows and 24 columns. The plurality of memory cells M 001 -M 424 for even addresses are configured to store even addressed data. “The even addressed data” are associated with even row addresses, respectively. Here, zero is included in the even numbers. Specifically, each of the plurality of memory cells M 001 , . . . , M 009 , M 010 , . . . , M 024 for even addresses stores the even addressed data associated with the row address “0”. Each of the plurality of memory cells M 201 , . . . , M 209 , M 210 , . . . , M 224 for even addresses stores the even addressed data associated with the row address “2”. Each of the plurality of memory cells M 401 , . . . , M 409 , M 410 , . . . , M 424 for even addresses stores the even addressed data associated with the row address “4”.

The plurality of memory cells M 001 , . . . , M 009 , M 010 , . . . , M 024 for even addresses are disposed in a row direction of the memory array 20 for even addresses. The plurality of memory cells M 201 , . . . , M 209 , M 210 , . . . , M 224 for even addresses are parallel with the plurality of memory cells M 001 , . . . , M 009 , M 010 , . . . , M 024 for even addresses. The plurality of memory cells M 401 , . . . , M 409 , M 410 , . . . , M 424 for even addresses are parallel with the plurality of memory cells M 201 , . . . , M 209 , M 210 , M 224 for even addresses.

Further, the memory array 20 for even addresses includes a plurality of write word lines WW 0 , WW 2 , WW 4 for even addresses. The plurality of write word lines WW 0 , WW 2 , WW 4 for even addresses are configured to access the plurality of memory cells M 001 -M 024 , M 201 -M 224 , M 401 -M 424 in the row direction, during a write operation of the even addressed data. The plurality of write word lines WW 0 , WW 2 , WW 4 for even addresses are parallel with the row direction of the memory array 20 for even addresses. Specifically, the write word line WW 0 for even addresses is electrically connected to gates of a pair of write transistors in each of the plurality of memory cells M 001 -M 024 for even addresses, as described below. The write word line WW 2 for even addresses is electrically connected to gates of a pair of write transistors in each of the plurality of memory cells M 201 -M 224 for even addresses. The write word line WW 4 for even addresses is electrically connected to gates of a pair of write transistors in each of the plurality of memory cells M 401 -M 424 for even addresses.

Also, the memory array 20 for even addresses includes a plurality of read word lines RW 0 , RW 2 , RW 4 for even addresses. The plurality of read word lines RW 0 , RW 2 , RW 4 for even addresses are configured to access the plurality of memory cells M 001 -M 024 , M 201 -M 224 , M 401 -M 424 in the row direction, during a read operation of the even addressed data. The plurality of read word lines RW 0 , RW 2 , RW 4 for even addresses are parallel with the row direction of the memory array 20 for even addresses. The read word line RW 0 for even addresses is electrically connected to gates of a pair of read transistors in each of the plurality of memory cells M 001 -M 024 for even addresses, as described below. The read word line RW 2 for even addresses is electrically connected to gates of a pair of read transistors in each of the plurality of memory cells M 201 -M 224 for even addresses. The read word line RW 4 for even addresses is electrically connected to gates of a pair of read transistors in each of the plurality of memory cells M 401 -M 424 for even addresses.

The memory array 20 for even addresses further includes a plurality of write bit lines WBE 1 a , WBE 1 b , . . . , WBE 9 a , WBE 9 b , WBE 10 a , WBE 10 b , WBE 24 a , WBE 24 b for even addresses. The plurality of write bit lines WBE 1 a , WBE 1 b , . . . , WBE 9 a , WBE 9 b , WBE 10 a , WBE 10 b , . . . WBE 24 a , WBE 24 b for even addresses are configured to transfer the even addressed data to be written to each of the plurality of the memory cells M 001 -M 024 , M 201 -M 224 , M 401 -M 424 for even addresses in a column direction of the memory array 20 for even addresses, during the write operation. The plurality of write bit lines WBE 1 a , WBE 1 b , . . . , WBE 9 a , WBE 9 b , WBE 10 a , WBE 10 b , . . . WBE 24 a , WBE 24 b for even addresses are parallel with the column direction. The pair of write bit lines WBE 1 a , WBE 1 b for even addresses is electrically connected to drain regions of the pair of write transistors in each of the plurality of memory cells M 001 , M 201 , M 401 for even addresses configured to store the even addressed data associated with the column address “1” and the even row address, respectively. The pair of write bit lines WBE 9 a , WBE 9 b for even addresses is electrically connected to drain regions of the pair of write transistors in each of the plurality of memory cells M 009 , M 209 , M 409 for even addresses configured to store the even addressed data associated with the column address “9” and the even row address, respectively. The pair of write bit lines WBE 10 a , WBE 10 b for even addresses is electrically connected to drain regions of the pair of write transistors in each of the plurality of memory cells M 010 , M 210 , M 410 for even addresses configured to store the even addressed data associated with the column address “10” and the even row address, respectively. The pair of write bit lines WBE 24 a , WBE 24 b for even addresses is electrically connected to drain regions of the pair write transistors in each of the plurality of memory cells M 024 , M 224 , M 424 for even addresses configured to store the even addressed data associated with the column address “24” and the even row address, respectively.

The memory array 20 for even addresses further includes a plurality of read bit lines RBE 1 a , RBE 1 b , . . . , RBE 9 a , RBE 9 b , RBE 10 a , RBE 10 b , . . . RBE 24 a , RBE 24 b for even addresses. The plurality of read bit lines RBE 1 a , RBE 1 b , . . . , RBE 9 a , RBE 9 b , RBE 10 a , RBE 10 b , . . . RBE 24 a , RBE 24 b for even addresses are configured to transfer the even addressed data to be read from each of the plurality of memory cells M 001 -M 024 , M 201 -M 224 , M 401 -M 424 for even addresses in the column direction, during the read operation. The plurality of read bit lines RBE 1 a , RBE 1 b , . . . , RBE 9 a , RBE 9 b , RBE 10 a , RBE 10 b , RBE 24 a , RBE 24 b for even addresses are parallel with the column direction of the memory array 20 for even addresses. The pair of read bit lines RBE 1 a , RBE 1 b for even addresses is electrically connected to drain regions of the pair of read transistors in each of the memory cells M 001 , M 201 , M 401 for even addresses configured to store the even addressed data associated with the column address “1” and the even row address, respectively. The pair of read bit lines RBE 9 a , RBE 9 b for even addresses is electrically connected to drain regions of the pair of read transistors in each of the memory cells M 009 , M 209 , M 409 for even addresses configured to store the even addressed data associated with the column address “9” and the even row address, respectively. The pair of read bit lines RBE 10 a , RBE 10 b for even addresses is electrically connected to drain regions of the pair of read transistors in each of the memory cells M 010 , M 210 , M 410 for even addresses configured to store the even addressed data associated with the column address “10” and the even row address, respectively. The pair of read bit lines RBE 24 a , RBE 24 b for even addresses is electrically connected to drain regions of the pair of read transistors in each of the memory cells M 024 , M 224 , M 424 for even addresses configured to store the even addressed data associated with the column address “24” and the even row address, respectively.

When the even addressed data is written in each of the plurality of memory cells M 001 -M 024 , M 201 -M 224 , M 401 -M 424 for even addresses, a write decoder 60 for even addresses, shown in FIG. 1 , transfers an even address signal for the write operation to each of the plurality of write word lines WW 0 , WW 2 , WW 4 for even addresses, shown in FIG. 2 , to select the row address for the even addressed data to be stored. When the even addressed data is read from each of the plurality of memory cells M 001 -M 024 , M 201 -M 224 , M 401 -M 424 for even addresses, a read decoder 62 for even addresses, shown in FIG. 1 , transfers an even address signal for the read operation to each of the plurality of read word lines RW 0 , RW 2 , RW 4 for even addresses, shown in FIG. 2 , to select the row address for the even addressed data to be read.

A write precharge circuit 40 for even addresses, shown in FIG. 1 , is configured to prechage a high level voltage to each of the plurality of write bit lines WBE 1 a , WBE 1 b , . . . , WBE 24 a , WBE 24 b for even addresses, shown in FIG. 2 . A write amplifier 30 for even addresses, shown in FIG. 1 , is configured to write the even addressed data to each of the plurality of memory cells M 001 -M 024 , M 201 -M 224 , M 401 -M 424 for even addresses, shown in FIG. 2 , through the plurality of write bit lines WBE 1 a , WBE 1 b , . . . , WBE 24 a , WBE 24 b for even addresses. A read precharge circuit 42 for even addresses, shown in FIG. 1 , is configured to precharge the high level voltage to each of the plurality of read bit lines RBE 1 a , RBE 1 b , . . . , RBE 24 a , RBE 24 b for even addresses, shown in FIG. 2 . A read amplifier 50 for even addresses, shown in FIG. 1 , is configured to read the even addressed data from each of the plurality of memory cells M 001 -M 024 , M 201 -M 224 , M 401 -M 424 for even addresses, shown in FIG. 2 , through the plurality of read bit lines RBE 1 a , RBE 1 b , RBE 24 a , RBE 24 b for even addresses.

A plurality of memory cells M 101 , . . . , M 109 , M 110 , M 124 , M 301 , . . . , M 309 , M 310 , . . . , M 324 , M 501 , . . . , M 509 , M 510 , . . . , M 524 for odd addresses are disposed in the memory array 21 for odd addresses, shown in FIG. 1 . The plurality of memory cells M 101 -M 524 for odd addresses are arranged in the array of three rows and 24 columns. The plurality of memory cells M 101 -M 524 for odd addresses are configured to store odd addressed data. “The odd addressed data” are associated with odd row addresses, respectively. Specifically, each of the plurality of memory cells M 101 , . . . , M 109 , M 110 , . . . , M 124 for odd addresses stores the odd addressed data associated with the row address “1”. Each of the plurality of memory cells M 301 , . . . , M 309 , M 310 , . . . , M 324 for odd addresses stores the odd addressed data associated with the row address “3”. Each of the plurality of memory cells M 501 , . . . , M 509 , M 510 , . . . , M 524 for odd addresses stores the odd addressed data associated with the row address “5”.

The plurality of memory cells M 101 , . . . , M 109 , M 110 , M 124 for odd addresses are disposed in the row direction of the memory array 21 for odd addresses. The plurality of memory cells M 301 , . . . , M 309 , M 310 , . . . , M 324 for odd addresses are parallel with the plurality of memory cells M 101 , . . . , M 109 , M 110 , . . . , M 124 for odd addresses, respectively. The plurality of memory cells M 501 , . . . , M 509 , M 510 , . . . , M 524 for odd addresses are parallel with the plurality of memory cells M 301 , M 309 , M 310 , . . . , M 324 for odd addresses, respectively.

Further, the memory array 21 for odd addresses includes a plurality of write word lines WW 1 , WW 3 , WW 5 for odd addresses. The plurality of write word lines WW 1 , WW 3 , WW 5 for odd addresses are configured to access the plurality of memory cells M 101 -M 124 , M 301 -M 324 , M 501 -M 524 for odd addresses in the row direction, during a write operation of the odd addressed data. The plurality of write word lines WW 1 , WW 3 , WW 5 for odd addresses are parallel with the row direction of the memory array 21 for odd addresses. Specifically, the write word line WW 1 for odd addresses is electrically connected to gates of a pair of write transistors in each of the plurality of memory cells M 101 -M 124 for odd addresses. The write word line WW 3 for odd addresses is electrically connected to gates of a pair of write transistors in each of the plurality of memory cells M 301 -M 324 for odd addresses. The write word line WW 5 for odd addresses is electrically connected to gates of a pair of write transistors in each of the plurality of memory cells M 501 -M 524 for odd addresses.

Also, the memory array 21 for even addresses includes a plurality of read word lines RW 1 , RW 3 , RW 5 for odd addresses. The plurality of read word lines RW 1 , RW 3 , RW 5 for odd addresses are configured to access the plurality of memory cells M 101 -M 124 , M 301 -M 324 , M 501 -M 524 for odd addresses in the row direction, during a read operation of the odd addressed data. The plurality of read word lines RW 1 , RW 3 , RW 5 for odd addresses are parallel with the row direction of the memory array 21 for odd addresses. The read word line RW 1 for odd addresses is electrically connected to gates of a pair of read transistors in each of the plurality of memory cells M 101 -M 124 for odd addresses. The read word line RW 3 for odd addresses is electrically connected to gates of a pair of read transistors in each of the plurality of memory cells M 301 -M 324 for odd addresses. The read word line RW 5 for odd addresses is electrically connected to gates of a pair of read transistors in each of the plurality of memory cells M 501 -M 524 for odd addresses.

The memory array 21 for odd addresses further includes a plurality of write bit lines WBO 1 a , WBO 1 b , . . . , WB 09 a , WBO 9 b , WBO 10 a , WBO 10 b , . . . WBO 24 a , WBO 24 b for odd addresses. The plurality of write bit lines WBO 1 a , WBO 1 b , . . . , WBO 9 a , WBO 9 b , WBO 10 a , WBO 10 b , WBO 24 a , WBO 24 b for odd addresses are configured to transfer the odd addressed data to be written to each of the plurality of memory cells M 101 -M 124 , M 301 -M 324 , M 501 -M 524 for odd addresses in the column direction, during the write operation. The plurality of write bit lines WBO 1 a , WBO 1 b , . . . , WBO 9 a , WB 09 b , WBO 10 a , WBO 10 b , . . . WBO 24 a , WBO 24 b for odd addresses are parallel with the column direction of the memory array 21 for odd addresses. The pair of write bit lines WBO 1 a , WBO 1 b for odd addresses is electrically connected to drain regions of the pair of write transistors in each of the plurality of memory cells M 101 , M 301 , M 501 for odd addresses configured to store the odd addressed data associated with the column address “1” and the odd row address. The pair of write bit lines WBO 9 a , WBO 9 b for odd addresses is electrically connected to drain regions of the pair of write transistors in each of the plurality of memory cells M 109 , M 309 , M 509 for odd addresses configured to store the odd addressed data associated with the column address “9” and the odd row address. The pair of write bit lines WBO 11 a , WBO 10 b for odd addresses is electrically connected to drain regions of the pair of write transistors in each of the plurality of memory cells M 110 , M 310 , M 510 for odd addresses configured to store the odd addressed data associated with the column address “10” and the odd row address. The pair of write bit lines WBO 24 a , WBO 24 b for odd addresses is electrically connected to drain regions of the pair of write transistors in each of the plurality of memory cells M 124 , M 324 , M 524 for odd addresses configured to store the odd addressed data associated with the column address “24” and the odd row address.

The memory array 21 for odd addresses further includes a plurality of read bit lines RBO 1 a , RBO 1 b , RB 09 a , RBO 9 b , RBO 10 a , RBO 1 b , . . . RBO 24 a , RBO 24 b for odd addresses. The plurality of read bit lines RBO 1 a , RBO 1 b , . . . , RBO 9 a , RBO 9 b , RBO 10 a , RBO 10 b , . . . RBO 24 a , RBO 24 b for odd addresses are configured to transfer the odd addressed data to be read from each of the plurality of memory cells M 101 -M 124 , M 301 -M 324 , M 501 -M 524 for odd addresses in the column direction, during the read operation. The plurality of read bit lines RBO 1 a , RBO 1 b , . . . , RBO 9 a , RBO 9 b , RB 010 a , RBO 10 b , . . . RBO 24 a , RBO 24 b for odd addresses are parallel with the column direction of the memory array 21 for odd addresses. The pair of read bit lines RBO 1 a , RBO 1 b for odd addresses is electrically connected to drain regions of the pair of read transistors in each of the plurality of memory cells M 101 , M 301 , M 501 for odd addresses configured to store the odd addressed data associated with the column address “1”. The pair of read bit lines RBO 9 a , RBO 9 b for odd addresses is electrically connected to drain regions of the pair of read transistors in each of the plurality of memory cells M 109 , M 309 , M 509 for odd addresses configured to store the odd addressed data associated with the column address “9”. The pair of read bit lines RBO 10 a , RBO 10 b for odd addresses is electrically connected to drain regions of the pair of read transistors in each of the plurality of memory cells M 110 , M 310 , M 510 for odd addresses configured to store the odd addressed data associated with the column address “10”. The pair of read bit lines RBO 24 a , RBO 24 b for odd addresses is electrically connected to drain regions of the pair of read transistors in each of the plurality of memory cells M 124 , M 324 , M 524 for odd addresses configured to store the odd addressed data associated with the column address “24”.

When the odd addressed data is written in each of the plurality of memory cells M 101 -M 124 , M 301 -M 324 , M 501 -M 524 for odd addresses, a write decoder 61 for odd addresses, shown in FIG. 1 , transfers an odd address signal for the write operation to each of the plurality of write word lines WW 1 , WW 3 , WW 5 for odd addresses, shown in FIG. 2 , to select the row address for the odd addressed data to be stored. When the odd addressed data is read from each of the plurality of memory cells M 101 -M 124 , M 301 -M 324 , M 501 -M 524 for odd addresses, a read decoder 63 for odd addresses, shown in FIG. 1 , transfers an odd address signal for the read operation to each of the plurality of read word lines RW 1 , RW 3 , RW 5 for odd addresses, shown in FIG. 2 , to select the row address for the odd addressed data to be read.

A write precharge circuit 41 for odd addresses, shown in FIG. 1 , is configured to precharge the high level voltage to each of the plurality of write bit lines WBO 1 a , WBO 1 b , . . . , WBO 24 a , WBO 24 b for odd addresses, shown in FIG. 2 . A write amplifier 31 for odd addresses, shown in FIG. 1 , is configured to write the odd addressed data to each of the plurality of memory cells M 101 -M 124 , M 301 -M 324 , M 501 -M 524 for odd addresses, shown in FIG. 2 , through the plurality of write bit lines WBO 1 a , WBO 1 b , . . . , WBO 24 a , WBO 24 b for odd addresses. A read precharge circuit 43 for odd addresses, shown in FIG. 1 , is configured to precharge the high level voltage to each of the plurality of read bit lines RBO 1 a , RBO 1 b , . . . , RBO 24 a , RBO 24 b for odd addresses, shown in FIG. 2 . A read amplifier 51 for odd addresses, shown in FIG. 1 , is configured to read the odd addressed data from each of the plurality of memory cells M 101 -M 124 , M 301 -M 324 , M 501 -M 524 for odd addresses, shown in FIG. 2 , through the plurality of read bit lines RBO 1 a , RBO 1 b , . . . , RBO 24 a , RBO 24 b for odd addresses.

The memory cell M 001 for even address is the one read and one write SRAM cell. With reference to FIG. 3 , the memory cell M 001 for even address includes the write transistor WTr 1 a of which the drain region is electrically connected to the write bit line WBE 1 a for even addresses, a load element LTr 1 a of which drain region is electrically connected to a source region of the write transistor WTr 1 a , and a drive transistor DTr 1 a of which drain region is electrically connected to the source region of the write transistor WTr 1 a . The memory cell M 001 for even address further includes the write transistor WTr 1 b of which the drain region is electrically connected to the write bit line WBE 1 b for even addresses, a load element LTr 1 b of which drain region is electrically connected to a source region of the write transistor WTr 1 b , and a drive transistor DTr 1 b of which drain region is electrically connected to the source region of the write transistor WTr 1 b . Also, the memory cell M 001 for even address includes the read transistor RTr 1 a of which the drain region is electrically connected to the read bit line RBE 1 a for even addresses and a source region is electrically connected to the source region of the write transistor WTr 1 a , the read transistor RTr 1 b of which the drain region is electrically connected to the read bit line RBE 1 b for even addresses and a source region is electrically connected to the source region of the write transistor WTr 1 b . The write transistors WTr 1 a , WTr 1 b , the read transistors RTr 1 a , RTr 1 b , and the drive transistors DTr 1 a , DTr 1 b are nMOS transistors. The load elements LTr 1 a , LTr 1 b are pMOS transistors. Those of ordinary skilled in the art will appreciate that the drain and the source can be exchanged in each of the write transistors WTr 1 a , WTr 1 b.

Each source region of the load elements LTr 1 a , LTr 1 b is electrically connected to a high level voltage supply VDD. Each source region of the drive transistors DTr 1 a , DTr 1 b is electrically connected to a low level voltage supply VSS. A gate of the load element LTr 1 a and a gate of the drive transistor DTr 1 a are electrically connected to each other to serve as an input of CMOS inverter. Also, a gate of the load element LTr 1 b and a gate of the drive transistor DTr 1 b are electrically connected to each other to serve as the input of the CMOS inverter.

An output of the CMOS inverter having the load element LTr 1 a and the drive transistor DTr 1 a is electrically connected to the source region of the write transistors WTr 1 b and transmits a feedback signal to the input of the CMOS inverter having the load element LTr 1 b and the drive transistor DTr 1 b . Also, an output of the CMOS inverter having the load element LTr 1 b and the drive transistor DTr 1 b is electrically connected to the source region of the write transistor WTr 1 a and transmits the feedback signal to the input of the CMOS inverter having the load element LTr 1 a and the drive transistor DTr 1 a.

Each gate of the write transistors WTr 1 a , WTr 1 b is electrically connected to the write word line WW 0 for even addresses. Each gate of the read transistors RTr 1 a , RTr 1 b is electrically connected to the read word line RW 0 for even addresses. Each of the memory cells M 002 -M 024 , M 201 -M 224 , M 401 -M 424 for even addresses and the memory cells M 101 -M 124 , M 301 -M 324 , M 501 -M 524 for odd addresses is also the one read and one write SRAM cell and similar to FIG. 3 .

Next, first example of the write operation of the semiconductor memory, according to the first embodiment, shown in FIGS. 1-3 , is described. Here, the start row address for sequential data to be written in the semiconductor memory is “2”. The start column address for the sequential data to be written in the semiconductor memory is “10”. The end row address for the sequential data to be written in the semiconductor memory is “3”. The end column address for the sequential data to be written in the semiconductor memory is “9”. Therefore, the sequential data are written in the semiconductor memory over two rows.

The write amplifier 30 for even addresses, shown in FIG. 1 , supplies a high level voltage signal to the plurality of write bit lines WBE 10 a -WBE 24 a for even addresses, shown in FIG. 2 , and a low level voltage signal to another plurality of write bit lines WBE 10 b -WBE 24 b for even addresses. Further, the write decoder 60 for even addresses, shown in FIG. 1 , applies the high level voltage as the even address signal for the write operation to the write word line WW 2 for even addresses, shown in FIG. 2 . Consequently, the states of write transistors WTr 1 a , WTr 1 b , shown in FIG. 3 , within each of the plurality of memory cells M 201 -M 224 for even addresses go from an off state to an on state.

Since the write transistors WTr 1 a , WTr 1 b are in the on state, the high level voltage signal as the even addressed data associated with the row address “2” and the column address “10” is written in a node of the write transistor WTr 1 a within the memory cell M 210 for even address. The plurality of even addressed data associated with the row address “2” and corresponding column addresses are also written in the plurality of memory cells M 211 -M 224 for even addresses, respectively.

Further, the write amplifier 31 for odd addresses, shown in FIG. 1 , supplies the high level voltage signal to the plurality of write bit lines write bit lines WBO 1 a -WBO 9 a for odd addresses, shown in FIG. 2 , and the low level voltage signal to another plurality of write bit lines WBO 1 b -WBO 9 b for odd addresses. Further, the write decoder 61 for odd addresses, shown in FIG. 1 , applies the high level voltage as the odd address signal for the write operation to the write word line WW 3 for odd addresses, shown in FIG. 2 . Consequently, the states of write transistors WTr 1 a , WTr 1 b , shown in FIG. 3 , within the plurality of memory cells M 301 -M 324 for odd addresses go from the off state to the on state.

Since the write transistors WTr 1 a , WTr 1 b are in the on state, the odd addressed data associated with the row address “3” and the column address “1” is written in a node of the write transistors WTr 1 a within the memory cell M 301 for odd address. The plurality of odd addressed data associated with the row address “3” and corresponding column addresses are written in the plurality of memory cells M 302 -M 308 for odd address, respectively. Also, the odd addressed data associated with the end row address “3” and the end column address “9” is written in a node of the write transistor WTr 1 a within the memory cell M 309 for odd address and the write operation of the sequential data is completed.

Next, second example of the write operation of the semiconductor memory, according to the first embodiment, shown in FIGS. 1-3 , is described. Here, the start row address for sequential data to be written in the semiconductor memory is “1”. The start column address for the sequential data to be written in the semiconductor memory is “10”. The end row address for the sequential data to be written in the semiconductor memory is “2”. The end column address for the sequential data to be written in the semiconductor memory is “9”. Therefore, the sequential data are written in the semiconductor memory over two rows.

The write amplifier 31 for odd addresses, shown in FIG. 1 , supplies the high level voltage signal to the plurality of write bit lines WBO 10 a -WBO 24 a for odd addresses, shown in FIG. 2 , and the low level voltage signal to another plurality of write bit lines WBO 10 b -WBO 24 b for odd addresses. Further, the write decoder 61 for odd addresses, shown in FIG. 1 , applies the high level voltage as the odd address signal for the write operation to the write word line WW 1 for odd addresses, shown in FIG. 2 . Consequently, the states of write transistors WTr 1 a , WTr 1 b , shown in FIG. 3 , within each of the plurality of memory cells M 101 -M 124 for odd addresses go from an off state to an on state.

Since the write transistors WTr 1 a , WTr 1 b are in the on state, the odd addressed data associated with the row address “1” and the column address “10” is written in a node of the write transistor WTr 1 a within the memory cell M 110 for odd address. The plurality of odd addressed data associated with the row address “1” and corresponding column addresses are also written in the plurality of memory cells M 111 -M 124 for odd address, respectively.

Also, the write amplifier 30 for even addresses, shown in FIG. 1 , supplies the high level voltage signal to the plurality of write bit lines WBE 1 a -WBE 9 a for even addresses, shown in FIG. 2 , and the low level voltage signal to another plurality of write bit lines WBE 1 b -WBE 9 b for even addresses. Further, the write decoder 60 for even addresses, shown in FIG. 1 , applies the high level voltage as the even address signal for the write operation to the write word line WW 2 for even addresses, shown in FIG. 2 . Consequently, the states of write transistors WTr 1 a , WTr 1 b , shown in FIG. 3 , within the plurality of memory cells M 201 -M 224 for even addresses go from the off state to the on state.

Since the write transistors WTr 1 a , WTr 1 b are in the on state, the even addressed data associated with the row address “2” and the column address “1” is written in a node of the write transistor WTr 1 a within the memory cell M 201 for even address. The plurality of even addressed data associated with the row address “2” and corresponding column addresses are also written in the plurality of memory cells M 202 -M 208 for even addresses, respectively. Also, the even addressed data associated with the end row address “2” and the end column address “9” is written in a node of the write transistor WTr 1 a within the memory cell M 209 for even address and the write operation of the sequential data is completed.

Next, an example of the read operation of the semiconductor memory, according to the first embodiment, shown in FIGS. 1-3 , is described. Here, the start row address for sequential data to be read from the semiconductor memory is “2”. The start column address for the sequential data to be read from the semiconductor memory is “10”. The end row address for the sequential data to be read from the semiconductor memory is “3”. The end column address for the sequential data to be read from the semiconductor memory is “9”. Therefore, the sequential data are read from the semiconductor memory over two rows.

The read precharge circuit 42 for even addresses, shown in FIG. 1 , supplies the high level voltage to the plurality of read bit lines RBE 10 a -RBE 24 a for even addresses, shown in FIG. 2 . And the read decoder 62 for even addresses, shown in FIG. 1 , applies the high level voltage as the even address signal for the read operation to the read word line RW 2 for even addresses, shown in FIG. 2 . Consequently, the states of read transistors RTr 1 a , RTr 1 b , shown in FIG. 3 , within each of the plurality of memory cells M 201 -M 224 for even addresses go from the off state to the on state.

When the high level voltage signal corresponding to the even addressed data associated with the row address “2” and the column address “10” is stored in the node of the read transistor RTr 1 a within the memory cell M 210 for even address, the voltage on the read bit line RBE 10 a for even addresses remains high after the read transistor RTr 1 a goes from the off state to the on state. The read amplifier 50 for even addresses reads the even addressed data associated with the row address “2” and the column address “10” stored in the memory cell M 210 for even address, based on the voltage on the read bit line RBE 10 a for even addresses. Also, the read amplifier 50 for even addresses reads the even addressed data stored in each of the plurality of memory cells M 211 -M 224 for even addresses.

The read precharge circuit 43 for odd addresses, shown in FIG. 1 , precharges the high level voltage to the plurality of read bit lines RBO 1 a -RBO 9 a for odd addresses, shown in FIG. 2 . Further, the read decoder 63 for odd addresses, shown in FIG. 1 , applies the high level voltage as the odd address signal for the read operation to the read word line RW 3 for odd addresses, shown in FIG. 2 . Consequently, the states of read transistors RTr 1 a , RTr 1 b , shown in FIG. 3 , within each of the plurality of memory cells M 301 -M 324 for odd addresses go from the off state to the on state.

When the high level voltage signal corresponding to the odd addressed data associated with the row address “3” and the column address “1” is stored in the node of the read transistor RTr 1 a within the memory cell M 301 for odd address, the voltage on the read bit line RBO 1 a for odd addresses remains high after the read transistor RTr 1 a goes from the off state to the on state. The read amplifier 51 for odd addresses reads the odd addressed data associated with the row address “3” and the column address “1” stored in the memory cell M 301 for odd address, based on the voltage on the read bit line RBO 1 a for odd addresses. The read amplifier 51 for odd addresses also reads the odd addressed data stored in each of the plurality of memory cells M 302 -M 309 for odd addresses and the read operation of the sequential data is completed.

With reference next to FIG. 4 , a semiconductor memory, according to a comparative example, includes a memory array 120 . As shown in FIG. 5 , the memory array 120 includes a plurality of memory cells N 001 , . . . , N 009 , N 010 , . . . , N 024 configured to store data associated with the row address “0”. A plurality of memory cells N 101 , . . . , N 109 , N 110 , . . . , N 124 are configured to store data associated with the row address “1”. A plurality of memory cells N 201 , . . . , N 209 , N 210 , . . . , N 224 are configured to store data associated with the row address “2”. A plurality of memory cells N 301 , . . . , N 309 , N 310 , . . . , N 324 are configured to store data associated with the row address “3”. A plurality of memory cells N 401 , . . . , N 409 , N 410 , . . . , N 424 are configured to store data associated with the row address “4”. A plurality of memory cells N 501 , . . . , N 509 , N 510 , . . . , N 524 are configured to store data associated with the row address “5”.

The plurality of memory cells N 001 , . . . , N 009 , N 010 , . . . , N 024 are parallel with a row direction of the memory array 120 . The plurality of memory cells N 101 , . . . , N 109 , N 110 , . . . , N 124 are parallel with the plurality of memory cells N 001 , . . . , N 009 , N 010 , . . . , N 024 . The plurality of memory cells N 201 , . . . , N 209 , N 210 , . . . , N 224 are parallel with the plurality of memory cells N 101 , . . . , N 109 , N 110 , . . . , N 124 . The plurality of memory cells N 301 , . . . , N 309 , N 310 , . . . , N 324 are parallel with the plurality of memory cells N 201 , . . . , N 209 , N 210 , . . . , N 224 . The plurality of memory cells N 401 , . . . , N 409 , N 410 , . . . , N 424 are parallel with the plurality of memory cells N 301 , . . . , N 309 , N 310 , . . . , N 324 . The plurality of memory cells N 501 , . . . , N 509 , N 510 , . . . , N 524 are parallel with the plurality of memory cells N 401 , . . . , N 409 , N 410 , . . . , N 424 .

The memory array further includes a plurality of first write word lines WW 0 a , WW 1 a , WW 2 a , WW 3 a , WW 4 a , WW 5 a and a plurality of second write word lines WW 0 b , WW 1 b , WW 2 b , WW 3 b , WW 4 b , WW 5 b . The plurality of first write word lines WW 0 a -WW 5 a are configured to transfer a first address signal for the write operation to select the plurality of memory cells N 001 -N 024 , N 101 -N 124 , N 201 -N 224 , N 301 -N 324 , N 401 -N 424 , N 501 -N 524 , during the write operation. The plurality of second write word lines WW 0 b -WW 5 b are configured to transfer a second address signal for the write operation. The plurality of first write word lines WW 0 a , WW 1 a , WW 2 a , WW 3 a , WW 4 a , WW 5 a and the plurality of second write word lines WW 0 b , WW 1 b , WW 2 b , WW 3 b , WW 4 b , WW 5 b are parallel with the row direction of the memory array 120 .

Specifically, the first write word line WW 0 a is electrically connected to gates of a pair of first write transistors in each of the plurality of memory cells N 001 , . . . , N 009 , N 010 , . . . , N 024 , as described bellow. The second write word line WW 0 b is electrically connected to gates of a pair of second write transistors in each of the plurality of memory cells N 001 , . . . , N 009 , N 010 , . . . , N 024 , as described bellow. The first write word line WW 1 a is electrically connected to gates of a pair of first write transistors in each of the plurality of memory cells N 101 , . . . , N 109 , N 110 , . . . , N 124 . The second write word line WW 1 b is electrically connected to gates of a pair of second write transistors in each of the plurality of memory cells N 101 , . . . , N 109 , N 110 , . . . , N 124 The first write word line WW 2 a is electrically connected to gates of a pair of first write transistors in each of the plurality of memory cells N 201 , . . . , N 209 , N 210 , . . . , N 224 . The second write word line WW 2 b is electrically connected to gates of a pair of second write transistors in each of the plurality of memory cells N 201 , . . . , N 209 , N 210 , . . . , N 224 . The first write word line WW 3 a is electrically connected to gates of a pair of first transistors in each of the plurality of memory cells N 301 , . . . , N 309 , N 310 , . . . , N 324 . The second write word line WW 3 b is electrically connected to gates of a pair of second write transistors in each of the plurality of memory cells N 301 , . . . , N 309 , N 310 , . . . , N 324 . The first write word line WW 4 a is electrically connected to gates of a pair of first write transistors in each of the plurality of memory cells N 401 , . . . , N 409 , N 410 , . . . , N 424 . The second write word line WW 4 b is electrically connected to gates of a pair of second write transistors in each of the plurality of memory cells N 401 , . . . , N 409 , N 410 , . . . , N 424 . The first write word line WW 5 a is electrically connected to gates of a pair of first write transistors in each of the plurality of memory cells N 501 , . . . , N 509 , N 510 , . . . , N 524 The second write word line WW 5 b is electrically connected to gates of a pair of second write transistors in each of the plurality of memory cells N 501 , . . . , N 509 , N 510 , . . . , N 524 .

Also, the memory array 120 includes a plurality of read word lines RW 0 , RW 1 , RW 2 , RW 3 , RW 4 , RW 5 configured to transfer an address signal for the read operation to select the plurality of memory cells N 001 -N 024 , N 101 -N 124 , N 201 -N 224 , N 301 -N 324 , N 401 -N 424 , N 501 -N 524 , during the read operation. The plurality of read word lines RW 0 , RW 1 , RW 2 , RW 3 , RW 4 , RW 5 are parallel with the row direction of the memory array 120 . The read word line RW 0 is electrically connected to gates of a pair of read transistors in each of the plurality of memory cells N 001 , . . . , N 009 , N 010 , . . . , N 024 , as described below. The read word line RW 1 is electrically connected to gates of a pair of read transistors in each of the plurality of memory cells N 101 , . . . , N 109 , N 110 , . . . , N 124 . The read word line RW 2 is electrically connected to gates of a pair of read transistors in each of the plurality of memory cells N 201 , . . . , N 209 , N 210 , . . . , N 224 . The read word line RW 3 is electrically connected to gates of a pair of read transistors in each of the plurality of memory cells N 301 , . . . , N 309 , N 310 , . . . , N 324 . The read word line RW 4 is electrically connected to gates of a pair of read transistors in each of the plurality of memory cells N 401 , . . . , N 409 , N 410 , . . . , N 424 . The read word line RW 5 is electrically connected to gates of a pair of read transistors in each of the plurality of memory cells N 501 , . . . , N 509 , N 510 , . . . , N 524 .

The memory array 120 further includes a plurality of write bit lines WB 1 aa , WB 1 ab , . . . , WB 9 aa , WB 9 ab , WB 10 aa , WB 10 ab , . . . WB 24 aa , WB 24 ab configured to transfer the data to each of the plurality of memory cells N 001 -N 024 , N 101 -N 124 , N 201 -N 224 , N 301 -N 324 , N 401 -N 424 , N 501 -N 524 , during the write operation. The plurality of write bit lines WB 1 aa , WB 1 ab , . . . , WB 9 aa , WB 9 ab , WB 10 aa , WB 10 ab , . . . WB 24 aa , WB 24 ab are arranged parallel with a column direction of the memory array 120 . The pair of first write bit lines WB 1 aa , WB 1 ab is electrically connected to drain regions of the pair of first write transistors, respectively, in each of the plurality of memory cells N 001 , N 101 , N 201 , N 301 , N 401 , N 501 configured to store the data associated with the column address “1”. The pair of first bit lines WB 9 aa , WB 9 ab is electrically connected to drain regions of the pair of first write transistors, respectively, in each of the plurality of memory cells N 009 , N 109 , N 209 , N 309 , N 409 , N 509 configured to store the data associated with the column address “9”. The pair of first bit lines WB 10 aa , WB 10 ab is electrically connected to drain regions of the pair of first write transistors, respectively, in each of the plurality of memory cells N 010 , N 110 , N 210 , N 310 , N 410 , N 510 configured to store the data associated with the column address “10”. The pair of first bit lines WB 24 aa , WB 24 ab is electrically connected to drain regions of the pair of first write transistors, respectively, in each of the plurality of memory cells N 024 , N 124 , N 224 , N 324 , N 424 , N 524 configured to store the data associated with the column address “24”.

The memory array 120 further includes a plurality of second write bit lines WB 1 ba , WB 1 bb , . . . , WB 9 ba , WB 9 bb , WB 10 ba , WB 10 bb , . . . WB 24 ba , WB 24 bb configured to transfer the data to each of the plurality of memory cells N 001 -N 024 , N 101 -N 124 , N 201 -N 224 , N 301 -N 324 , N 401 -N 424 , N 501 -N 524 , during the write operation. The plurality of second write bit lines WB 1 ba , WB 1 bb , . . . , WB 9 ba , WB 9 bb , WB 10 ba , WB 10 bb , . . . WB 24 ba , WB 24 bb are arranged parallel with the column direction of the memory array 120 . The pair of second write bit lines WB 1 ba , WB 1 bb is electrically connected to drain regions of the pair of second write transistors, respectively, in each of the memory cells N 001 , N 101 , N 201 , N 301 , N 401 , N 501 configured to store the data associated with the column address “1” The pair of second write bit lines WB 9 ba , WB 9 bb is electrically connected to drain regions of the pair of second write transistors, respectively, in each of the memory cells N 009 , N 109 , N 209 , N 309 , N 409 , N 509 configured to store the data associated with the column address “9”. The pair of second write bit lines WB 10 ba, WB 10 bb is electrically connected to drain regions of the pair of second write transistors, respectively, in each of the memory cells N 010 , N 110 , N 210 , N 310 , N 410 , N 510 configured to store the data associated with the column address “10”. The pair of second write bit lines WB 24 ba , WB 24 bb is electrically connected to drain regions of the pair of second write transistors, respectively, in each of the memory cells N 024 , N 124 , N 224 , N 324 , N 424 , N 524 configured to store the data associated with the column address “24”.

The memory array 120 further includes a plurality of read bit lines RB 1 a , RB 1 b , . . . , RB 9 a , RB 9 b , RB 10 a , RB 10 b , . . . RB 1 a , RB 10 b configured to transfer the data to be read from the plurality of memory cells N 001 -N 024 , N 101 -N 124 , N 201 -N 224 , N 301 -N 324 , N 401 -N 424 , N 501 -N 524 , during the read operation. The plurality of read bit lines RB 1 a , RB 1 b , . . . , RB 9 a , RB 9 b , RB 10 a , RB 1 b , . . . RB 10 a , RB 10 b are parallel with the column direction of the memory array 120 . The pair of read bit lines RB 1 a , RB 1 b is electrically connected to drain regions of the pair of read transistors, respectively, in each of the plurality of memory cells N 001 , N 101 , N 201 , N 301 , N 401 , N 501 configured to store the data associated with the column address “1”. The pair of read bit lines RB 9 a , RB 9 b is electrically connected to drain regions of the pair of read transistors, respectively, in each of the plurality of memory cells N 009 , N 109 , N 209 , N 309 , N 409 , N 509 configured to store the data associated with the column address “9”. The pair of read bit lines RB 10 a , RB 10 b is electrically connected to drain regions of the pair of read transistors, respectively, in each of the plurality of memory cells N 010 , N 110 , N 210 , N 310 , N 410 , N 510 configured to store the data associated with the column address “10”. The pair of read bit lines RB 24 a , RB 24 b is electrically connected to drain regions of the pair of read transistors, respectively, in each of the plurality of memory cells N 024 , N 124 , N 224 , N 324 , N 424 , N 524 configured to store the data associated with the column address “24”.

The memory cell N 001 , shown in FIG. 5 , is the one read and two write SRAM cell. With reference to FIG. 6 , the memory cell N 001 includes the first write transistor WTr 1 aa of which the drain region is electrically connected to the first write bit line WB 1 aa , and another first write transistor WTr 1 ab of which the drain region is electrically connected to another first write bit line WB 1 ab . Each gate of the first write transistor WTr 1 aa , WTr 1 ab is electrically connected to the first write word line WW 0 a . Also, the memory cell N 001 includes the second write transistor WTr 1 ba of which the drain region is electrically connected to the second write bit line WB 1 ba , and another second write transistor WTr 1 bb of which the drain region is electrically connected to another second write bit line WB 1 bb . Each gate of the second write transistors WTr 1 ba , WTr 1 bb is electrically connected to the second write word line WW 0 b . Further, the memory cell N 001 includes the read transistor RTr 1 a of which the drain region is electrically connected to the read bit line RB 1 a , and another read transistor RTr 1 b of which the drain region is electrically connected to another read bit line RB 1 b . Each gate of the read transistors RTr 1 a , RTr 1 b is electrically connected to the read word line RW 0 .

The first write transistors WTr 1 aa , WTr 1 ab , the second write transistors WTr 1 ba , WTr 1 bb , and the read transistors RTr 1 a , RTr 1 b are nMOS transistors. The memory cell N 001 further includes CMOS inverters having load elements LTr 1 a , LTr 1 b and drive transistors DTr 1 a , DTr 1 b , respectively, similar to the memory cell M 001 for even address shown in FIG. 3 . Each of the plurality of memory cells N 009 -N 524 , shown in FIG. 5 is also the one read and two write SRAM cell and similar to FIG. 6 .

With reference to FIG. 4 , a first write decoder 160 is configured to transfer the first address signal for the write operation to each of the plurality of first write word lines WW 0 a -WW 5 a , shown in FIG. 5 , to select the row address for the data, when the data is written in each of the plurality of memory cells N 001 -N 024 , N 101 -N 124 , N 201 -N 224 , N 301 -N 324 , N 401 -N 424 , N 501 -N 524 . A second write decoder 161 , shown in FIG. 4 , is configured to transfer the second address signal for the write operation to each of the plurality of second write word lines WW 0 b -WW 5 b , shown in FIG. 5 , to select the row address for the data, when the data is written in the plurality of memory cells N 001 -N 024 , N 101 -N 124 , N 201 -N 224 , N 301 -N 324 , N 401 -N 424 , N 501 -N 524 . A read decoder 162 , shown in FIG. 4 , is configured to transfer the address signal for the read operation to each of the plurality of read word lines RW 0 -RW 5 , shown in FIG. 5 , to select the row address for the data, when the data is read from each of the plurality of memory cells N 001 -N 024 , N 101 -N 124 , N 201 -N 224 , N 301 -N 324 , N 401 -N 424 , N 501 -N 524 .

With reference to FIG. 4 , a first write precharge circuit 140 is configured to precharge the high level voltage to each of the plurality of first write bit lines WB 1 aa , WB 1 ab , . . . , WB 24 aa , WB 24 ab , shown in FIG. 5 . A second write precharge circuit 141 , shown in FIG. 4 , is configured to precharge the high level voltage to each of the plurality of second write bit lines WB 1 ba , WB 1 bb , . . . , WB 24 ba , WB 24 bb , shown in FIG. 5 . A first write amplifier 130 , shown in FIG. 4 , is configured to write the data to each of the plurality of memory cells N 001 -N 024 , N 101 -N 124 , N 201 -N 224 , N 301 -N 324 , N 401 -N 424 , N 501 -N 524 , shown in FIG. 5 , through the plurality of first write bit lines WB 1 aa , WB 1 ab , WB 24 aa , WB 24 ab . A second write amplifier 131 , shown in FIG. 4 , is configured to write the data to each of the plurality of memory cells N 001 -N 024 , N 101 -N 124 , N 201 -N 224 , N 301 -N 324 , N 401 -N 424 , N 501 -N 524 , shown in FIG. 5 , through the plurality of second write bit lines WB 1 ba , WB 1 bb , . . . , WB 24 ba , WB 24 bb . A read precharge circuit 142 , shown in FIG. 4 , is configured to precharge the high level voltage to each of the plurality of read bit lines RB 1 a , RB 1 b , . . . , RB 1 a , RB 10 b , shown in FIG. 5 . A read amplifier 150 , shown in FIG. 4 , is configured to read the data from each of the plurality of memory cells N 001 -N 024 , N 101 -N 124 , N 201 -N 224 , N 301 -N 324 , N 401 -N 424 , N 501 -N 524 , shown in FIG. 5 , through the plurality of read bit lines RB 1 a , RB 1 b , . . . , RB 10 a , RB 10 b.

Next, an example of the write operation of the semiconductor memory, according to the comparative example, shown in FIGS. 4-6 , is described. Here, the start row address for sequential data to be written in the semiconductor memory is “2”. The start column address for the sequential data to be written in the semiconductor memory is “10”. The end row address for the sequential data to be written in the semiconductor memory is “3”. The end column address for the sequential data to be written in the semiconductor memory is “9”. Therefore, the sequential data are written in the semiconductor memory, according to the comparative example, over two rows.

The first write amplifier 130 supplies the high level voltage signal to the plurality of first write bit lines WB 10 aa -WB 24 aa , shown in FIG. 5 , and the low level voltage signal to another plurality of first write bit lines WB 10 ab -WB 24 ab . Further, the second write amplifier 131 , shown in FIG. 4 , supplies the high level voltage signal to the plurality of second write bit lines WB 1 ba -WB 9 ba , shown in FIG. 5 , and the low level voltage signal to another plurality of second write bit lines WB 1 bb -WB 9 bb.

The first write decoder 160 , shown in FIG. 4 , applies the high level voltage to the first write word line WW 2 a , shown in FIG. 5 . Consequently, the states of first write transistors WTr 1 aa , WTr 1 ab , shown in FIG. 6 , within each of the plurality of memory cells N 201 -N 224 go from the off state to the on state. Therefore, the high level voltage signal as the data associated with the row address “2” and the column address “10” is written in a node of the first write transistor WTr 1 aa within the memory cell N 210 , shown in FIG. 5 . The plurality of data associated with the row address “2” and corresponding column addresses are also written in the plurality of memory cells N 211 -N 224 .

The second write decoder 161 , shown in FIG. 4 , applies the high level voltage to the second write word line WW 3 b , shown in FIG. 5 . Consequently, the states of second write transistors WTr 1 ba , WTr 1 bb , shown in FIG. 6 , within each of the plurality of memory cells N 301 -N 324 go from the off state to the on state. Therefore, the high level voltage signal as the data associated with the row address “3” and the column address “1” is written in a node of the first write transistor WTr 1 ba within the memory cell N 301 , shown in FIG. 5 . The plurality of data associated with the row address “3” and corresponding column addresses are also written in the plurality of memory cells N 302 -N 308 . Further, the data associated with the end row address “3” and the end column address “9” is written in a node of the second write transistor WTr 1 ba within the memory cell N 309 and the write operation of the semiconductor memory, according to the comparative example, is completed.

In the comparative example, shown in FIG. 5 , it is impossible to use the one read and one write SRAM cell for each of the plurality of memory cells N 001 -N 524 . For example, the plurality of memory cells N 001 , N 101 , N 201 , N 301 , N 401 , N 501 configured to store the data associated with the column address “1” own the bit line jointly. Therefore, if the one read and one write SRAM cell is applied to the semiconductor memory according to the comparative example, the data to be written in the memory cell N 301 is also written in the memory cell N 201 , unintentionally, in the above example of the write operation. Similar problems happen to the plurality of memory cells N 202 -N 209 .

However, the semiconductor memory, according to the first embodiment, shown in FIGS. 1-3 , writes the even addressed data associated with the even row addresses in the plurality of memory cells M 001 -M 024 , M 201 -M 224 , M 401 -M 424 for even addresses, through the plurality of write bit lines WBE 1 a , WBE 1 b , WBE 24 a , WBE 24 b for even addresses. Also, the semiconductor memory, according to the first embodiment, writes the odd addressed data associated with the odd row addresses in the plurality of memory cells M 101 -M 124 , M 301 -M 324 , M 501 -M 524 for odd addresses, through the plurality of write bit lines WBO 1 a , WBO 1 b , . . . , WBO 24 a , WBO 24 b that are independent from the plurality of write bit lines WBE 1 a , WBE 1 b , . . . , WBE 24 a , WBE 24 b for even addresses. Therefore, even though the semiconductor memory, according to the first embodiment, uses the plurality of one read and one write SRAM cells, the semiconductor memory writes the sequential data over the plurality of rows, correctly. Accordingly, unintentional writing operation as described above does not happen. Also, the semiconductor memory reads the sequential data over the plurality of rows, correctly.

Further, the area of the one read and one write SRAM cell is smaller than the area of the one read and two write SRAM cell, since the one read and one write SRAM cell includes fewer transistors than the one read and two write SRAM cell. Therefore, the first embodiment makes it possible to reduce the area of the semiconductor memory. Also, manufacturing the one read and one write SRAM cell is easier than manufacturing the one read and two write SRAM cell. Accordingly, the first embodiment makes it possible to increase the yield rate when the semiconductor memory is manufactured.

Second Embodiment

With reference to FIG. 7 , the semiconductor memory, according to the second embodiment, also includes the memory array 220 for even addresses and the memory array 221 for odd addresses. With reference to FIG. 8 , the memory array 220 for even addresses, according to the second embodiment, includes the plurality of memory cells M 001 -M 024 , M 201 -M 224 , M 401 -M 424 , M 601 -M 624 for even addresses arranged in an array of four rows and 24 columns. Each of the plurality of memory cells M 001 -M 024 , M 201 -M 224 , M 401 -M 424 , M 601 -M 624 is the one read and one write SRAM cell, as shown in FIG. 3 . As shown in FIG. 8 , the semiconductor memory, according to the second embodiment, has hierarchical bit line architecture. Specifically, the memory array 220 for even addresses includes a pair of global write bit lines WGE 1 a , WGE 1 b for even addresses. A local write amplifier WAE 1 a for even addresses is connected to the global write bit lines WGE 1 a , WGE 1 b for even addresses. A pair of local write bit lines WLE 1 aa , WLE 1 ab for even addresses is connected to the local write amplifier WAE 1 a for even addresses. The local write amplifier WAE 1 a for even addresses is configured to supply the voltage to each of the local write bit lines WLE 1 aa , WLE 1 ab , based on the voltage on the global write bit lines WGE 1 a , WGE 1 b for even addresses. The local write bit lines WLE 1 aa , WLE 1 ab for even addresses are connected to the write transistors WTr 1 a , WTr 1 b within the memory cells M 001 , M 201 for even addresses, respectively. Also, the local write bit lines WLE 1 aa , WLE 1 ab for even addresses are connected to a local write precharge circuit WPE 1 a for even addresses. The local write precharge circuit WPE 1 a for even addresses is configured to precharge the high level voltage to the local write bit lines WLE 1 aa , WLE 1 ab for even addresses.

Also, the memory array 220 for even addresses includes a pair of global read bit lines RGE 1 a , RGE 1 b for even addresses. A local read amplifier RAE 1 a for even addresses is connected to the global read bit lines RGE 1 a , RGE 1 b for even addresses. A pair of local read bit lines RLE 1 aa , RLE 1 ab for even addresses is connected to the local read amplifier RAE 1 a for even addresses. The local read bit lines RLE 1 aa , RLE 1 ab for even addresses are connected to the read transistors RTr 1 a , RTr 1 b in the memory cells M 001 , M 201 for even addresses, respectively. The local read amplifier RAE 1 a for even addresses is configured to supply the voltage to each of the global read bit lines RGE 1 a , RGE 1 b for even addresses, based on the voltage on the local read bit lines RLE 1 aa , RLE 1 ab for even addresses. A local read precharge circuit RPE 1 a is connected to the local read bit lines RLE 1 aa , RLE 1 ab for even addresses. The local read precharge circuit RPE 1 a is configured to precharge the high level voltage to each of the local read bit lines RLE 1 aa , RLE 1 ab for even addresses.

Further, a local write amplifier WAE 1 b for even addresses is connected to the global write bit liens WGE 1 a , WGE 1 b for even addresses. A pair of local write bit lines WLE 1 ba , WLE 1 bb for even addresses is connected to the local write amplifier WAE 1 b for even addresses. The local write amplifier WAE 1 b for even addresses is configured to supply the voltage to the local write bit lines WLE 1 ba , WLE 1 bb for even addresses, based on the voltage on the global write bit lines WGE 1 a , WGE 1 b for even addresses. The local write bit lines WLE 1 ba , WLE 1 bb for even addresses are connected to the write transistors WTr 1 a , WTr 1 b in the memory cells M 401 , M 601 for even addresses, respectively. Also, a local write precharge circuit WPE 1 b for even addresses is connected to the local write bit lines WLE 1 ba , WLE 1 bb for even addresses. The local write precharge circuit WPE 1 b for even addresses is configured to precharge the high level voltage to each of the local write bit lines WLE 1 ba , WLE 1 bb for even addresses.

Further, a local read amplifier RAE 1 b for even addresses is connected to the global read bit lines RGE 1 a , RGE 1 b for even addresses. A pair of local read bit lines RLE 1 ba , RLE 1 bb for even addresses is connected to the local read amplifier RAE 1 b for even addresses. The local read bit lines RLE 1 ba , RLE 1 bb for even addresses are connected to the read transistors RTr 1 a , RTr 1 b in the memory cells M 401 , M 601 for even addresses, respectively. The local read amplifier RAE 1 b for even addresses is configured to supply the voltage to the global read bit lines RGE 1 a , RGE 1 b for even addresses, based on the voltage on the local read bit lines RLE 1 ba , RLE 1 bb for even addresses. Also, a local read precharge circuit RPE 1 b for even addresses is connected to the local read bit lines RLE 1 ba , RLE 1 bb for even addresses. The local read precharge circuit RPE 1 b for even addresses is configured to precharge the high level voltage to each of the local read bit lines RLE 1 ba , RLE 1 bb for even addresses.

The memory array 220 for even addresses further includes a pair of global write bit lines WGE 9 a , WGE 9 b for even addresses. A local write amplifier WAE 9 a for even addresses is connected to the global write bit lines WGE 9 a , WGE 9 b . A pair of local write bit lines WLE 9 aa , WLE 9 ab for even addresses is connected to the local write amplifier WAE 9 a for even addresses. The local write amplifier WAE 9 a for even addresses is configured to supply the voltage to the local write bit lines WLE 9 aa , WLE 9 ab for even addresses, based on the voltage on the global write bit lines WGE 9 a , WGE 9 b for even addresses. The local write bit lines WLE 9 aa , WLE 9 ab for even addresses are connected to the write transistors WTr 1 a , WTr 1 b in the memory cells M 009 , M 209 for even addresses, respectively. Further, a local write precharge circuit WPE 9 a for even addresses is connected to the local write bit lines WLE 9 aa , WLE 9 ab for even addresses. The local write precharge circuit WPE 9 a for even addresses is configured to precharge the high voltage to each of the local write bit lines WLE 9 aa , WLE 9 ab for even addresses.

Also, a local read amplifier RAE 9 a for even addresses is connected to global read bit lines RGE 9 a , RGE 9 b for even addresses. A pair of local read bit lines RLE 9 aa , RLE 9 ab for even addresses is connected to the local read amplifier RAE 9 a for even addresses. The local read bit lines RLE 9 aa , RLE 9 ab for even addresses are connected to the read transistors RTr 1 a , RTr 1 b in the memory cells M 009 , M 209 , respectively. The local read amplifier RAE 9 a for even addresses is configured to supply the voltage to the global read bit lines RGE 9 a , RGE 9 b for even addresses, based on the voltage on the local read bit lines RLE 9 aa , RLE 9 ab for even addresses. Also, a local read precharge circuit RPE 9 a for even addresses is connected to the local read bit lines RLE 9 aa , RLE 9 ab for even addresses. The local read precharge circuit RPE 9 a for even addresses is configured to precharge the high level voltage to each of the local read bit lines RLE 9 aa , RLE 9 ab for even addresses.

Further, a local write amplifier WAE 9 b for even addresses is connected to the global write bit lines WGE 9 a , WGE 9 b for even addresses. A pair of local write bit lines WLE 9 ba , WLE 9 bb for even addresses is connected to the local write amplifier WAE 9 b for even addresses. The local write amplifier WAE 9 b for even addresses is configured to supply the voltage to each of the local write bit liens WLE 9 ba , WLE 9 bb for even addresses, based on the voltage on the global write bit lines WGE 9 a , WGE 9 b for even addresses. The local write bit lines WLE 9 ba , WLE 9 bb for even addresses are connected to the write transistors WTr 1 a , WTr 1 b in the memory cells M 409 , M 609 for even addresses, respectively. Also, a local write precharge circuit WPE 9 b is connected to the local write bit lines WLE 9 ba , WLE 9 bb for even addresses. The local write precharge circuit WPE 9 b is configured to precharge the high level voltage to each of the local write bit lines WLE 9 ba , WLE 9 bb for even addresses.

Further, a local read amplifier RAE 9 b for even addresses is connected to the global read bit lines RGE 9 a , RGE 9 b for even addresses. A pair of read bit lines RLE 9 ba , RLE 9 bb for even addresses is connected to the local read amplifier RAE 9 b for even addresses. The local read bit lines RLE 9 ba , RLE 9 bb for even addresses are connected to the read transistors RTr 1 a , RTr 1 b in the memory cells M 409 , M 609 for even addresses, respectively. The local read amplifier RAE 9 b for even addresses is configured to supply the voltage to each of the global read bit lines RGE 9 a , RGE 9 b for even addresses, based on the voltage on the local read bit lines RLE 9 ba , RLE 9 bb for even addresses. Also, a local read precharge circuit RPE 9 b for even addresses is connected to the local read bit lines RLE 9 ba , RLE 9 bb for even addresses. The local read precharge circuit RPE 9 b for even addresses is configured to precharge the high level voltage to each of the local read bit lines RLE 9 ba , RLE 9 bb for even addresses.

A local write amplifier WAE 24 a for even addresses is connected to global write bit lines WGE 24 a , WGE 24 b for even addresses. A pair of local write bit lines WLE 24 aa , WLE 24 ab for even addresses is connected to the local write amplifier WAE 24 a for even addresses. The local write amplifier WAE 24 a for even addresses is configured to supply the voltage to the local write bit lines WLE 24 aa , WLE 24 ab for even addresses, based on the voltage on the global write bit lines WGE 24 a , WGE 24 b for even addresses. The local write bit lines WLE 24 aa , WLE 24 ab for even addresses are connected to the write transistors WTr 1 a , WTr 1 b in the memory cells M 024 , M 224 for even addresses, respectively. Also, a local write precharge circuit WPE 24 a for even addresses is connected to the local write bit lines WLE 24 aa , WLE 24 ab for even addresses. The local write precharge circuit WPE 24 a for even addresses is configured to precharge the high level voltage to the local write bit lines WLE 24 aa , WLE 24 ab for even addresses.

Also, a local read amplifier RAE 24 a for even addresses is connected to global read bit lines RGE 24 a , RGE 24 b for even addresses. Apair of local read bit lines RLE 24 aa , RLE 24 ab for even addresses is connected to the local read amplifier RAE 24 a for even addresses. The local read bit lines RLE 24 aa , RLE 24 ab for even addresses are connected to the read transistors RTr 1 a , RTr 1 b in the memory cells M 024 , M 224 for even addresses, respectively. The local read amplifier RAE 24 a for even addresses is configured to supply the voltage to the global read bit lines RGE 24 a , RGE 24 b for even addresses, based on the voltage on the local read bit lines RLE 24 aa , RLE 24 ab for even addresses. Also, a local read precharge circuit RPE 24 a for even addresses is connected to the local read bit lines RLE 24 aa , RLE 24 ab for even addresses. The local read precharge circuit RPE 24 a for even addresses is configured to precharge the high level voltage to the local read bit lines RLE 24 aa , RLE 24 ab for even addresses.

Further, a local write amplifier WAE 24 b for even addresses is connected to the global write bit lines WGE 24 a , WGE 24 b for even addresses. A pair of local write bit lines WLE 24 ba , WLE 24 bb for even addresses is connected to the local write amplifier WAE 24 b for even addresses. The local write amplifier WAE 24 b for even addresses is configured to supply the voltage to each of the local write bit lines WLE 24 ba , WLE 24 bb for even addresses, based on the voltage on the global write bit lines WGE 24 a , WGE 24 b for even addresses. The local write bit lines WLE 24 ba , WLE 24 bb for even addresses are connected to the write transistors WTr 1 a , WTr 1 b in the memory cells M 424 , M 624 , respectively. Also, a local write precharge circuit WPE 24 b for even addresses is connected to the local write bit lines WLE 24 ba , WLE 24 bb for even addresses. The local write precharge circuit WPE 24 b for even addresses is configured to precharge the high level voltage to each of the local write bit lines WLE 24 ba , WLE 24 bb for even addresses.

Further, a local read amplifier RAE 24 b for even addresses is connected to the global read bit lines RGE 24 a , RGE 24 b for even addresses. A pair of read bit lines RLE 24 ba , RLE 24 bb for even addresses is connected to the local read amplifier RAE 24 b for even addresses. The local read bit lines RLE 24 ba , RLE 24 bb for even addresses are connected to the read transistors RTr 1 a , RTr 1 b in the memory cells M 424 , M 624 for even addresses, respectively. The local read amplifier RAE 24 b for even addresses is configured to supply the voltage to each of the global read bit lines RGE 24 a , RGE 24 b for even addresses, based on the voltage on the local read bit lines RLE 24 ba , RLE 24 bb for even addresses. Also, a local read precharge circuit RPE 24 b for even addresses is connected to the local read bit lines RLE 24 ba , RLE 24 bb for even addresses. The local read precharge circuit RPE 24 b for even addresses is configured to precharge the high level voltage to the local read bit lines RLE 24 ba , RLE 24 bb for even addresses.

With reference again to FIG. 7 , a global write precharge circuit 240 for even addresses is configured to precharge the high level voltage to each of the plurality of global write bit lines WGE 1 a , WGE 1 b , . . . , WGE 24 a , WGE 24 b for even addresses, shown in FIG. 8 . A global write amplifier 230 for even addresses, shown in FIG. 7 , is configured to write the even addressed data to each of the plurality of memory cells M 001 -M 024 , M 201 -M 224 , M 401 -M 424 , M 601 -M 624 for even addresses, shown in FIG. 8 , through each of the plurality of global write bit lines WGE 1 a , WGE 1 b , WGE 24 a , WGE 24 b for even addresses. A global read precharge circuit 242 for even addresses, shown in FIG. 7 , is configured to precharge the high level voltage to each of the plurality of global read bit lines RGE 1 a , RGE 1 b , . . . , RGE 24 a , RGE 24 b for even addresses, shown in FIG. 8 . A global read amplifier 250 for even addresses, shown in FIG. 7 , is configured to read the even addressed data from each of the plurality of memory cells M 001 -M 024 M 201 -M 224 , M 401 -M 424 , M 601 -M 624 for even addresses, through each of the plurality of global read bit lines RGE 1 a , RGE 1 b , . . . , RGE 24 a , RGE 24 b for even addresses, shown in FIG. 8 .

With reference next to FIG. 9 , the memory array 221 for odd addresses, according to the second embodiment, includes the plurality of memory cells M 101 -M 124 , M 301 -M 324 , M 501 -M 524 , M 701 -M 724 for odd addresses arranged in the array of four rows and 24 columns. Each of the plurality of memory cells M 101 -M 124 , M 301 -M 324 , M 501 -M 524 , M 701 -M 724 for odd addresses is the one read and one write SRAM cell, shown in FIG. 3 . As shown in FIG. 9 , the memory array 221 for odd addresses includes a pair of global write bit lines WGO 1 a , WGO 1 b for odd addresses. A local write amplifier WAO 1 a for odd addresses is connected to the global write bit lines WGO 1 a , WGO 1 b for odd addresses. A pair of local write bit lines WLO 1 aa , WLO 1 ab for odd addresses is connected to the local write amplifier WAO 1 a for odd addresses. The local write amplifier WAO 1 a for odd addresses is configured to supply the voltage to each of the local write bit lines WLO 1 aa , WLO 1 ab for odd addresses, based on the voltage on the global write bit lines WGO 1 a , WGO 1 b for odd addresses. The local write bit lines WLO 1 aa , WLO 1 ab for odd addresses are connected to the write transistors WTr 1 a , WTr 1 b in the memory cells M 101 , M 301 for odd addresses, respectively Also, a local write precharge circuit WPO 1 a for odd addresses is connected to the local write bit lines WLO 1 aa , WLO 1 ab for odd addresses. The local write precharge circuit WPO 1 a for odd addresses is configured to precharge the high level voltage to each of the local write bit lines WLO 1 aa , WLO 1 ab for odd addresses.

Also, a local read amplifier RAO 1 a for odd addresses is connected to global read bit lines RGO 1 a , RGO 1 a for odd addresses. A pair of local read bit lines RLO 1 aa , RLO 1 ab for odd addresses is connected to the local read amplifier RAO 1 a for odd addresses. The local read bit lines RLO 1 aa , RLO 1 ab for odd addresses are connected to the read transistors RTr 1 a , RTr 1 b in the memory cells M 101 , M 301 for odd addresses, respectively. The local read amplifier RAO 1 a for odd addresses is configured to supply the voltage to each of the global read bit lines RGO 1 a , RGO 1 b for odd addresses, based on the voltage on the local read bit lines RLO 1 aa , RLO 1 ab for odd addresses. Also, a local read precharge circuit RPO 1 a for odd addresses is connected to the local read bit lines RLO 1 aa , RLO 1 ab for odd addresses. The local read precharge circuit RPO 1 a for odd addresses is configured to precharge the high level voltage to each of the local read bit lines RLO 1 aa , RLO 1 ab for odd addresses.

Further, a local write amplifier WAO 1 b for odd addresses is connected to the global write bit lines WGO 1 a , WGO 1 b for odd addresses. A pair of local write bit lines WLO 1 ba , WLO 1 bb for odd addresses is connected to the local write amplifier WAO 1 b for odd addresses. The local write amplifier WAO 1 b for odd addresses is configured to supply the voltage to each of the local write bit lines WLO 1 ba , WLO 1 bb for odd addresses, based on the voltage on the global write bit lines WGO 1 a , WGO 1 b for odd addresses. The local write bit lines WLO 1 ba , WLO 1 bb for odd addresses is connected to the write transistors WTr 1 a , WTr 1 b in the memory cells M 501 , M 701 for odd addresses, respectively. Also, a local write precharge circuit WPO 1 b for odd addresses is connected to the local write bit lines WLO 1 ba , WLO 1 bb for odd addresses. The local write precharge circuit WPO 1 b for odd addresses is configured to precharge the high level voltage to each of the local write bit lines WLO 1 ba , WLO 1 bb for odd addresses.

Further, a local read amplifier RAO 1 b for odd addresses is connected to the global read bit lines RGO 1 a , RGO 1 b for odd addresses. A pair of local read bit lines RLO 1 ba , RLO 1 bb for odd addresses is connected to the local read amplifier RAO 1 b for odd addresses. The local read bit lines RLO 1 ba , RLO 1 bb for odd addresses are connected to the read transistors RTr 1 a , RTr 1 b in the memory cells M 501 , M 701 for odd addresses, respectively. The local read amplifier RAO 1 b for odd addresses is configured to supply the voltage to each of the global read bit lines RGO 1 a , RGO 1 b for odd addresses, based on the voltage on the local read bit lines RLO 1 ba , RLO 1 bb for odd addresses. Also, a local read precharge circuit RPO 1 b for odd addresses is connected to the local read bit lines RLO 1 ba , RLO 1 bb for odd addresses. The local read precharge circuit RPO 1 b for odd addresses is configured to precharge the high level voltage to each of the local read bit lines RLO 1 ba , RLO 1 bb for odd addresses.

A local write amplifier WAO 10 a for odd addresses is connected to global write bit lines WGO 10 a , WGO 10 b for odd addresses. A pair of local write bit lines WLO 10 aa , WLO 10 ab for odd addresses is connected to the local write amplifier WAO 10 a for odd addresses. The local write amplifier WAO 10 a for odd addresses is configured to supply the voltage to each of the local write bit lines WLO 10 aa , WLO 10 ab for odd addresses, based on the voltage on the global write bit lines WGO 10 a , WGO 10 b for odd addresses. The local write bit lines WLO 10 aa , WLO 10 ab for odd addresses are connected to the write transistors WTr 1 a , WTr 1 b in the memory cells M 110 , M 310 for odd addresses, respectively. Also, a local write precharge circuit WPO 10 a for odd addresses is connected to the local write bit lines WLO 10 aa , WLO 10 ab for odd addresses. The local write precharge circuit WPO 10 a for odd addresses is configured to precharge the high level voltage to each of the local write bit lines WLO 10 aa , WLO 10 ab for odd addresses.

Also, a local read amplifier RAO 10 a for odd addresses is connected to the global read bit lines RGO 10 a , RGO 10 b for odd addresses. A pair of local read bit lines RLO 10 aa , RLO 10 ab for odd addresses is connected to the local read amplifier RAO 10 a for odd addresses. The local read bit lines RLO 10 aa , RLO 10 ab for odd addresses are connected to the read transistors RTr 1 a , RTr 1 b in the memory cells M 110 , M 310 for odd addresses, respectively. The local read amplifier RAO 10 a for odd addresses is configured to supply the voltage to each of the global read bit lines RGO 10 a , RGO 10 b for odd addresses, based on the voltage on the local read bit lines RLO 10 aa , RLO 10 ab for odd addresses Also, a local read precharge circuit RPO 10 a for odd addresses is connected to the local read bit lines RLO 10 aa , RLO 10 ab for odd addresses. The local read precharge circuit RPO 10 a for odd addresses is configured to precharge the high level voltage to each of the local read bit lines RLO 10 aa , RLO 10 ab for odd addresses.

Further, a local write amplifier WAO 10 b for odd addresses is connected to the global write bit lines WGO 10 a , WGO 10 b for odd addresses. A pair of write bit lines WLO 10 ba , WL 010 bb for odd addresses is connected to the local write amplifier WAO 10 b for odd addresses. The local write amplifier WAO 10 b for odd addresses is configured to supply the voltage to each of the local write bit lines WLO 10 ba , WLO 10 bb for odd addresses, based on the voltage on the global write bit lines WGO 10 a , WGO 10 b for odd addresses. The local write bit lines WLO 10 ba , WLO 10 bb for odd addresses are connected to the write transistors WTr 1 a , WTr 1 b in the memory cells M 510 , M 710 for odd addresses. Also, a local write precharge circuit WPO 10 b for odd addresses is connected to the local write bit lines WLO 10 ba , WLO 10 bb for odd addresses. The local write precharge circuit WPO 10 b for odd addresses is configured to precharge the high level voltage to each of the local write bit lines WL 010 ba , WLO 10 bb for odd addresses.

Further, a local read amplifier RAO 10 b for odd addresses is connected to the global read bit lines RGO 10 a , RGO 10 b for odd addresses. A pair of local read bit lines RLO 10 ba , RLO 1 bb for odd addresses is connected to the local read amplifier RA 010 b for odd addresses. The local read bit lines RLO 10 ba , RLO 10 bb for odd addresses are connected to the read transistors RTr 1 a , RTr 1 b in the memory cells M 510 , M 710 for odd addresses. The local read amplifier RAO 10 b for odd addresses is configured to supply the voltage to the global read bit lines RGO 10 a , RGO 10 b , based on the voltage on the local read bit lines RLO 10 ba , RLO 10 bb for odd addresses. Also, a local read precharge circuit RPO 10 b for odd addresses is connected to the local read bit lines RLO 10 ba , RLO 10 bb for odd addresses. The local read precharge circuit RPO 10 b for odd addresses is configured to precharge the high level voltage to each of the local read bit lines RLO 10 ba , RLO 10 bb for odd addresses.

A local write amplifier WAO 24 a for odd addresses is connected to global write bit lines WGO 24 a , WGO 24 b for odd addresses. A pair of local write bit lines WLO 24 aa , WLO 24 ab for odd addresses is connected to the local write amplifier WA 024 a for odd addresses. The local write amplifier WAO 24 a for odd addresses is configured to supply the voltage to the local write bit lines WLO 24 aa , WLO 24 ab for odd addresses, based on the voltage on the global write bit lines WGO 24 a , WGO 24 b for odd addresses. The local write bit lines WLO 24 aa , WLO 24 ab for odd addresses are connected to the write transistors WTr 1 a , WTr 1 b in the memory cells M 124 , M 324 for odd addresses. Also, a local write precharge circuit WPO 24 a for odd addresses is connected to the local write bit lines WLO 24 aa , WLO 24 ab for odd addresses. The local write precharge circuit WPO 24 a for odd addresses is configured to precharge the high level voltage to each of the local write bit liens WLO 24 aa , WLO 24 ab for odd addresses.

Further, a local read amplifier RAO 24 a for odd addresses is connected to global read bit lines RGO 24 a , RGO 24 b for odd addresses. A pair of local read bit lines RLO 24 aa , RLO 24 ab for odd addresses is connected to the local read amplifier RAO 24 a for odd addresses. The local read bit lines RLO 24 aa , RLO 24 ab for odd addresses are connected to the read transistors RTr 1 a , RTr 1 b in the memory cells M 124 , M 324 for odd addresses. The local read amplifier RAO 24 a for odd addresses is configured to supply the voltage to each of the global read bit lines RGO 24 a , RGO 24 b for odd addresses, based on the voltage on the local read bit lines RLO 24 aa , RLO 24 ab for odd addresses. Also, a local read precharge circuit RPO 24 a for odd addresses is connected to the local read bit lines RLO 24 aa , RLO 24 ab for odd addresses. The local read precharge circuit RPO 24 a for odd addresses is configured to precharge the high level voltage to each of the local read bit lines RLO 24 aa , RLO 24 ab for odd addresses.

Further, a local write amplifier WAO 24 b for odd addresses is connected to the global write bit lines WGO 24 a , WGO 24 b for odd addresses. A pair of local write bit lines WLO 24 ba , WLO 24 bb for odd addresses is connected to the local write amplifier WAO 24 b for odd addresses. The local write amplifier WAO 24 b for odd addresses is configured to supply the voltage to each of the local write bit lines WLO 24 ba , WLO 24 bb for odd addresses, based on the voltage on the global write bit lines WGO 24 a , WGO 24 b for odd addresses. The local write bit lines WLO 24 ba , WLO 24 bb for odd addresses are connected to the write transistors WTr 1 a , WTr 1 b in the memory cells M 524 , M 724 for odd addresses, respectively. Also, a local write precharge circuit WPO 24 b for odd addresses is connected to the local write bit lines WLO 24 ba , WLO 24 bb for odd addresses. The local write precharge circuit WPO 24 b for odd addresses is configured to precharge the high level voltage to each of the local write bit lines WLO 24 ba , WLO 24 bb for odd addresses.

Further, a local read amplifier RAO 24 b for odd addresses is connected to the global read bit lines RGO 24 a , RGO 24 b for odd addresses. A pair of local read bit lines RLO 24 ba , RLO 24 bb for odd addresses is connected to the local read amplifier RAO 24 b for odd addresses. The local read bit lines RLO 24 ba , RLO 24 bb for odd addresses are connected to the read transistors RTr 1 a , RTr 1 b in the memory cells M 524 , M 724 for odd addresses, respectively. The local read amplifier RAO 24 b for odd addresses is configured to supply the voltage to the global read bit lines RGO 24 a , RGO 24 b for odd addresses, based on the voltage on the local read bit lines RLO 24 ba , RLO 24 bb for odd addresses. Also, a local read precharge circuit RPO 24 b for odd addresses is connected to the local read bit lines RLO 24 ba , RLO 24 bb for odd addresses. The local read precharge circuit RPO 24 b for odd addresses is configured to precharge the high level voltage to each of the local read bit lines RLO 24 ba , RLO 24 bb for odd addresses.

With reference again to FIG. 7 , a global write precharge circuit 241 for odd addresses is configured to precharge the high level voltage to each of the plurality of global write bit lines WGO 1 b , . . . , WGO 24 a , WGO 24 b for odd addresses, shown in FIG. 9 . A global write amplifier 231 for odd addresses, shown in FIG. 7 , is configured to write the odd addresses data to each of the plurality of memory cells M 101 -M 124 , M 301 -M 324 , M 501 -M 524 , M 701 -M 724 for odd addresses, shown in FIG. 9 , through each of the global write bit lines WGO 1 a , WGO 1 b , . . . , WGO 24 a , WGO 24 b for odd addresses. A global read precharge circuit 243 for odd addresses, shown in FIG. 7 , is configured to precharge the high level voltage to each of the plurality of global read bit lines RGO 1 a , RGO 1 b , . . . , RGO 24 a , RGO 24 b for odd addresses, shown in FIG. 9 . A global read amplifier 251 for odd addresses, shown in FIG. 7 , is configured to read the odd addressed data from each of the plurality of memory cells M 101 -M 124 , M 301 -M 324 , M 501 -M 524 , M 701 -M 724 for odd addresses, shown in FIG. 9 , through each of the plurality of global read bit lines RGO 1 a , RGO 1 b , . . . , RGO 24 a , RGO 24 b for odd addresses.

Next, an example of the write operation of the semiconductor memory, according to the second embodiment, shown in FIGS. 7-9 , is described. Here, the start row address for sequential data to be written in the semiconductor memory is “1”. The start column address for sequential data to be written in the semiconductor memory is “10”. The end row address for sequential data to be written in the semiconductor memory is “2”. The end column address for sequential data to be written in the semiconductor memory is “9”. Therefore, the sequential data are written in the semiconductor memory over two rows.

The global write amplifier 231 for odd addresses, shown in FIG. 7 , supplies the high level voltage to each of the global write bit lines WGO 10 a -WGO 24 a for odd addresses, shown in FIG. 9 . The plurality of local write amplifiers WAO 10 a -WAO 24 a for odd addresses supply the high level voltage signals to the plurality of local write bit lines WLO 10 aa -WLO 24 aa for odd addresses, based on changes of the voltages on the plurality of global write bit lines WGO 10 a -WGO 24 a for odd addresses, respectively.

Also, the global write amplifier 231 for odd addresses, shown in FIG. 7 , supplies the low level voltage signal to another plurality of global write bit lines WGO 10 b -WGO 24 b for odd addresses, shown in FIG. 9 . The plurality of local write amplifiers WAO 10 a -WAO 24 a supply the low level voltage signals to another plurality of local write bit lines WLO 10 ab -WLO 24 ab for odd addresses, based on the changes of the voltages on the plurality of global write bit lines WGO 10 b -WGO 24 b for odd addresses, respectively.

The write decoder 61 for odd addresses, shown in FIG. 7 , supplies the high level voltage as the odd address signal for the write operation to the write word line WW 1 for odd addresses, shown in FIG. 9 . Consequently, the states of write transistors WTr 1 a , WTr 1 b , shown in FIG. 3 , within each of the plurality of memory cells M 101 -M 124 for odd addresses go from the off state to the on state. Therefore, the odd addressed data associated with the row address “1” and the column address “10” is written in the node of the write transistor WTr 1 a within the memory cell M 110 for odd address, shown in FIG. 9 . Also, the plurality of odd addressed data associated with the row address “1” and corresponding column addresses are written in the plurality of memory cells M 111 -M 124 for odd address, respectively.

The global write amplifier 230 for even addresses, shown in FIG. 7 , supplies the high level voltage signals to the plurality of global write bit lines WGE 1 a -WGE 9 a for even addresses, shown in FIG. 8 . The plurality of local write amplifiers WAE 1 a -WAE 9 a for even addresses supply the high level voltage signals to the plurality of local write bit lines WLE 1 aa -WLE 9 aa for even addresses, based on the changes of the voltages on the plurality of global write bit lines WGE 1 a -WGE 9 a for even addresses, respectively.

Also, the global write amplifier 230 for even addresses, shown in FIG. 7 , supplies the low level voltage signal to another plurality of global write bit lines WGE 1 b -WGE 9 b for even addresses, shown in FIG. 8 . The plurality of local write amplifiers WAE 1 a -WAE 9 a for even addresses supply the low level voltage signals to another plurality of local write bit lines WLE 1 ab -WLE 9 ab for even addresses, based on the changes of the voltages on the plurality of global write bit lines WGE 1 b -WGE 9 b for even addresses.

The write decoder 60 for even addresses, shown in FIG. 7 , applies the high level voltage as the even address signal for the write operation to the write word line WW 2 for even addresses, shown in FIG. 8 . Consequently, the states of write transistors WTr 1 a , WTr 1 b , shown in FIG. 3 , within each of the plurality of memory cells M 201 -M 224 for even addresses go from the off state to the on state. Therefore, the even addressed data associated with the row address “2” and the column address “1” is written in the node of the write transistor WTr 1 a within the memory cell M 201 for even address, shown in FIG. 8 . The plurality of even addressed data associated with the row address “2” and corresponding column addresses are also written in the plurality of memory cells M 202 -M 209 for even addresses, respectively, and the write operation of the sequential data is completed.

Next, an example of the read operation of the semiconductor memory, according to the second embodiment, shown in FIGS. 7-9 , is described. Here, the start row address for the sequential data to be read from the semiconductor memory is “1”. The start column address for the sequential data to be read from the semiconductor memory is “10”. And the end row address for the sequential data to be read from the semiconductor memory is “2”. The end column address for the sequential data to be read from the semiconductor memory is “9”. Therefore, the sequential data are read from the semiconductor memory over two rows.

The global read precharge circuit 243 for odd addresses precharges the high level voltage to the plurality of global read bit lines RGO 10 a -RGO 24 a , shown in FIG. 9 . The plurality of local read precharge circuits RPO 10 a -RPO 24 a for odd addresses precharge the high level voltages to the plurality of local read bit lines RLO 10 aa -RL 024 aa , based on the changes of the voltages on the plurality of global read bit lines RGO 10 a -RGO 24 a for odd addresses.

The read decoder 63 for odd addresses, shown in FIG. 7 , supplies the high level voltage as the odd address signal for the read operation to the read word line RW 1 for odd addresses, shown in FIG. 9 . Consequently, the states of read transistors RTr 1 a , RTr 1 b , shown in FIG. 3 , within each of the plurality of memory cells M 110 -M 124 for odd addresses go from the off state to the on state.

When the high level voltage signal corresponding to the odd addressed data associated with the row address “1” and the column address “10” is stored in the node of the read transistor RTr 1 a within the memory cell M 110 for odd address, the voltage on the local read bit line RLO 10 aa for odd addresses remains high after the read transistor RTr 1 a goes from the off state to the on state.

The local read amplifier RAO 10 a for odd addresses amplifies the high level voltage signal transmitted by the local read bit lines RLO 10 aa for odd addresses. The local read amplifier RAO 10 a for odd addresses transfers the amplified high level voltage signal to the global read bit line RGO 10 a for odd addresses. The global read amplifier 251 for odd addresses, shown in FIG. 7 , reads the odd addressed data associated with the row address “1” and the column address “10” stored in the memory cell M 110 for odd address, based on the voltage on the global read bit line RGO 10 a for odd addresses. Also, the global read amplifier 251 for odd addresses reads the odd addressed data stored in each of the plurality of memory cells M 110 -M 124 for odd addresses.

Also, the global read precharge circuit 242 for even addresses precharges the high level voltage to the plurality of read bit lines RGE 1 a -RGE 9 a for even addresses, shown in FIG. 8 . The plurality of local read precharge circuits RPE 1 a -RPE 9 a for even addresses precharge the high level voltages to the plurality of local read bit lines RLE 1 aa -RLE 9 aa for even addresses, based on the changes of the voltages on the plurality of global read bit lines RGE 1 a -RGE 9 a for even addresses.

The read decoder 62 for even addresses, shown in FIG. 7 , supplies the high level voltage as the even address signal for the read operation to the read word line RW 2 for even addresses, shown in FIG. 8 . Consequently, the states of read transistor RTr 1 a , RTr 1 b , shown in FIG. 3 , within each of the plurality of memory cells M 201 -M 209 for even addresses go from the off state to the on state.

When the high level voltage signal corresponding to the even addressed data associated with the row address “2” and the column address “1” is stored in the node of the read transistor RTr 1 a within the memory cell M 201 for even address, shown in FIG. 8 , the voltage on the local read bit line RLE 1 aa for even addresses remains high after the read transistor RTr 1 a goes from the off state to the on state.

The local read amplifier RAE 1 a for even addresses amplifies the high level voltage signal transmitted by the local read bit lines RLE 1 aa for even addresses. The local read amplifier RAE 1 a for even addresses transfers the amplified high level voltage signal to the global read bit line RGE 1 a for even addresses. The global read amplifier 250 for even addresses, shown in FIG. 7 , reads the even addressed data associated with the row address “2” and the column address “1” stored in the memory cell M 201 for even address, based on the voltage on the global read bit line RGE 1 a for even addresses The global read amplifier 250 for even addresses also reads the even addressed data stored in each of the plurality of memory cells M 202 -M 209 for even addresses, and the read operation of the sequential data is completed.

As described above, the semiconductor memory having the hierarchical bit line architecture makes it possible to write and read the sequential data over the plurality of rows, correctly, even though the semiconductor memory uses the plurality of one read and one write SRAM cells.

Other Embodiments

Although the invention has been described above by reference to the embodiments of the present invention, the present invention is not limited to the embodiments described above. Modifications and variations of the embodiments described above will occur to those skilled in the art, in the light of the above teachings. For example, in FIG. 1 , the memory array 20 for even addresses is next to the memory array 21 for odd addresses. However, the memory array 20 for even addresses and the memory array 21 for odd addresses are connected to the independent read amplifiers and the independent write amplifiers, respectively. Therefore, there is no need to dispose the memory array 20 for even addresses next to the memory array 21 for odd addresses. Disposing the memory array 20 for even addresses apart from the memory array 21 for odd addresses is an alternative. Also, disposing the memory array 220 for even addresses, shown in FIG. 7 , apart form the memory array 221 for odd addresses is the alternative. As described above, the present invention includes many variations of the embodiments. Therefore, the scope of the invention is defined with reference to the following claims.