LexDanaLexDanabeta
Inventor

Yukihiro Fujimoto

Inventor
Yokohama, JP

Overview

30→
Patents
1995–2017
Patent span
Physics
Primary field (CPC G)

Patents· 30 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores47%
H03KPulse technique11%
H10DInorganic electric semiconductor devices11%
G06FElectric digital data processing9%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses6%
H10BElectronic memory devices4%
G01RMeasuring electric variables2%
H01LSemiconductor devices2%
H03DDemodulation or transference of modulation from one carrier to another2%
H04JMultiplex communication2%
PatentTitleYear
9,607,686'Semiconductor memory device'20178,340,520'Optical network unit'20128,154,943'Semiconductor integrated circuit'20127,924,605'Semiconductor memory device'20117,478,358'Semiconductor integrated circuit device'20097,423,926'Semiconductor memory'20087,417,890'Semiconductor memory device'20087,304,884'Semiconductor memory device'20077,158,428'Semiconductor memory device having hierarchical bit line structure'20077,116,574'Semiconductor memory device'20067,095,673'Semiconductor memory device capable of operating at high speed'20066,876,560'Content addressable memory and memory system'20056,856,555'Leak immune semiconductor memory'20056,661,731'Semiconductor memory, semiconductor integrated circuit and semiconductor mounted device'20036,570,792'Bus driving circuit and memory device having same'20036,567,326'Semiconductor memory device'20036,515,887'Semiconductor memory device'20036,449,196'Bus driving circuit and memory device having same'20026,429,687'Semiconductor integrated circuit device'20026,301,160'Bus driving circuit and memory device having same'20016,145,055'Cache memory having flags for inhibiting rewrite of replacement algorithm area corresponding to fault cell and information processing system having such a cache memory'20006,107,837'Address decoding circuit'20006,097,209'Erroneous operation protection circuit formed between data buses and intergrated circuit employing the same'20005,986,309'Semiconductor integrated circuit apparatus having a plurality of well bias voltage supply circuits'19995,982,675'Cache memory and microprocessor having the same'19995,717,353'Clock signal generating circuit'19985,675,274'Semiconductor clock signal generation circuit'19975,577,086'Clock signal generation circuit capable of operating at high speed with high frequency'19965,517,439'Arithmetic unit for executing division'19965,430,391'Data input/output control circuit'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–2017Patents assigned to TOSHIBA KK (28)· patent assignee history
1995–2017Based in Yokohama, JP· patent location history
1996Patents assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO LTD (1)· patent assignee history
1997–2009Based in Kanagawa, JP· patent location history
1999–2000Based in Tokyo, JP· patent location history
2012Patents assigned to FUJIMOTO YUKIHIRO (2)· patent assignee history
2012Patents assigned to KANI JUNICHI (1)· patent assignee history
2012Patents assigned to KUBO RYOGO (1)· patent assignee history
2012Based in Makuhari, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TOSHIBA KK281995–2017
FUJIMOTO YUKIHIROself22012
KANI JUNICHI12012
KUBO RYOGO12012
MATSUSHITA ELECTRIC INDUSTRIAL CO LTD11996
Locations
LocationPatentsSpan
Yokohama, JP181995–2017
Kanagawa, JP91997–2009
Tokyo, JP21999–2000
Makuhari, JP12012