Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device

1. Field of the Invention

Embodiments of the present invention relate generally to semiconductor device assemblies that include more than one semiconductor die. More specifically, embodiments of the present invention relate generally to semiconductor device assemblies that include electrically conductive paths that provide electrical communication between semiconductor dice in such semiconductor device assemblies and conductive structures of a substrate to which the semiconductor dice are structurally and electrically coupled. Embodiments of the present invention further relate to semiconductor device assemblies, to methods of fabricating such semiconductor device assemblies and to systems that include such semiconductor device assemblies.

2. Background of Related Art

In order to conserve the amount of surface area, or “real estate,” consumed on a carrier substrate, such as a circuit board, by semiconductor devices coupled thereto, various types of increased circuit density semiconductor devices have been developed. Some types of semiconductor device assemblies include semiconductor dice or semiconductor device packages that are stacked one over another. Among these various types of semiconductor devices are stacked multi-chip modules (MCMs) and package-on-package (POP) assemblies. The amount of surface area on a carrier substrate that may be saved by stacking semiconductor dice or semiconductor device packages is readily apparent. A stack of semiconductor dice or semiconductor device packages may consume roughly as little real estate on a carrier substrate as a single, horizontally oriented semiconductor die or semiconductor device package.

Another benefit of stacked semiconductor device assemblies is flexibility in manufacturing, as they provide a variety of configurations, while enabling high-volume semiconductor device production. By way of example and not limitation, stacked semiconductor device assemblies may be manufactured that combine various numbers of like semiconductor devices, such as dynamic random-access memory (DRAM) devices, providing a memory module that may be configured to a selected storage capacity. Stacked semiconductor device assemblies may also be manufactured that combine various numbers of different semiconductor devices. For example, a semiconductor device assembly may include a DRAM device, a non-volatile Flash memory device, and an application specific integrated circuit (ASIC) device, thereby combining the functionality of each semiconductor device into a single module. This is advantageous, as one may use a relatively small variety of semiconductor devices, which may be combined in a diversity of ways, and create a large variety of stacked semiconductor device assemblies with differing functionalities.

Semiconductor device assemblies typically include electrically conductive paths that provide electrical communication between the dice and a substrate to which dice are, or may be, attached. The electrically conductive paths are conventionally formed on or within a substrate, which provides them with support and mutual electrical isolation. Various designs of semiconductor device assemblies including such conductive paths have been disclosed in the art.

U.S. Pat. No. 5,977,640, to Bertin et al., which issued Nov. 2, 1999, discloses a stacked multi-chip module, including a chip-on-chip (COC) component, where the active region of a first chip is electrically coupled to the active region of a second chip. The COC component is coupled to a substrate, the upper surface of the substrate having solderable metallurgical pads and the lower surface having solder balls. Multiple components can then be stacked and coupled, with the solder balls on the bottom surface of a component corresponding to the metallurgical pads on the top surface of another component.

U.S. Pat. No. 6,020,629, to Farnworth et al., which issued Feb. 1, 2000 and is assigned to the assignee of the present invention, discloses a stacked multi-chip module, including multiple substrates, each having a semiconductor die mounted thereon. Each substrate includes matching patterns of external contacts and contact pads formed on opposing sides of the substrate. Interlevel conductors through the substrate interconnect the external contacts and contact pads. The external contact pads on a substrate are bonded to the contact pads on an adjacent substrate, such that all of the dice in the package are interconnected.

U.S. Pat. No. 6,072,233, to Corisis et al., which issued Jun. 6, 2000 and is assigned to the assignee of the present invention, discloses a package-on-package assembly in which fine ball grid array (FBGA) packages are stacked one upon another. Each FBGA package is configured such that conductive elements on the package extend beyond one or more of the major surfaces and make contact with adjacent FBGA packages in the stack.

U.S. Pat. No. 6,225,688, to Kim et al., which issued May 1, 2001, discloses a stacked multi-chip module, which includes a flexible substrate having a wiring layer with conductive paths extending to a plurality of attachment sites. A plurality of microelectronic components is assembled to the attachment sites, and the flexible substrate is folded so as to provide a stacked assembly with conductive terminals exposed at the bottom end of the stack.

U.S. Pat. No. 6,323,060, to Isaak, which issued Nov. 27, 2001, discloses a stacked multi-chip module, including multiple flex circuit integrated circuit (IC) packages. The patent teaches a flex circuit, which is comprised of a flexible base with a conductive pattern disposed thereon, that is wrapped around a frame, having an IC device mounted there within. The conductive pattern of the flex circuit is electrically coupled to the IC device, forming a stackable flex circuit IC package. Multiple flex circuit IC packages can then be stacked and electrically coupled using a conductive epoxy.

While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of the embodiments of the present invention can be more readily ascertained from the following description of various embodiments of the invention when read in conjunction with the accompanying drawings in which:

FIG. 1 is a side view of one example of a semiconductor device assembly that embodies teachings of the present invention;

FIG. 2 is a side view of another example of a semiconductor device assembly that embodies teachings of the present invention;

FIG. 3 is a side view of another example of a semiconductor device assembly that embodies teachings of the present invention;

FIG. 4 is a side view of another example of a semiconductor device assembly that embodies teachings of the present invention;

FIG. 5 is a cross-sectional side view of another example of a semiconductor device assembly that embodies teachings of the present invention;

FIG. 6 is a cross-sectional side view of another example of a semiconductor device assembly that embodies teachings of the present invention;

FIG. 7 is a cross-sectional side view of another example of a semiconductor device assembly that embodies teachings of the present invention;

FIGS. 8-17 illustrate one example of a method for forming a semiconductor device assembly that embodies teachings of the present invention;

FIGS. 18-21 illustrate another example of a method for forming a semiconductor device assembly that embodies teachings of the present invention;

FIG. 22 illustrates yet another example of a method for forming a semiconductor device assembly that embodies teachings of the present invention; and

FIG. 23 is a schematic diagram of a system that embodies teachings of the present invention.

In the description which follows, like features and elements may be identified by the same or similar reference numerals for ease of identification and enhanced understanding of the disclosure hereof. Such identification is by way of convenience for the reader only, however, and is not limiting of the present invention or an implication that features and elements of various components and embodiments identified by like reference numerals are identical or constrained to identical functions.

In one embodiment, the present invention includes a semiconductor device assembly that includes a plurality of semiconductor devices stacked one over another. At least one conductive pathway extends around a side of one semiconductor device in the assembly such that a first end thereof extends generally over a first major surface thereof and a second end extends generally over a second major surface thereof. The conductive pathway may include a self-supporting conductive lead or a conductive trace carried by a carrier substrate. Optionally, the semiconductor device assembly may include an additional conductive pathway that communicates electrically with the first conductive pathway and extends around the sides of at least two semiconductor devices of the assembly.

In another embodiment, the present invention includes a system having at least one electronic signal processor configured to communicate electrically with at least one memory device. At least one of the at least one electronic signal processor and the at least one memory device includes a semiconductor device assembly that includes a plurality of semiconductor devices stacked one over another. At least one conductive pathway extends around a side of one semiconductor device in the assembly such that a first end thereof extends generally over a first major surface thereof and a second end extends generally over a second major surface thereof. The at least one conductive pathway may include a self-supporting conductive lead or a conductive trace carried by a carrier substrate. Optionally, an additional conductive pathway may communicate electrically with the first conductive pathway and extend around the sides of at least two semiconductor devices of the assembly.

In yet another embodiment, the present invention includes a method of forming a semiconductor device assembly that includes at least two semiconductor devices. The method includes structurally and electrically coupling a conductive element of a first semiconductor device to an end of a conductive pathway and bending the conductive pathway around a side of the semiconductor device to position another end of the conductive pathway on an opposite side of the semiconductor device. A second semiconductor device then may be structurally and electrically coupled to the end of the conductive pathway positioned on the opposite side of the semiconductor device.

Several non-limiting examples of various embodiments of the present invention are described in further detail below.

Referring to FIG. 1 , an embodiment of the present invention in the form of semiconductor device assembly 10 that comprises a plurality of semiconductor devices 12 A- 12 D is depicted. As shown in FIG. 1 , the semiconductor devices 12 A- 12 D may be substantially bare semiconductor dice.

The semiconductor device assembly 10 may include a first semiconductor device 12 A, a second semiconductor device 12 B, a third semiconductor device 12 C, and a fourth semiconductor device 12 D. In additional embodiments, the semiconductor device assembly 10 may include only two, only three, or more than four semiconductor devices. In some embodiments, the semiconductor device assembly 10 may also comprise a substrate 26 , such as a printed circuit board (PCB). By way of example and not limitation, the substrate 26 may be or include an interposer substrate, a motherboard or daughterboard of a computer system, or other carrier substrate.

Each of the semiconductor devices 12 A- 12 D may include a respective first major surface 18 A- 18 D and a respective opposing second major surface 20 A- 20 D. The semiconductor devices 12 A- 12 D may further include conductive elements 16 A- 16 D, respectively, on or in their corresponding first major surface 18 A- 18 D. However, additional conductive elements may be disposed on or in one or more of the second major surfaces 20 A- 20 D. By way of example and not limitation, the conductive elements 16 A- 16 D may comprise bond pads, either at original or redistributed locations over the active surface. The conductive elements 16 A- 16 D may communicate electrically with components (e.g., transistors, capacitors, etc.) of integrated circuits (not shown) contained within each of the respective semiconductor devices 12 A- 12 D.

The semiconductor devices 12 A- 12 D may be configured in a stacked configuration, one stacked over the other, as depicted in FIG. 1 . For example, the first semiconductor device 12 A may be situated over a substrate 26 with its first major surface 18 A adjacent the substrate 26 . The second semiconductor device 12 B may be situated over the first semiconductor device 12 A, the third semiconductor device 12 C over the second semiconductor device 12 B, and the fourth semiconductor device 12 D over the third semiconductor device 12 C. As shown in FIG. 1 , in one particular non-limiting embodiment, set forth merely as an example, the first major surface 18 B of the second semiconductor device 12 B may be disposed adjacent the second major surface 20 A of the first semiconductor device 12 A, the first major surface 18 C of the third semiconductor device 12 C may be disposed adjacent the first major surface 18 B of the second semiconductor device 12 B, and the first major surface 18 D of the fourth semiconductor device 12 D may be disposed adjacent the second major surface 20 C of the third semiconductor device 12 C.

The semiconductor device assembly 10 may further include a plurality of self-supporting conductive leads. As used herein, the term “self-supporting conductive leads” is used in a non-limiting sense and includes elongated conductive paths, comprising a metal or metal alloy, that are supported by the metal or metal alloy from which they are formed and are not externally supported or carried by a substrate as are the conductive traces and vias of printed circuit boards (PCB), flexible printed wiring (FPW), or tape automated bonding (TAB) and the like, which are disposed on or within a dielectric substrate that provides support and electrical insulation. For example, the semiconductor device assembly 10 may include a first plurality of self-supporting conductive leads 14 A, a second plurality of self-supporting conductive leads 14 B, and a third plurality of self-supporting conductive leads 14 C. Each self-supporting conductive lead 14 A- 14 C has a first end 22 A- 22 C, respectively, and a second end 24 A- 24 C, respectively. In some embodiments, each of the second plurality of self-supporting conductive leads 14 B may be longer than each of the first plurality of self-supporting conductive leads 14 A, and each of the third plurality of self-supporting conductive leads 14 C may be longer than each of the second plurality of self-supporting conductive leads 14 B, as shown in FIG. 1 .

The self-supporting conductive leads 14 A- 14 C may be arranged in a plurality of lead stacks 15 , each lead stack 15 comprising one self-supporting conductive lead 14 A, one self-supporting conductive lead 14 B, and one self-supporting conductive lead 14 C. In the embodiment shown in FIG. 1 , the semiconductor device assembly 10 includes a plurality of lead stacks 15 disposed along each of two sides of the semiconductor device assembly 10 . In additional embodiments, lead stacks 15 may be disposed along only one side of the semiconductor device assembly 10 , or along more than two sides of the semiconductor device assembly 10 .

As shown in FIG. 1 , each self-supporting conductive lead 14 A may wrap around the side of the first semiconductor device 12 A, such that the first end 22 A thereof extends generally over a portion of the first major surface 18 A of the first semiconductor device 12 A, and the second end 24 A extends generally over the second major surface 20 A of the first semiconductor device 12 A. Each second self-supporting conductive lead 14 B may wrap around the sides of both the first and second semiconductor devices 12 A and 12 B, such that the first end 22 B thereof extends generally over the first end 22 A of a first self-supporting conductive lead 14 A, and the second end 24 B thereof extends generally over the second major surface 20 B of the second semiconductor device 12 B. Similarly, each third self-supporting conductive lead 14 C may wrap around the sides of each of the first, second, and third semiconductor devices 12 A- 12 C, such that the first end 22 C thereof extends generally over the first end 22 B of a second self-supporting conductive lead 14 B, and the second end 24 C thereof extends generally over the second major surface 20 C of the third semiconductor device 12 C.

In this configuration, the first ends 22 A- 22 C of the self-supporting conductive leads 14 A- 14 C in each lead stack 15 may be situated one over another, such that the first end 22 A of the first self-supporting conductive lead 14 A is disposed between the first major surface 18 A of the first semiconductor device 12 A and the first end 22 B of the second self-supporting conductive lead 14 B, and the first end 22 B of the second self-supporting conductive lead 14 B is disposed between the first end 22 A of the first self-supporting conductive lead 14 A and the first end 22 C of the third self-supporting conductive lead 14 C. Electrical communication may be established between the self-supporting conductive leads 14 A- 14 C of each lead stack 15 . For example, electrical communication may be established between the first ends 22 A- 22 C of the self-supporting conductive leads 14 A- 14 C of each lead stack 15 . In some embodiments, the first ends 22 A- 22 C of the self-supporting conductive leads 14 A- 14 C in each lead stack 15 may be structurally and electrically coupled together by, for example, using a conductive adhesive, a soldering process, a brazing process, or a welding process (e.g., a spot welding process).

As shown in FIG. 1 , each conductive element 16 A of the first semiconductor device 12 A may be structurally and electrically coupled to a first end 22 A of a first self-supporting conductive lead 14 A using conductive material 28 . Each conductive element 16 B of the second semiconductor device 12 B may be structurally and electrically coupled to a second end 24 A of a first self-supporting conductive lead 14 A using conductive material 28 . Similarly, each conductive element 16 C of the third semiconductor device 12 C may be structurally and electrically coupled to a second end 24 B of a second self-supporting conductive lead 14 B using conductive material 28 , and each conductive element 16 D of the third semiconductor device 12 D may be structurally and electrically coupled to a second end 24 C of a third self-supporting conductive lead 14 C using conductive material 28 . By way of example and not limitation, the conductive material 28 may include solder material (e.g., solder balls, solder bumps; etc.), conductive or conductor-filled epoxy, anisotropically conductive film, or any other suitable conductive material that may be used to structurally and electrically couple together the respective conductive structures (such as, for example, bond pads and conductive leads).

Additionally, each lead stack 15 may be structurally and electrically coupled to conductive terminals and/or traces (not shown) of the substrate 26 using, for example, conductive material 28 . In this configuration, electrical communication may be established between the components of the integrated circuits (not shown) contained within each semiconductor device 12 A- 12 D and conductive terminals and/or traces of the substrate 26 through the self-supporting conductive leads 14 A- 14 C.

As will be apparent to those of ordinary skill in the art, it is not necessary that all lead stacks 15 of the semiconductor device assembly 10 communicate electrically with each of the semiconductor devices 12 A- 12 D. For example, some of the lead stacks may be configured as “chip-select” lead stacks and may communicate with only one of the semiconductor devices 12 A- 12 D. In such chip-select lead stacks, non-conductive material (not shown) may be used in place of the conductive material 28 as necessary to electrically insulate one or more of the semiconductor devices 12 A- 12 D from the self-supporting conductive leads 14 A- 14 C of such chip-select lead stacks.

FIG. 2 illustrates another embodiment of the present invention in the form of semiconductor device assembly 60 . The semiconductor device assembly 60 is generally similar to the semiconductor device assembly 10 shown in FIG. 1 , and may include a plurality of semiconductor devices 12 A- 12 D, which may be coupled to a substrate 26 . The semiconductor device assembly 60 includes a plurality of self-supporting conductive leads, which may include the conductive leads 14 A- 14 C, and an additional fourth plurality of self-supporting conductive leads 14 D.

As illustrated in this example, the semiconductor devices 12 A- 12 D of the semiconductor device assembly 60 may be situated with their respective first major surfaces 18 A- 18 D facing upwards, away from the substrate 26 . Each self-supporting conductive lead 14 D of the additional fourth plurality of self-supporting conductive leads 14 D, may extend over the sides of semiconductor devices 12 A- 12 D. The second end 24 D of each self-supporting conductive lead 14 D may extend generally over the first major surface 18 D of the fourth semiconductor device 12 D, and the first end 22 D of each self-supporting conductive lead 14 D may extend generally over the first end 22 C of a third self-supporting conductive lead 14 C. Additionally, the conductive elements 16 A- 16 D of the semiconductor devices 12 A- 12 D may be structurally and electrically coupled to the corresponding second ends 24 A- 24 D of the self-supporting conductive leads 14 A- 14 D using conductive material 28 , in a manner substantially similar to that previously described in relation to the semiconductor device assembly 10 shown in FIG. 1 .

FIG. 3 illustrates yet another embodiment of the present invention in the form of semiconductor device assembly 70 . The semiconductor device assembly 70 is generally similar to the semiconductor device assembly 10 shown in FIG. 1 , and may include a plurality of semiconductor devices 12 A- 12 D, which may be coupled to a substrate 26 . The semiconductor device assembly 70 includes a plurality of self-supporting conductive leads. For example, the semiconductor device assembly 70 may include a first plurality of self-supporting conductive leads 14 E and a second plurality of self-supporting conductive leads 14 F, each having a respective first end 22 E and 22 F and a respective second end 24 E and 24 F.

As illustrated in FIG. 3 , the first major surfaces 18 A and 18 C of the. semiconductor devices 12 A and 12 C may face downwards, towards the substrate 26 , and the first major surfaces 18 B and 18 D of the semiconductor devices 12 B and 12 D may face upwards, away from the substrate 26 .

With continued reference to FIG. 3 , the first ends 22 E of the first plurality of self-supporting conductive leads 14 E may be disposed between the first major surface 18 A of the first semiconductor device 12 A and the first ends 22 F of the second plurality of self-supporting conductive leads 14 F. In this configuration, a first side of each of the first ends 22 E of the self-supporting conductive leads 14 E may be structurally and electrically coupled to the conductive elements 16 A of the first semiconductor device 12 A using conductive material 28 , and a second side of each of the first ends 22 E of the self-supporting conductive leads 14 E may be structurally and electrically coupled to a first side of the first end 22 F of a second self-supporting conductive lead 14 F. The first ends 22 F of the second plurality of self-supporting conductive leads 14 F may be disposed between a substrate 26 and the first ends 22 E of the first plurality of self-supporting conductive leads 14 E. A second side of each of the first ends 22 F of the second self-supporting conductive leads 14 F may be structurally and electrically coupled to the substrate 26 using conductive material 28 .

The second ends 24 E of the first self-supporting conductive leads 14 E, may be disposed between the first major surface 18 B of the second semiconductor device 12 B and the first major surface 18 C of the third semiconductor device 12 C. The second end 24 E of each of the first conductive leads 14 E may be structurally and electrically coupled to both a conductive element 16 B of the second semiconductor device 12 B and a conductive element 16 C of the third semiconductor device 12 C using conductive material 28 , as shown in FIG. 3 . The second end 24 F of each of the second self-supporting conductive leads 14 F may extend over the first major surface 18 D of the fourth semiconductor device 12 D and may be structurally and electrically coupled to a conductive elements 16 D of the fourth semiconductor device 12 D using conductive material 28 .

FIG. 4 illustrates another embodiment of the present invention in the form of semiconductor device assembly 80 . The semiconductor device assembly 80 is generally similar to the semiconductor device assembly 10 shown in FIG. 1 , and may include a plurality of semiconductor devices 12 A- 12 D, which may be coupled to a substrate 26 . The semiconductor device assembly 80 may include a plurality of self-supporting conductive leads. For example, the semiconductor device assembly 80 may include a first plurality of self-supporting conductive leads 14 G and a second plurality of self-supporting conductive leads 14 H, each having a respective first end 22 G and 22 H and a respective second end 24 G and 24 H.

As illustrated in FIG. 4 , the first major surfaces 18 A and 18 C of the semiconductor devices 12 A and 12 C may face upwards, away from the substrate 26 , and the first major surfaces 18 B and 18 D of the semiconductor devices 12 B and 12 D may face downwards, towards the substrate 26 .

The first ends 22 G and 22 H of the self-supporting conductive leads 14 G and 14 H may be configured substantially identical to the first ends 22 E and 22 F of the self-supporting conductive leads 14 E and 14 F shown in FIG. 3 , with the exception that the first end 22 G of the self-supporting conductive lead 14 G is not structurally and electrically coupled directly to a conductive element 16 A of the first semiconductor device 12 A, as is the first end 22 E of the self-supporting conductive lead 14 E.

The second end 24 G of each first self-supporting conductive lead 14 G, may be disposed between the first major surface 18 A of the first semiconductor device 12 A and the first major surface 18 B of the second semiconductor device 12 B. Furthermore, a first side of the second end 24 G of each first self-supporting conductive lead 14 G may be structurally and electrically coupled directly to a conductive element 16 A of the first semiconductor device 12 A using conductive material 28 , and a second side of the second end 24 G of each first self-supporting conductive lead 14 G may be structurally and electrically coupled directly to a conductive element 16 B of the second semiconductor device 12 B using conductive material 28 . The second end 24 H of each second self-supporting conductive leads 14 H may be disposed between the first major surface 18 C of the third semiconductor device 12 C and the first major surface 18 D of the fourth semiconductor device 12 D. Furthermore, a first side of the second end 24 H of each second self-supporting conductive lead 14 H may be structurally and electrically coupled directly to a conductive element 16 C of the third semiconductor device 12 C using conductive material 28 , and a second side of the second end 24 H of each second self-supporting conductive lead 14 H may be structurally and electrically coupled directly to a conductive element 16 D of the fourth semiconductor device 12 D using conductive material 28 .

As previously mentioned, it is not necessary that semiconductor device assemblies that embody teachings of the present invention include four semiconductor devices. FIG. 5 illustrates another embodiment of the present invention in the form of semiconductor device assembly 100 that includes only two semiconductor devices. For example, the semiconductor device assembly 100 may include a first substantially bare die 112 A and a second substantially bare die 112 B, which may be structurally and electrically coupled to a substrate 26 . The semiconductor device assembly 100 further includes a plurality of self-supporting conductive leads 114 , each having a first end 122 , and a second end 124 .

The semiconductor dice 112 A and 112 B may have bond pads 116 A and 116 B on or in their respective first major surfaces 118 A and 118 B. The bond pads 116 A of the first semiconductor die 112 A may be structurally and electrically coupled to the first ends 122 of the self-supporting conductive leads 114 using solder balls 128 , and the bond pads 116 B of the second semiconductor die 112 B may be structurally and electrically coupled to the second ends 124 using solder balls 128 . In addition, the first ends 122 also may be structurally and electrically coupled to the substrate 26 using solder balls 128 . In additional embodiments, other solder structures (e.g., solder bumps, solder balls, etc.), conductive or conductor-filled epoxy, anisotropically conductive film, or any other conductive material that may be used to structurally and electrically couple together conductive structures may be used in addition to, or as an alternative to, the solder balls 128 .

In addition to substantially bare semiconductor dice, semiconductor device assemblies that embody teachings of the present invention may include other types of semiconductor devices, such as, for example, semiconductor device packages. FIG. 6 illustrates another semiconductor device assembly 150 that embodies teachings of the present invention in a somewhat different structural form. The semiconductor device assembly 150 is generally similar to the semiconductor device assembly 100 shown in FIG. 5 . In contrast to substantially bare semiconductor dice of the semiconductor device assembly 100 , however, the semiconductor device assembly 150 may include a first semiconductor device package 152 A and a second semiconductor device package 152 B. By way of example and not limitation, each of the first and second semiconductor device packages 152 A and 152 B may include a package substrate 154 , a first semiconductor die 156 , and a second semiconductor die 158 . In additional embodiments, each of the semiconductor device packages 152 A and 152 B may include only one semiconductor die. In yet other embodiments, each of the semiconductor device packages 152 A and 152 B may include more than two semiconductor dice.

As shown in FIG. 6 , the first and second semiconductor device packages 152 A and 152 B may be substantially identical in some embodiments of the present invention. In other embodiments, the second semiconductor device package 152 B may differ from the first semiconductor device package 152 A in at least one aspect. As shown in FIG. 6 , in each of the first and second semiconductor device packages 152 A and 152 B, the first semiconductor die 156 may be situated generally over the package substrate 154 , and the second semiconductor die 158 may be situated generally over the first semiconductor die 156 . A dielectric spacer 160 A may be disposed between the first semiconductor die 156 and the second semiconductor die 158 . Similarly, another dielectric spacer 160 B may be disposed between the first semiconductor die 156 and the package substrate 154 . The dielectric spacers 160 A and 160 B may be used to electrically isolate each of the package substrate 154 , the first semiconductor die 156 , and the second semiconductor die 158 from one another. By way of example and not limitation, the dielectric spacers 160 A and 160 B may be or include a layer of disc comprising an electrically insulating material, such as, for example a polymer material (e.g., epoxy), a ceramic material (e.g., silica), or silicon.

Each of the first semiconductor die 156 and the second semiconductor die 158 may communicate electrically with the respective package substrate 154 . By way of example and not limitation, bond wires 162 may be used to provide electrical communication between bond pads 164 on or in a surface of each semiconductor die 156 and 158 and corresponding conductive lands 166 on or in a surface of the package substrate 154 . Conductive traces and/or vias (not shown) on and/or in the package substrates 154 may provide electrical communication between the conductive lands 166 and the conductive terminals 168 .

Optionally, each of the semiconductor device packages 152 A and 152 B may include a dielectric encapsulant material 170 , shown for purposes of illustration only as a transfer-molded encapsulant. By way of example and not limitation, an encapsulant material 170 may be disposed around the bond wires 162 and over at least a portion of the package substrate 154 and the semiconductor dice 156 , 158 . The semiconductor device packages 152 A and 152 B shown in FIG. 6 and described herein are disclosed merely as an example of one type of a semiconductor device package that may be used in semiconductor device assemblies that embody teachings of the present invention.

As will be apparent to those of ordinary skill in the art, the semiconductor device packages 152 A and 152 B shown in FIG. 6 have a “board-on-chip” (BOC) configuration. In additional embodiments, the semiconductor device packages 152 A and 152 B may have a “chip-on-board” (COB) configuration. Furthermore, each of the semiconductor device packages 152 A and 152 B may include semiconductor dice that are flip-chip bonded to the underlying semiconductor die or package substrate 154 , and may not include bond wires 162 . Various other types of semiconductor device packages are known in the art and may be used to provide additional semiconductor device assemblies that embody teachings of the present invention.

Each of the previously described semiconductor device assemblies include conductive pathways provided by self-supporting conductive leads extending between the semiconductor devices and the respective substrate 26 . The present invention is not so limited, however, and such conductive pathways may be provided by conductive traces carried on or in a carrier substrate, such as, for example, those conventionally used in so-called “flex-circuit” and tape-automated bonding (TAB) applications.

The semiconductor device assembly 350 shown in FIG. 7 illustrates an example of a semiconductor device assembly 350 that embodies teachings of the present invention and includes conductive traces 352 A- 352 D carried on or in a carrier substrate 358 A- 358 D. The semiconductor device assembly 350 is generally similar to the previously described semiconductor device assembly 60 shown in FIG. 2 , and may include a plurality of semiconductor devices 12 A- 12 D. The semiconductor device assembly 350 may further include a first plurality of conductive traces 352 A carried by at least one first layer carrier substrate 358 A, a second plurality of conductive traces 352 B carried by at least one second layer carrier substrate 358 B, a third plurality of conductive traces 352 C carried by at least one third layer carrier substrate 358 C, and a fourth plurality of conductive traces 352 D carried by at least one fourth layer carrier substrate 358 D. In the embodiment shown in FIG. 7 , the semiconductor device assembly 350 includes two first layer carrier substrates 358 A, two second layer carrier substrates 358 B, two third layer carrier substrates 358 C, and two fourth layer carrier substrates 358 D. The carrier substrates 358 A- 358 D are configured to wrap generally around two sides of each of the semiconductor devices 12 A- 12 D. The carrier substrates 358 A- 358 D may, respectively, provide structural support for conductive traces 352 A- 352 D.

In additional embodiments, the semiconductor device assembly 350 may include only one of each of the first through fourth layers of carrier substrates 358 A- 358 D, or more than two of each of the first through fourth layers of carrier substrates 358 A- 358 D. Furthermore, the carrier substrates 358 A- 358 D may be configured to wrap generally around only one side of each of the semiconductor devices 12 A- 12 D, or to wrap generally around more than two sides of each of the semiconductor devices 12 A- 12 D.

By way of example and not limitation, the conductive traces 352 A- 352 D each may include a conductive material such as, for example, copper or copper-based alloy (including alloys based on copper and beryllium), aluminum or aluminum-based alloy, nickel-chromium-iron superalloy (such as that sold under the trademark INCONEL®), or a conductive polymer material.

By way of example and not limitation, each of the carrier substrates 358 A- 358 D may include a flexible dielectric material such as, for example, a polyimide or polyimide-based material, a polyester or polyester-based material, an aramid or aramid-based material, a reinforced composite material, or a fluorocarbon-based material (e.g., polytetrafluoroethylene).

As shown in FIG. 7 , each conductive trace 352 A- 352 D may have a respective first end 354 A- 354 D and a respective second end 356 A- 356 D. The conductive traces 352 A and 352 B may be configured to provide stacks of conductive traces, similar to the lead stacks 15 previously described in relation to FIG. 1 . Electrical communication may be provided between the conductive traces 356 A amd 356 D in each stack at the first ends 354 A- 354 D thereof. For example, in some embodiments, the conductive traces 352 A- 352 D on each carrier substrate 358 A- 358 D may have a substantially similar configuration, differing only in the length of the respective conductive traces 352 A- 352 D. In this configuration, the first ends 354 A- 354 D of the conductive traces 352 A- 352 D may be aligned with one another by aligning the carrier substrates 358 A- 358 D. By way of example and not limitation, through holes may be formed through the carrier substrates 358 A- 358 D and each of the conductive traces 352 A- 352 D in each trace stack. The through holes then may be aligned and filled with a conductive material, such as, for example, a conductive metal or metal alloy, to form conductive vias 360 that provide electrical communication between the conductive traces 352 A- 352 D in each stack.

With continued reference to FIG. 7 , the second end 356 A of each of the first plurality of conductive traces 352 A may be structurally and electrically coupled to a conductive element 16 A of the first semiconductor device 12 A using conductive material 28 . The second end 356 B of each of the second plurality of conductive traces 352 B may be structurally and electrically coupled to a conductive element 16 B of the second semiconductor device 12 B using conductive material 28 . Similarly, the second end 356 C of each of the third plurality of conductive traces 352 C may be structurally and electrically coupled to a conductive element 16 C of the third semiconductor device 12 C using conductive material 28 . Finally, the second end 356 D of each of the fourth plurality of conductive traces 352 D may be structurally and electrically coupled to a conductive element 16 D of the fourth semiconductor device 12 D using conductive material 28 .

In addition, the first ends 354 A- 354 D may be structurally and electrically coupled to the substrate by way of vias 360 through the carrier substrates 358 A- 358 D (e.g., flexible dielectric films) using conductive material 28 .

Any of the previously described semiconductor device assemblies (e.g., the semiconductor device assembly 10 shown in FIG. 1 , the semiconductor device assembly 60 shown in FIG. 2 , the semiconductor device assembly 70 shown in FIG. 3 , the semiconductor device assembly 80 shown in FIG. 4 , the semiconductor device assembly 100 shown in FIG. 5 , and the semiconductor device assembly 150 shown in FIG. 6 ) may include conductive pathways provided by conductive traces carried on or in a carrier substrate, in addition to, or as an alternative to, the previously described self-supporting conductive leads.

Additional embodiments of the present invention include methods of manufacturing semiconductor device assemblies. One example of a method that embodies teachings of the present invention and that may be used to manufacture a semiconductor device assembly, such as the semiconductor device assembly 10 shown in FIG. 1 , is described below with reference to FIGS. 8-17 .

Referring to FIG. 8 , a first lead frame 200 A may be provided that includes a first plurality of self-supporting conductive leads 14 A. The self-supporting conductive leads 14 A may be attached to a carrier strip 206 A as shown in FIG. 8 (providing an integral tie bar extending laterally between self-supporting conductive leads 14 A, and/or to an outer frame member 201 A of the first lead frame 200 A). The first lead frame 200 A may further include additional tie bars (not shown), which may extend laterally between adjacent self-supporting conductive leads 14 A to provide additional support to the first plurality of self-supporting conductive leads 14 A during forming, as known in the art. The lead frame 200 A may be formed by, for example, cutting, stamping, punching, or etching a sheet of metal or metal alloy, or by any other method known in the art for forming conventional lead frames.

The area of FIG. 8 enclosed within the dashed line 202 is illustrated in an enlarged perspective view in FIG. 9 to facilitate description thereof. As shown in FIG. 9 , the first ends 22 A of the self-supporting conductive leads 14 A may be cantilevered from the carrier strip 206 A (or other element of the lead frame 200 A) and positioned in a generally central region of the lead frame 200 A.

Referring to FIG. 10 , a first semiconductor device 12 A may be positioned over the self-supporting conductive leads 14 A such that conductive elements 16 A ( FIG. 1 ), disposed on a surface thereof, are aligned with and adjacent the first ends 22 A of the conductive elements 16 A, and the first ends 22 A of the conductive elements 16 A may be structurally and electrically coupled to the conductive elements 16 A using a conductive material 28 , as previously described. Referring to FIG. 11 , the carrier strip 206 A may be severed from the self-supporting conductive leads 14 A. After severing the carrier strip 206 A from the self-supporting conductive leads 14 A, the self-supporting conductive leads 14 A may extend laterally from the semiconductor device 12 A, and the second ends 24 A of the self-supporting conductive leads 14 A may be disposed laterally outward from the semiconductor device 12 A and coplanar with the first ends 22 A of the self-supporting conductive leads 14 A.

As shown in FIG. 12 , the self-supporting conductive leads 14 A may be bent or wrapped around side 30 A of the semiconductor device 12 A, such that the second ends 24 A extend generally over the second major surface 20 A of the first semiconductor device 12 A. By way of example and not limitation, each of the self-supporting conductive leads 14 A may be bent or wrapped around the side 30 A of the semiconductor device 12 A using commercially available trim-and-form equipment for bending or forming self-supporting conductive leads 14 A.

As the self-supporting conductive leads 14 A are bent or wrapped around the side 30 A of the semiconductor device 12 A, the second ends 24 A of the self-supporting conductive leads 14 A may be positioned at relative positions substantially corresponding to a pattern of conductive elements on a second semiconductor device 12 B to be attached thereto, as described in further detail below.

In some embodiments, the self-supporting conductive leads 14 A may be caused to substantially conform to the exterior surfaces of the semiconductor device 12 A. In additional embodiments, the self-supporting conductive leads 14 A may not substantially conform to the exterior surfaces of the semiconductor device 12 A.

Referring to FIG. 13 , a second lead frame 200 B may be provided that is generally similar to the first lead frame 200 A ( FIGS. 8-10 ), with the exception that the self-supporting conductive leads 14 B of the second lead frame 200 B may be longer than the self-supporting conductive leads 14 A of the first lead frame 200 A. As shown in FIG. 13 , the first ends 22 B of the second self-supporting conductive leads 14 B may be aligned with and positioned over the first ends 22 A of the self-supporting conductive leads 14 A, and the first ends 22 B of the self-supporting conductive leads 14 B may be structurally and electrically coupled to the first ends 22 A of the self-supporting conductive leads 14 A, as previously described.

As shown in FIG. 14 , a second semiconductor device 12 B may be positioned over the second ends 24 A ( FIG. 13 ) of the first self-supporting conductive leads 14 A such that conductive elements 16 B ( FIG. 1 ) disposed on a surface of the second semiconductor device 12 B are aligned with and adjacent the second ends 24 A of the self-supporting conductive leads 14 A. The second ends 24 A of the self-supporting conductive leads 14 A may be structurally and electrically coupled to the conductive elements 16 B of the second semiconductor device 12 B using a conductive material 28 , as previously described. In additional embodiments, the conductive elements 16 B of the second semiconductor device 12 B may be attached to the second ends 24 A of the self-supporting conductive leads 14 A prior to attaching the first ends 22 B of the self-supporting conductive leads 14 B to the first ends 22 A of the self-supporting conductive leads 14 A.

Referring to FIG. 15 , the carrier strip 206 B may be severed from the self-supporting conductive leads 14 B in a manner substantially identical to that previously described in relation to the carrier strip 206 A with reference to FIG. 11 . After severing the carrier strip 206 B from the self-supporting conductive leads 14 B, the self-supporting conductive leads 14 B may extend laterally from the assembly, and the second ends 24 B of the self-supporting conductive leads 14 B may be disposed laterally outward from the assembly and coplanar with the first ends 22 B of the self-supporting conductive leads 14 B.

As shown in FIG. 16 , the self-supporting conductive leads 14 B may be bent or wrapped around the side 30 A of the first semiconductor device 12 A and the side 30 B of the second semiconductor device 12 B, such that the second ends 24 B extend generally over the second major surface 20 B of the second semiconductor device 12 B. As the self-supporting conductive leads 14 B are bent or wrapped around the side 30 A of the first semiconductor device 12 A and the side 30 B of the second semiconductor device 12 B, the second ends 24 B of the self-supporting conductive leads 14 B may be positioned at relative positions substantially corresponding to a pattern of conductive elements on a third semiconductor device 12 C ( FIG. 1 ) to be attached thereto.

Referring to FIG. 17 , a third lead frame 200 C may be provided that is generally similar to the first lead frame 200 A and the second lead frame 200 B, with the exception that the self-supporting conductive leads 14 C of the third lead frame 200 C may be longer than the self-supporting conductive leads 14 B of the second lead frame 200 B. As shown in FIG. 17 , the first ends 22 C of the third self-supporting conductive leads 14 C may be aligned with and positioned over the first ends 22 B of the self-supporting conductive leads 14 B, and the first ends 22 C of the self-supporting conductive leads 14 C may be structurally and electrically coupled to the first ends 22 B of the self-supporting conductive leads 14 B, as previously described.

The above-described processes may be repeated until a selected number of semiconductor devices have been structurally and electrically coupled to one another, to provide a semiconductor device assembly that embodies teachings of the present invention. For example, the above-described processes may be repeated to structurally and electrically couple together four semiconductor devices 12 A- 12 D, thereby providing the semiconductor device assembly 10 shown in FIG. 1 . Furthermore, the process described above with reference to FIGS. 8-17 may be used to provide any of the previously described semiconductor device assemblies, simply by flipping the semiconductor devices over as necessary and attaching the conductive elements of each semiconductor devices to the respective ends of the conductive leads that are disposed adjacent thereto.

In additional methods that embody teachings of the present invention, the leads of each lead stack 15 ( FIG. 1 ) may be structurally and electrically coupled to one another prior to attaching any semiconductor device to the conductive leads. For example, the previously described first lead frame 200 A, second lead frame 200 B, and third lead frame 200 C may be provided and stacked one on top of another, such that the first ends 22 A, 22 B, 22 C of the self-supporting conductive leads 14 A, 14 B, 14 C are disposed adjacent one another, as shown in FIG. 18 . The first ends 22 A, 22 B, 22 C of the self-supporting conductive leads 14 A, 14 B, 14 C then may be structurally and electrically coupled together by, for example, using a conductive adhesive, a welding process (e.g., a spot welding process), a soldering process, or a brazing process.

Referring to FIG. 19 , a first semiconductor device 12 A may be positioned over the self-supporting conductive leads 14 A such that conductive elements 16 A, disposed on or in a surface thereof, are aligned with and adjacent the first ends 22 A of the conductive leads 16 A, and the first ends 22 A of the self-supporting conductive leads 14 A may be structurally and electrically coupled to the conductive elements 16 A using a conductive material 28 , as previously described. The carrier strip 206 A ( FIG. 18 ) may be severed from the self-supporting conductive leads 14 A, and the self-supporting conductive leads 14 A may be bent or wrapped around the side 30 A of the first semiconductor device 12 A such that the second ends 24 A extend generally over the second major surface 20 A of the first semiconductor device 12 A, as shown in FIG. 20 .

Referring to FIG. 21 , a second semiconductor device 12 B may be positioned over the second ends 24 A (of the first self-supporting conductive leads 14 A such that conductive elements 16 B disposed on a surface of the second semiconductor device 12 B are aligned with and adjacent the second ends 24 A of the self-supporting conductive leads 14 A. The second ends 24 A of the self-supporting conductive leads 14 A may be structurally and electrically coupled to the conductive elements 16 B of the second semiconductor device 12 B using a conductive material 28 , as previously described. The carrier strip 206 B ( FIG. 18 ) may be severed from the self-supporting conductive leads 14 B, and the self-supporting conductive leads 14 B may be bent or wrapped around the side 30 A of the first semiconductor device 12 A and the side 30 B of the second semiconductor device 12 B such that the second ends 24 B extend generally over the second major surface 20 B of the second semiconductor device 12 B, as shown in FIG. 21 .

The above-described processes may be repeated until a selected number of semiconductor devices have been structurally and electrically coupled to one another, thereby providing a semiconductor device assembly that embodies teachings of the present invention. For example, the above described processes may be repeated to structurally and electrically couple together four semiconductor devices 12 A- 12 D, thereby providing the semiconductor device assembly 10 shown in FIG. 1 . Furthermore, the process described above with reference to FIGS. 18-21 may be used to provide any of the previously described semiconductor device assemblies, simply by flipping the semiconductor devices over as necessary and attaching the conductive elements of each semiconductor devices to the respective ends of the conductive leads that are disposed adjacent thereto.

In yet additional methods that embody teachings of the present invention, the semiconductor devices may be structurally coupled to one another and to the conductive leads prior to bending or wrapping the conductive leads around any of the semiconductor devices. For example, referring to FIG. 22 , the conductive elements 16 D of the fourth semiconductor device 12 D may be structurally and electrically coupled to the first ends 22 D of a fourth plurality of self-supporting conductive leads 14 D using a conductive material 28 . The first ends 22 C of the third plurality of self-supporting conductive leads 14 C may be structurally coupled to the second major surface 20 D of a fourth semiconductor device 12 D using, for example, a non-conducting adhesive material (epoxy, double-sided adhesive film, etc.). The conductive elements 16 C of the third semiconductor device 12 C may be structurally and electrically coupled to the first ends 22 C of the third plurality of self-supporting conductive leads 14 C using a conductive material 28 . The first ends 22 B of the second plurality of self-supporting conductive leads 14 B may be structurally coupled to the second major surface 20 C of the third semiconductor device 12 C using, for example, a non-conducting adhesive material. The conductive elements 16 B of the second semiconductor device 12 B may be structurally and electrically coupled to the first ends 22 C of the third plurality of self-supporting conductive leads 14 C using a conductive material 28 . The first ends 22 A of the first plurality of self-supporting conductive leads 14 A may be structurally coupled to the second major surface 20 B of the second semiconductor device 12 B using, for example, a non-conducting adhesive material. The conductive elements 16 A of the first semiconductor device 12 A may be structurally and electrically coupled to the first ends 22 A of the first plurality of self-supporting conductive leads 14 A using a conductive material 28 .

After forming the structure shown in FIG. 22 , the first self-supporting conductive leads 14 A may be bent or wrapped around the first semiconductor device 12 A as previously described, followed by the second plurality of self-supporting conductive leads 14 B, the third plurality of self-supporting conductive leads 14 C, and the fourth plurality of self-supporting conductive leads 14 D. The second ends 24 A, 24 B, 24 C, 24 D of the self-supporting conductive leads 14 A, 14 B, 14 C, 14 D thus may be positioned generally over the second major surface 20 A of the first semiconductor device 12 A and structurally and electrically coupled to one another, as previously described, thereby forming the semiconductor device assembly 60 shown in FIG. 2 .

The previously described methods have been described with reference to self-supporting conductive leads. Additional methods that embody teachings of the present invention may be carried out using other configurations of electrical pathways, including, for example, conductive traces carried on or in a carrier substrate, as previously described with reference to FIG. 7 . In such methods, some ends of the conductive traces may be electrically coupled to conductive elements of semiconductor devices as necessary, while other ends of the conductive traces may be electrically coupled to one another in a manner substantially identical to that previously described with reference to FIG. 7 . Furthermore, the carrier substrate (and conductive traces carried thereby) may be bent or wrapped around the sides of the semiconductor devices in a manner substantially similar to that previously described in relation to the self-supporting conductive leads.

Semiconductor device assemblies that embody teachings of the present invention may be used in electronic systems such as, for example, a desktop computer, a laptop computer, a handheld computer (e.g., a personal data assistant (PDA)), a mobile telephone, an audio player, a digital camera, a video player, and a visual display. Furthermore, such electronic systems may include, for example, computer subsystems such as graphic cards, etc. FIG. 23 is a simplified schematic diagram of a computer system 300 that embodies teachings of the present invention and includes a processor device 302 and a memory device 304 . At least one of the processor device 302 and the memory device 304 may be or include a semiconductor device assembly that embodies teachings of the present invention (e.g., the semiconductor device assembly 10 shown in FIG. 1 , the semiconductor device assembly 60 shown in FIG. 2 , the semiconductor device assembly 70 shown in FIG. 3 , the semiconductor device assembly 80 shown in FIG. 4 , the semiconductor device assembly 100 shown in FIG. 5 , and the semiconductor device assembly 150 shown in FIG. 6 ).

Additionally, the computer system 300 may include an input device 306 (such as, for example, a key pad, a pointing device, or an electronic sensor) and an output device 308 (such as, for example, a monitor, an audio speaker, a printer, or an electromechanical actuator).

Semiconductor device assemblies that embody teachings of the present invention may provide a robust POP structure with enhanced solder joint reliability, and a lower stacked package profile in comparison to conventional POP structures. Such semiconductor device assemblies may also exhibit improved RLC performance by, for example, providing greater speed with higher signal quality and experiencing or exhibiting reduced parasitic capacitances along the conductive pathways extending between the semiconductor devices of the assemblies because the pathways extend around the sides of the semiconductor devices, instead of through each of the semiconductor devices. Furthermore, the self-supporting conductive leads described herein may behave as a heat sink, drawing heat generated within the semiconductor devices to the outside of the assembly, which may provide enhanced performance and/or longer product life. In addition, each semiconductor device, which may be a semiconductor device package or a bare die, may optionally be burned-in and tested prior to assembly in the stack.

While the present invention has been described in terms of certain illustrated embodiments and variations thereof, it will be understood and appreciated by those of ordinary skill in the art that the invention is not so limited. Rather, additions, deletions and modifications to the illustrated embodiments may be effected without departing from the spirit and scope of the invention as defined by the claims, which follow.