High density memory array system

This application is a Continuation-In-Part of application Ser. No. 10/831,199, filed Apr. 26, 2004, now U.S. Pat. No. 7,072,210 and entitled “Memory Array”.

1. Field of the Invention

The invention relates to a semiconductor device, and more particularly to a memory array with increased data throughput.

2. Description of the Related Art

Non-volatile read only memory (ROM) retains information even if power is cut off. Erasable ROM types comprise Mask ROM, EPROM, EEPROM, and Flash Memory, of which Mask ROM cannot modify stored data, and is suited to large fabrications. Additionally, Flash Memory, using electrons entering and exiting floating gate to store information, is non-volatile and accessible, and can also restore and access information even when power is not provided.

FIG. 1 a is a cross section of a conventional flash memory unit during programming. When programming is performed, a high voltage is applied to a control gate electrode 105 and a drain region 101 a , and then electrons penetrate through a gate oxide layer 102 to a floating gate electrode 103 from the drain region 101 a in a silicon substrate 101 .

FIG. 1 b is a cross section of a conventional flash memory unit during erasure. When erasure is performed, a negative or zero voltage is applied to the control gate electrode 105 , and a high voltage is applied to the drain region 101 a in the silicon substrate 101 . Electrons then penetrate through the gate oxide layer 102 back to the drain region 101 a from the floating gate electrode 103 .

As a result, one set of data can be programmed or erased each time by the conventional flash memory unit, that is, the maximum set count of data programmed or erased each time equals the number of memory units.

FIG. 1 c is a cross section of a conventional programmed Mask ROM. The programming process is disclosed as follows. First, a silicon substrate 120 having a memory unit, such as a MOS transistor, thereon is provided. An oxide layer 122 is then formed over the silicon substrate 120 . The memory unit comprises a gate electrode 123 , such as a polysilicon layer, and source/drain regions 121 a and 121 b , such as n + or p + diffusion region, here, the source/drain regions 121 a and 121 b are n + diffusion regions.

Next, a lithography process is performed using a code mask to form a patterned photoresist layer over a part of the gate electrode 123 and the source/drain regions 121 a and 121 b . Channel implantation with the silicon substrate 120 having memory units is then performed to complete the memory unit coding. When the gate electrode 123 is uncovered by the patterned photoresist, the memory unit is defined as logic “1” due to implantation of the channel region 124 , to the contrary, when the gate electrode 123 is covered by the patterned photoresist, the memory unit is defined as logic “0”, because the channel region 124 cannot be implanted.

Implantation Programming is completed by implanting ions into channel region to adjust the threshold voltage. This process is performed after forming the MOS transistor, and before forming contacts or inter layer dielectrics (ILD).

As integration density is increased, reduced time and memory unit size, and increased quantity and speed of data treatment are required for fabricating Mask ROMs.

Accordingly, an object of the present invention is to provide various multi-bit memory arrays to increase memory unit density, and thereby, throughput.

To achieve this and other objects, the present invention provides a memory array, comprising a plurality of word lines, a plurality of first source/drain lines, a plurality of second source/drain lines, and a plurality of memory units. Each memory unit comprises a gate electrode coupled to one of the word lines, a first source/drain region coupled to one of the first source/drain lines or first bit lines, a second source/drain region coupled to one of the second source/drain lines or second bit lines, a first spacer between the first source/drain region and the gate electrode to store electrons or electric charges, a second spacer between the second source/drain region and the gate electrode to store electrons or electric charges.

In one embodiment of the invention, the memory array further comprises a selecting/driving circuit coupled to a plurality of word lines and a plurality of first and second bit lines of the memory units, a sensing circuit coupled to the first and the second bit lines, and a controller for executing memory operations on the memory units. The controller electrically connected to the selecting/driving and sensing circuits, receives a command from an external data bus or command bus and an address from the external address bus. Thus, the controller generates and transmits a plurality of control signals to the selecting/driving and sensing circuits based on the received command and outputs the status and data stored in the memory array based on the address. The controller is capable of performing at least one of various operating functions including an initializing operation, a reading operation, a programming operation, a program-verifying operation, an erasing operation, an erase-verifying operation, a self-testing operation and a repairing operation.

The present invention also provides another memory array, comprising a plurality of word lines, a plurality of first source/drain lines, a plurality of second source/drain lines, and a plurality of memory units. Each memory unit comprises a gate electrode coupled to one of the word lines, a first source/drain region coupled to one of the first source/drain lines or first bit lines, a second source/drain region coupled to one of the second source/drain lines or second bit lines, a programmable source/drain extended area between the gate electrode and the first or second source/drain region to store or keep electric information.

The memory array further comprises a selecting/driving circuit coupled to the word lines, the first bit lines and the second bit lines, a sensing circuit coupled to the first and the second bit lines, and a controller for executing a memory operation on the memory units. The controller coupled to the selecting/driving and sensing circuits receive a command from an external data bus or command bus and an address from the external address bus. Thus, the controller generates and transmits a plurality of control signals to the selecting/driving and sensing circuits based on the received command and outputs the status and data stored in the memory array based on the address. The controller is capable of performing at least one of various operating functions including an initializing operation, a reading operation, a self-testing operation and a repairing operation.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

For a better understanding of the invention, reference is made to a detailed description to be read in conjunction with the accompanying drawings, in which:

FIG. 1 a shows a cross section of a conventional flash memory unit during programming.

FIG. 1 b shows a cross section of a conventional flash memory unit during erasure.

FIG. 1 c shows a cross section of a conventional programmed Mask ROM.

FIG. 2 a shows a cross section of one embodiment of the multi-bit EPROM unit of the invention during a left-bit programming operation.

FIG. 2 b shows a cross section of one embodiment of the multi-bit EPROM unit of the invention during a right-bit programming operation.

FIGS. 2 c , 2 d , 2 e and 2 f show cross sections of a multi-bit Mask ROM of the invention respectively having digital states of (11), (10), (01) and (00).

FIG. 3 a shows a single multi-bit memory unit of the first embodiment of the invention.

FIG. 3 b shows a multi-bit memory array of the first embodiment of the invention.

FIG. 3 c shows a multi-bit memory array of FIG. 3 b with peripheral circuits.

FIG. 4 a shows a single multi-bit memory unit of the second embodiment of the invention.

FIG. 4 b shows a multi-bit memory array of the second embodiment of the invention.

FIG. 4 c shows a multi-bit memory array of FIG. 4 b with peripheral circuits.

FIGS. 5 a and 5 b show two single multi-bit memory units in the third embodiment of the invention.

FIG. 5 c shows a multi-bit memory array of the third embodiment of the invention.

FIG. 5 d shows a multi-bit memory array of FIG. 5 c with peripheral circuits.

FIGS. 6 a and 6 b show two single multi-bit memory units of the fourth embodiment of the invention.

FIG. 6 c shows a multi-bit memory array of the fourth embodiment of the invention.

FIG. 6 d shows a multi-bit memory array of FIG. 6 c with peripheral circuits.

FIGS. 7 a and 7 b show two single multi-bit memory units of the fifth embodiment of the invention.

FIG. 7 c shows a multi-bit memory array of the fifth embodiment of the invention.

FIG. 7 d shows a multi-bit memory array of FIG. 7 c with peripheral circuits.

FIG. 8 shows a memory system diagram of one embodiment the invention.

FIG. 2 a shows a cross section of one embodiment of the multi-bit EPROM unit of the invention during a left-bit programming operation. The multi-bit memory unit comprises a semiconductor substrate 201 having a source region and a drain region therein, a gate electrode 202 , such as a polysilicon layer, on the semiconductor substrate 201 , a gate dielectric layer 203 a , such as a gate oxide layer, between the gate electrode 202 and the semiconductor substrate 201 , a spacer 204 , such as a nitride layer, on a sidewall of the gate electrode 202 to store electrons or electric charges, an oxide layer 203 b between the spacer 204 and the gate electrode 202 , and a metal-semiconductor compound layer 205 , such as TiSi 2 , CoSi 2 or NiSi, over the gate electrode 202 and the source/drain region. The memory unit also comprises a dielectric layer, such as an oxide layer, over the semiconductor substrate 201 and the above elements, and a contact plug filled with a conductive layer in the dielectric layer to connect the source/drain region installed between gate electrodes and a subsequently formed bit line.

When a left-bit programming operation is performed on the EPROM unit, a programming gate signal, Vg-program, is applied to the gate electrode 202 via the metal-semiconductor compound layer 205 , a programming drain signal, Vd-program, is applied to the source region and the drain region is coupled to ground. In this embodiment, the EPROM unit is selected by a word line, such as WL 1 in FIG. 3 a , via a column decoder and a bit line, such as BL 3 in FIG. 3 a , via a row decoder. As the memory unit is activated, the carriers, e − , are injected and stored in a multi-layer dielectric spacer (not labeled) at the left side of the gate as shown in FIG. 2 a . The presence of charge in the dielectric spacer represents a digital state of the memory unit.

FIG. 2 b shows a cross section of one embodiment of the multi-bit EPROM unit of the invention during a right-bit program operation. When a right-bit programming operation is performed on the EPROM unit, a programming gate signal, Vg-program, is applied to the gate electrode 202 via the metal-semiconductor compound layer 205 , a programming drain signal, Vd-program, is applied to the drain region and the source region is coupled to ground. In this embodiment, the EPROM unit is selected by a word line, such as WL 1 in FIG. 3 a , via a column decoder and a bit line, such as BL 3 in FIG. 3 a , via a row decoder. As the memory unit is activated, the carriers, e − , are injected and stored in a multi-layer dielectric spacer (not labeled) at the right side of the gate as shown in FIG. 2 b . The presence of charges in the dielectric spacer represents a digital state of the memory unit. Thus, the EPROM unit of FIG. 2 a and FIG. 2 b can store 2 bits of data therein based on the left-bit and right-bit programming operation.

FIGS. 2 c , 2 d , 2 e and 2 f show cross sections of a multi-bit Mask ROM of the invention respectively having digital states of (11), (10), (01) and (00). The multi-bit memory unit comprises a semiconductor substrate 220 having a gate dielectric layer 222 a and a gate electrode 223 thereon and a source/drain extension area 221 therein under one side of the gate electrode 223 , a spacer 224 on a sidewall of the gate electrode 223 , an oxide layer 222 b between the spacer 224 and the gate electrode 223 , a source/drain region in the semiconductor substrate 220 , and a metal-semiconductor compound layer 225 over the gate electrode 223 and the source/drain region, wherein the source/drain extension area 221 is formed using a photoresist layer and the gate electrode 223 as masks formed by a code mask, and the source/drain region is formed by implanting the semiconductor substrate 220 with As or P ions using the gate electrode 223 and the spacer 224 as masks.

If the source/drain extension area 221 is not formed between the source/drain region and the gate electrode 223 , the threshold voltage of the memory unit may increase. When accessing data, if a normal voltage is applied to the gate electrode 223 , the source/drain region can not be conducted, producing merely lowered leakage current, thus the logic “ 0 ” is accessed. If the source/drain extension area 221 is formed between the source/drain region and the gate electrode 223 , the threshold voltage of the memory unit may decrease. When accessing data, if a normal voltage is applied to the gate electrode 223 , the source/drain region can be conducted, and logic “1” is accessed. Thus, the memory unit is accessed as logic “1”, when the source/drain extension 221 is formed coupled to the gate electrode 223 , and the memory unit is accessed as logic “0”, when the source/drain extension 221 is not coupled to the gate electrode 223 .

FIG. 3 a shows a single multi-bit memory unit in the first embodiment of the resent invention, FIG. 3 b shows a memory array in the first embodiment of the present invention, and FIG. 3 c shows a multi-bit memory array of FIG. 3 b with peripheral circuits.

Referring to FIG. 3 a , a semiconductor substrate (not shown) having the multi-bit memory unit shown in FIG. 2 a or 2 b is provided, with an active area 30 defined therein.

The multi-bit memory unit comprises a word line WL 1 , a first bit line BL 3 , a second bit line BL 4 , a first connection point C 1 , and a second connection point C 2 , wherein the word line is the gate electrode, and the connection points are contact plugs.

The word line WL 1 is perpendicular to the first bit line BL 3 and the second bit line BL 4 . The first bit line BL 3 is parallel to the second bit line BL 4 , and the first bit line BL 3 and the second bit line BL 4 are separated into two portions by the word line WL 1 . The first connection point C 1 electrically connects to the first bit line BL 3 , and the second connection point C 2 electrically connects to the second bit line BL 4 , wherein the first connection point C 1 and the second connection point C 2 are located on the first and second source/drain regions separated by the word line WL 1 . The active area 30 is under the above elements. The active area 30 is rectangular, and the first connection point C 1 and the second connection point C 2 are respectively located on the diagonal position thereof.

Referring to FIG. 3 b , the memory array comprises word lines WL 1 , WL 2 , and WL 3 , bit lines BL 1 , BL 2 , BL 3 , BL 4 , BL 5 , and BL 6 , connection points C 1 and C 2 , memory unit 301 , and active areas 30 , wherein the memory unit 301 is the single multi-bit memory unit shown in FIG. 3 a . Each connection point can be jointly used by adjacent memory units, for example, the second connection point C 2 is jointly used by the memory unit 301 and its adjacent memory unit to form the electrical connection, as shown in FIG. 3 c.

FIG. 3 c shows a multi-bit memory array of FIG. 3 b with peripheral circuits.

The memory array is driven by word line drivers, such as WL-1 Driver, and bit line drivers, such as BL-1 Driver. The word line driver is coupled to one word line and when the word line driver receive a control signal from the column decoder, the word line driver enables a selected column of memory units. The bit line driver is coupled to one bit line, wherein the bit line may be a first bit line or a second bit line. When data is written to or read from the memory array, an address is transmitted to the column decoder and the row decoder to enable the corresponding word line driver and bit line driver to activate the selected memory unit. The amplifier Amp further senses the output signal of the data in a memory unit to a predetermined electrical level and the data of the memory unit is temporarily stored in the output buffer.

FIG. 4 a shows a single multi-bit memory unit of the second embodiment of the invention, FIG. 4 b shows a memory array of the second embodiment of the invention, and FIG. 4 c shows a multi-bit memory array of FIG. 4 b with peripheral circuits.

Referring to FIG. 4 a , a semiconductor substrate (not shown) having the multi-bit memory unit shown in FIG. 2 a or 2 b is provided, with an active area 40 defined therein.

The multi-bit memory unit comprises a word line WL 1 , a first bit line BL 3 , a second bit line BL 4 , a first connection point C 1 , and a second connection point C 2 , wherein the word line is the gate electrode, and the connection points are contact plugs.

The word line WL 1 is perpendicular to the first bit line BL 3 and the second bit line BL 4 . The first bit line BL 3 is parallel to the second bit line BL 4 , and the first bit line BL 3 and the second bit line BL 4 are separated into two portions by the word line WL 1 . The first connection point C 1 electrically connects to the first bit line BL 3 , and the second connection point C 2 electrically connects to the second bit line BL 4 , wherein the first connection point C 1 and the second connection point C 2 are located on the first and second source/drain regions separated by the word line WL 1 . The active area 40 is under the above elements. The active area 40 is rectangular, and the first connection point C 1 and the second connection point C 2 are respectively located on two ends of the active area 40 . The included angle between the active area 40 and the word line WL 1 is less than 90°.

Referring to FIG. 4 b , the memory array comprises word lines WL 1 , WL 2 , WL 3 , and WL 4 , bit lines BL 1 , BL 2 , BL 3 , and BL 4 , connection points C 1 and C 2 , memory unit 401 , and active areas 40 , wherein the memory unit 401 is the single multi-bit memory unit shown in FIG. 4 a . Each connection point can be jointly used by adjacent memory units, for example, the second connection point C 2 is jointly used by the memory unit 401 and its adjacent memory unit to form the electrical connection, as shown in FIG. 4 c.

FIG. 4 c shows a multi-bit memory array of FIG. 4 b with peripheral circuits.

The memory array is driven by word line drivers, such as WL-1 Driver, and bit line drivers, such as BL-1 Driver. The word line driver is coupled to one word line and when the word line driver receive a control signal from the column decoder, the word line driver enables a selected column of memory units. The bit line driver is coupled to one bit line, wherein the bit line may be a first bit line or a second bit line. When data is written to or read from the memory array, an address is transmitted to the column decoder and the row decoder to enable the corresponding word line driver and bit line driver to activate the selected memory unit. The amplifier Amp further senses the output signal of the data in a memory unit to a predetermined electrical level and the data of the memory unit is temporarily stored in the output buffer.

FIGS. 5 a and 5 b show two single multi-bit memory units of the third embodiment of the invention, FIG. 5 c shows a memory array of the third embodiment of the invention, and FIG. 5 d shows a multi-bit memory array of FIG. 5 c with peripheral circuits.

Referring to FIGS. 5 a and 5 b , a semiconductor substrate (not shown) having a multi-bit memory unit shown in FIG. 2 a or 2 b is provided, with an active area 50 defined therein.

Referring to FIG. 5 a, one of the two multi-bit memory units is disclosed as follows. The multi-bit memory unit comprises a word line WL 1 , a first bit line BL 3 , a second bit line BL 4 , a first connection point C 1 , and a second connection point C 2 , wherein the word line is the gate electrode, and the connection points are contact plugs.

The word line WL 1 is perpendicular to the first bit line BL 3 and the second bit line BL 4 . The first bit line BL 3 is parallel to the second bit line BL 4 , and the first bit line BL 3 and the second bit line BL 4 are separated into two portions by the word line WL 1 . The first connection point C 1 electrically connects to the first bit line BL 3 , and the second connection point C 2 electrically connects to the second bit line BL 4 , wherein the first connection point C 1 and the second connection point C 2 are located on the first and second source/drain regions separated by the word line WL 1 . The active area 50 is under the above elements. The active area 50 is rectangular, and the first connection point C 1 and the second connection point C 2 are respectively located at two ends of the active area 50 . The included angle between the active area 50 and the word line WL 1 is less than 90°.

Referring to FIG. 5 b , another multi-bit memory unit is disclosed as follows.

The multi-bit memory unit comprises a word line WL 2 , a first bit line BL 3 , a second bit line BL 4 , a second connection point C 2 , and a third connection point C 3 , wherein the word line is the gate electrode, and the connection points are contact plugs.

The word line WL 2 is perpendicular to the first bit line BL 3 and the second bit line BL 4 . The first bit line BL 3 is parallel to the second bit line BL 4 , and the first bit line BL 3 and the second bit line BL 4 are segregated to two portions by the word line WL 2 . The second connection point C 2 electrically connects to the first bit line BL 3 , and the third connection point C 3 electrically connects to the second bit line BL 4 , wherein the second connection point C 2 and the third connection point C 3 are located on the first and second source/drain regions separated by the word line WL 2 . The active area 50 comprises the above elements. The active area 50 is rectangular, and the second connection point C 2 and the third connection point C 3 are respectively located on two ends of the active area 50 . The included angle between the active area 50 and the word line WL 2 is less than 90°.

Referring to FIG. 5 c, the memory array comprises word lines WL 1 , WL 2 , and WL 3 , bit lines BL 1 , BL 2 , BL 3 , BL 4 , BL 5 , and BL 6 , connection points C 1 , C 2 , and C 3 , memory unit 501 , and active areas 50 , wherein the memory unit 501 is the single multi-bit memory unit shown in FIG. 5 a or 5 b . Each connection point can be jointly used by four adjacent memory units, for example, the second connection point C 2 is jointly used by the memory unit 501 and its adjacent three memory units to form the electrical connection, as shown in FIG. 5 d.

FIG. 5 d shows a multi-bit memory array of FIG. 5 c with peripheral circuits.

The memory array is driven by word line drivers, such as WL-1 Driver, and bit line drivers, such as BL-1 Driver. The word line driver is coupled to one word line and when the word line driver receive a control signal from the column decoder, the word line driver enables a selected column of memory units. The bit line driver is coupled to one bit line, wherein the bit line may be a first bit line or a second bit line. When data is written to or read from the memory array, an address is transmitted to the column decoder and the row decoder to enable the corresponding word line driver and bit line driver to activate the selected memory unit. The amplifier Amp further senses the output signal of the data in a memory unit to a predetermined electrical level and the data of the memory unit is temporarily stored in the output buffer.

FIGS. 6 a and 6 b show two single multi-bit memory units of the fourth embodiment of the invention, FIG. 6 c shows a memory array of the fourth embodiment of the invention, and FIG. 6 d shows a multi-bit memory array of FIG. 6 c with peripheral circuits.

Referring to FIGS. 6 a and 6 b , a semiconductor substrate (not shown) having a multi-bit memory unit shown in FIG. 2 a or 2 b is provided, with an active area 60 defined therein.

Referring to FIG. 6 a , one of the two multi-bit memory units is disclosed in the following. The multi-bit memory unit comprises a word line WL 1 , a first bit line BL 3 , a second bit line BL 4 , a first connection point C 1 , and a second connection point C 2 , wherein the word line is the gate electrode, and the connection points are contact plugs.

The word line WL 1 is perpendicular to the first bit line BL 3 and the second bit line BL 4 . The first bit line BL 3 is parallel to the second bit line BL 4 , and the first bit line BL 3 and the second bit line BL 4 are separated into two portions by the word line WL 1 . The first connection point C 1 electrically connects to the first bit line BL 3 , and the second connection point C 2 electrically connects to the second bit line BL 4 , wherein the first connection point C 1 and the second connection point C 2 are located on the first and second source/drain regions separated by the word line WL 1 . The active area 60 is under the above elements. The active area 60 is Z-shaped, comprising a main area and two extended areas, with the two extension areas perpendicularly connecting to two ends of the main area respectively. A first source/drain region is formed in one of the extended areas and a part of the main area, and a second source/drain region is formed in another extended area and a part of the main area. Therefore, the first connection point C 1 corresponding to the first source/drain region and the second connection point C 2 corresponding to the second source/drain region are respectively located on the terminal of the extension areas.

Referring to FIG. 6 b , another multi-bit memory unit is disclosed as follows. The multi-bit memory unit comprises a word line WL 2 , a second bit line BL 4 , a third bit line BL 5 , a second connection point C 2 , and a third connection point C 3 , wherein the word line is the gate electrode, and the connection points are contact plugs.

The word line WL 2 is perpendicular to the second bit line BL 4 and the third bit line BL 5 . The second bit line BL 4 is parallel to the third bit line BL 5 , and the second bit line BL 4 and the third bit line BL 5 are separated to two portions by the word line WL 2 . The second connection point C 2 electrically connects to the second bit line BL 4 , and the third connection point C 3 electrically connects to the third bit line BL 5 , wherein the second connection point C 2 and the third connection point C 3 are located on different sides separated by the word line WL 2 . The active area 60 comprises the above elements. The active area 60 is Z-shaped, comprising a main area and two extended areas, with the two extended areas perpendicularly connecting to two ends of the main area respectively. The second connection point C 2 and the third connection point C 3 are respectively located at the terminus of the extended areas.

Referring to FIG. 6 c , the memory array comprises word lines WL 1 , WL 2 , and WL 3 , bit lines BL 1 , BL 2 , BL 3 , BL 4 , BL 5 , BL 6 , and BL 7 , connection points C 1 , C 2 , and C 3 , memory unit 601 , and active areas 60 , wherein the memory unit 601 is the single multi-bit memory unit shown in FIG. 6 a or 6 b . Each connection point can be jointly used by four adjacent memory units, for example, the second connection point C 2 is jointly used by the memory unit 601 and its adjacent three memory units to form the electrical connection, as shown in FIG. 6 c.

FIG. 6 d shows a multi-bit memory array of FIG. 6 c with peripheral circuits. The memory array is driven by word line drivers, such as WL-1 Driver, and bit line drivers, such as BL-1 Driver. The word line driver is coupled to one word line and when the word line driver receive a control signal from the column decoder, the word line driver enables a selected column of memory units. The bit line driver is coupled to one bit line, wherein the bit line may be a first bit line or a second bit line. When data is written to or read from the memory array, an address is transmitted to the column decoder and the row decoder to enable the corresponding word line driver and bit line driver to activate the selected memory unit. The amplifier Amp further senses the output signal of the data in a memory unit to a predetermined electrical level and the data of the memory unit is temporarily stored in the output buffer.

FIGS. 7 a and 7 b show two single multi-bit memory units of the fifth embodiment of the invention, FIG. 7 c shows a memory array of the fifth embodiment of the invention, and FIG. 7 d shows a multi-bit memory array of FIG. 7 c with peripheral circuits.

Referring to FIGS. 7 a and 7 b , a semiconductor substrate (not shown) having a multi-bit memory unit shown in FIG. 2 a or 2 b is provided, with an active area 70 defined therein.

Referring to FIG. 7 a , the two multi-bit memory units are disclosed as follows. The multi-bit memory unit comprises a word line WL 1 or WL 2 , a first bit line BL 3 , a first connection point C 1 , wherein the word line is the gate electrode, and the connection point is a contact plug.

The word line WL 1 or WL 2 is perpendicular to the first bit line BL 3 , thus the first bit line BL 3 is separated to two portions thereby. The first connection point C 1 is located on one of the first and second source/drain regions separated sides by the word line WL 1 or WL 2 , and electrically connects to the first bit line BL 3 . The active area 70 is under the above elements. The active area 70 is T-shaped, comprising a main area and an extended area, with one end of the main area connecting to the middle of the extended area. The main area is parallel to the first bit line BL 3 (the first source line) corresponding thereto. The extended area is parallel to the word line corresponding thereto.

Referring to FIG. 7 c , the memory array comprises word lines WL 1 and WL 2 , bit lines BL 1 , BL 2 , BL 3 , BL 4 , BL 5 , and BL 6 , connection points C 1 , C 111 , and C 112 , memory unit 701 , and active areas 70 , wherein the memory unit 701 is the single multi-bit memory unit shown in FIG. 7 a or 7 b . Each connection point corresponding to the drain area can be jointly used by two adjacent memory units in the same row, and the source area installed on the same column can be jointly used by each memory unit in the same column. Additionally, memory units connect to the additional metal line M 11 or M 12 by the connection point C 111 or C 112 . Referring to FIG. 7 d , the first connection point C 1 is jointly used by the memory unit 701 and its adjacent memory unit in the same row to form the electrical connection, and the source area, such as source- 1 , installed on the same column can be jointly used by each memory unit in the same column. Additionally, memory units connect to potential switch through the additional metal line M 11 or M 12 by the connection point C 111 or C 112 as common sources. Furthermore, the operation of the circuit of FIG. 7 d is similar to the operation of FIG. 3 c , FIG. 4 c , FIG. 5 d and FIG. 6 d.

FIG. 8 shows a memory circuit diagram of a six embodiment of the invention. Referring FIG. 8 , the memory array may be the memory array of the first, the second, the third, the fourth and the fifth embodiments, and peripheral circuits including a selecting/driving circuit, a plurality of first and second bit lines, a sensing circuit and a controller are disclosed. The selecting/driving circuit is coupled to a plurality of word lines and a plurality of first and second bit lines of memory units. The sensing circuit is coupled to the first and the second bit lines through the selecting/driving circuit to amplify the signals of the data in the memory units. The controller performs a memory operation, such as reading, writing, on the memory units. The controller coupled to the selecting/driving and sensing circuits receive a command from an external data bus or command bus and an address from the external address bus. The controller generates a plurality of control signals to the selecting/driving and sensing circuits based on the received command, thus, the selecting/driving circuit selects memory units based on the address. When the controller receives a write command, the controller writes the data to the corresponding memory units selected by the selecting/driving circuit. When the controller receives a read command, the sensing circuit reads the data of the corresponding memory units via the bit lines. The controller is further capable of performing at least one of various operating functions including an initializing operation, a reading operation, a programming operation, a program-verifying operation, an erasing operation, an erase-verifying operation, a self-testing operation and a repairing operation.

The operations described in this disclosure, such as reading operation, programming operation and others, can be applied to the memory unit of the six embodiments, and the detailed operations are described as following. The initializing operation comprises selecting at least one memory unit, applying a first initializing signal to a word line of the memory unit, applying a second initializing signal to a first bit line of the memory unit, and applying a third initializing signal to a second bit line of the memory unit when the output current of the memory unit is lower than a predetermined current level. The reading operation comprises selecting one memory unit, applying a first reading signal to the word line of the memory unit, applying a second reading signal to one of the first and the second bit lines of the memory unit, and coupling another one of the first and the second bit lines of the memory unit to the ground or the same potential as the semiconductor substrate. The programming operation comprises selecting at least one memory unit, applying a first programming signal to the word line of the memory unit, applying a second programming signal to one of the first and the second bit lines of the memory unit, and coupling another one of the first and the second bit lines of the memory unit to the ground or the same potential as the semiconductor substrate. The program-verifying operation comprises selecting at least one memory unit, sensing the output current of the memory unit, and applying a programming operation to the memory unit if the output current is higher than a predetermined current level. The erasing operation comprises selecting at least one memory unit, applying a first erasing signal to the word line of the memory unit, and applying a second erasing signal to at least one of the first and the second bit lines of the memory unit. The erase-verifying operation comprises selecting at least one memory unit, sensing the output current of the memory unit, and applying a erasing operation to the memory unit if the output current is lower than a predetermined current level. The self-testing operation comprises selecting at least one memory unit, applying a first self-testing signal to a word line of the memory unit, applying a second self-testing signal to the first bit line of the memory unit, applying a third self-testing signal to the second bit line of the memory unit, and when the output current of the memory unit is out of a predetermined current range, the controller outputs an error signal. The repairing operation comprises switching off a damaged word line or a damaged bit line, and selecting and switching on a redundant word line or a redundant bit line for replacing the damaged word line or the damaged bit line.

The invention provides two blocks in a memory unit to store data, that is, two sets of data can be programmed or erased in a single transistor. The maximum set count of data programmed or erased each time is twice the number of memory units.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.