Inventor
Tzu-Shih Yen
Inventor
Hsinchu, TW
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1031%
H10DInorganic electric semiconductor devices22%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H10BElectronic memory devices10%
H01LSemiconductor devices8%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
C11DDetergent compositions2%
G11CStatic stores2%
PatentTitleYear
9,209,278'Replacement source/drain finFET fabrication'20159,159,810'Doping a non-planar semiconductor device'20159,006,065'Plasma doping a non-planar semiconductor device'20158,871,584'Replacement source/drain finFET fabrication'20148,685,825'Replacement source/drain finFET fabrication'20147,457,154'High density memory array system'20086,423,646'Method for removing etch-induced polymer film and damaged silicon layer from a silicon surface'20026,376,384'Multiple etch contact etching method incorporating post contact etch etching'20026,306,759'Method for forming self-aligned contact with liner'20016,278,189'High density integrated circuits using tapered and self-aligned contacts'20016,265,296'Method for forming self-aligned contacts using a hard mask'20016,235,621'Method for forming a semiconductor device'20016,140,240'Method for eliminating CMP induced microscratches'20006,136,661'Method to fabricate capacitor structures with very narrow features using silyated photoresist'20006,124,192'Method for fabricating ultra-small interconnections using simplified patterns and sidewall contact plugs'20006,037,216'Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process'20005,994,228'Method of fabricating contact holes in high density integrated circuits using taper contact and self-aligned etching processes'19995,990,018'Oxide etching process using nitrogen plasma'19995,962,195'Method for controlling linewidth by etching bottom anti-reflective coating'19995,904,154'Method for removing fluorinated photoresist layers from semiconductor substrates'19995,899,747'Method for forming a tapered spacer'19995,895,740'Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers'19995,780,338'Method for manufacturing crown-shaped capacitors for dynamic random access memory integrated circuits'19985,688,713'Method of manufacturing a DRAM cell having a double-crown capacitor using polysilicon and nitride spacers'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2002Patents assigned to VANGUARD INT SEMICONDUCT CORP (18)· patent assignee history
1997–2008Based in Taipei, TW· patent location history
1999–2015Based in Hsinchu, TW· patent location history
2008Patents assigned to APPLIED INTELLECTUAL PROPERTIE (1)· patent assignee history
2014–2015Patents assigned to ADVANCED ION BEAM TECH INC (5)· patent assignee history
2014–2015Patents assigned to TANG DANIEL (3)· patent assignee history
2014–2015Patents assigned to YEN TZU-SHIH (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| VANGUARD INT SEMICONDUCT CORP | 18 | 1997–2002 |
| ADVANCED ION BEAM TECH INC | 5 | 2014–2015 |
| TANG DANIEL | 3 | 2014–2015 |
| YEN TZU-SHIHself | 3 | 2014–2015 |
| APPLIED INTELLECTUAL PROPERTIE | 1 | 2008 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 15 | 1999–2015 |
| Taipei, TW | 9 | 1997–2008 |