Delta-sigma modulators with double sampling input networks and systems using the same

The present invention relates in general to mixed-signal circuit techniques, and in particular, to delta-sigma modulators with double sampling input networks and systems using the same.

Delta-sigma modulators are particularly useful in digital to analog and analog to digital converters (DACs and ADCs). Using oversampling, a delta-sigma modulator spreads the quantization noise power across an oversampling frequency band, which is typically much greater than the input signal bandwidth. Additionally, the delta-sigma modulator performs noise shaping by acting as a lowpass filter to the input signal and a highpass filter to the noise; hence, most of the quantization noise power is thereby shifted out of the signal band.

The typical delta-sigma modulator includes a summer summing the input signal with negative feedback, a linear filter, quantizer and a feedback loop with a digital to analog converter coupling the quantizer output and the inverting input of the summer. In a first order modulator, the linear filter comprises a single integrator stage while the filter in a higher order modulator comprises a cascade of a corresponding number of integrator stages. The quantizer can be either a one-bit or a multiple-bit quantizer. Higher-order modulators have improved quantization noise transfer characteristics over those of lower order, but stability becomes a more critical design factor as the order increases.

Switched-capacitor filters/integrators are useful in a number of applications including the integrator stages in delta-sigma modulators. Generally, a basic differential switched-capacitor integrator samples the input signal, and often a reference voltage as well, onto a corresponding pair of sampling capacitors during the sampling (charging) phase. During the following charge transfer phase, the charge on the sampling capacitor is transferred at the summing nodes of an operational amplifier to a corresponding pair of integrator capacitors in the amplifier feedback loops. The operational amplifier drives the integrator output.

Noise performance is an important design constraint in delta-sigma modulator design. Noise can result from a number of different factors, including parasitic capacitances and timing mismatches. Settling time is another constraint on noise performance when switched-capacitor integrator stages are utilized. Generally, sufficient time must be provided during the charge transfer phases to allow the voltages at the opamp inputs to settle to their steady state values. This time requirement in turn limits the switching speed of the integrator stage, and consequently the operating speed of the overall system, or alternatively limits noise performance.

Reducing input impedance of a switched capacitor integrator stage is a further important design consideration. A higher input impedance will allow the integrator stage to be driven by a smaller, less complicated, and/or less expensive driver circuit.

Hence, for applications requiring low-noise delta-sigma modulation, improved techniques for reducing noise are required. Another goal is the reduction of the input impedance at the input sampling network, such that smaller, less complicated, external drivers may be utilized. Finally, improvement of modulator performance at high frequencies is an additional design consideration, which should be addressed.

In one representative embodiment of the principles of the present invention, a method is disclosed for sampling an input signal in a delta-sigma modulator having at least an integrator stage and a feedback digital-to-analog converter (DAC) stage and which includes sampling an input signal at a sampling rate by alternately utilizing two sampling capacitors during two sampling cycles such that the two sampling capacitors are utilized at half of the sampling rate. Samples from the two sampling capacitors are summed at the sampling rate at an intermediate node with feedback samples provided by the feedback DAC stage at the sampling rate to generate output samples which are output from integrator stage at the sampling rate.

In sum, by alternatively switching each input between each sampling capacitor at half the modulator feedback loop rate, the impedance of the sampling network/integrator stage is approximately doubled. In turn, the external driver circuitry driving the stage may be made smaller and less expensive. Additionally, by alternating each input between sampling capacitors during odd and even cycles, the sampling capacitors must only be charged proportional to the relatively small change in the input voltage, rather than charged proportional to the full input voltage swing. Consequently, each sampling phase of each cycle may be shortened, and each charge transfer phase lengthened, such that power consumption and size of the first integrator stage in the cascade are reduced. Additionally, with the sampling capacitors being charged with a reduced voltage swing, noise and distortion are reduced. Finally, in a multiple stage delta-sigma modulator, decreasing the size and power of the first stage in the cascade allows for a proportional reduction in the size and power of the following stages.

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a high level operational block diagram of an analog to digital converter suitable for illustrating the application of the inventive principles;

FIG. 2 is a operational block diagram of an exemplary 5th order delta-sigma modulator suitable for use in circuits and systems such as the analog to digital converter shown in FIG. 1 ;

FIG. 3A is a more detailed operational block diagram of a switched-capacitor sampling/input integrator stage of the delta-sigma modulator shown in FIG. 2 ;

FIG. 3B is a conceptual timing diagram illustrating exemplary operations of the switched-capacitor stage shown in FIG. 3A according to the principles of the present invention; and

FIG. 4 is a conceptual timing diagram illustrating exemplary operations of the feedback loop digital to analog converter (DAC) of the delta-sigma modulator shown in FIG. 2 .

The principles of the present invention and their advantages are best understood by referring to the illustrated embodiment depicted in FIGS. 1–4 of the drawings, in which like numbers designate like parts.

FIG. 1 is a high-level operational block diagram of a single-chip audio analog-to-digital (A/D) 100 suitable for practicing the principles of the present invention. A/D converter 100 is only one of a number of possible applications employing delta-sigma data converters. Other examples include digital to analog converters (DACs) and Codecs.

A/D converter 100 includes two conversion paths for converting left and right channel analog audio data respectively received at left and right analog differential inputs AINL+/− and AINR+/−. The analog input signals are respectively passed through input gain stages 101 a – 101 b and then to delta-sigma analog to digital converters (ADCs) 200 a – 200 b , which will be described in detail in conjunction with FIG. 2 . The digital outputs of delta-sigma ADCs 200 a – 200 b are passed through corresponding decimation filters 107 a – 107 b , which reduces the sample rate, and high pass filters 108 a – 108 b . Delta-sigma ADCs 200 a – 200 b sample the analog-signal at the oversampling rate and output digital data, in either single-bit or multiple-bit form depending on the quantization, at the oversampling rate. The resulting quantization noise is shaped and generally shifted to frequencies above the audio band.

The resulting left and right channel digital audio data are output through a single serial port SDOUT of serial output interface 109 , timed with serial clock SCLK and left-right clock LRCK in accordance with the Digital Interface Format (DIF). The SCLK and LRCK clocks can be generated externally and input to converter 100 or can be generated on-chip, along with the associated data, in response to a received master clock MCLK.

FIG. 2 is an exemplary 5th order feedforward delta-sigma modulator 200 , which is a suitable modulator that can be used in delta-sigma ADC 200 a or 200 b . Delta-sigma modulator 200 comprises an input summer 201 and five (5) integrator stages 202 a – 202 e . Delta-sigma modulator 200 is a weighted feed-forward design in which the outputs of each of the integrator stages are passed through a gain stage (amplifier) 203 a – 203 e to an output summer 204 . Amplifiers 203 a – 203 e allow the outputs of the integrator stages to be weighted at the input of summer 204 . The output from summer 204 is quantized by a multiple-bit quantizer 205 , which generates the multiple-bit digital output signal. Additionally, the output from quantizer 205 is fed back to the inverting input of summer 201 through dynamic element matching (DEM) circuitry 206 and multiple-bit digital to analog converter (DAC) 207 . (A 5th order feed-forward design was selected for discussion purposes; in actual implementation; the order as well as the configuration of the modulator will vary. A general discussion of delta-sigma modulator topologies can be found in the literature, for example, in Norsworthy et al., Delta - Sigma Data Converters, Theory, Design and Simulation , IEEE Press, 1996).

FIG. 2 also shows an additional feed-forward path, including amplifier 208 , between modulator input 210 and summer 204 . The gain of amplifier stage 208 is preferably:

Gain=(1/Quantizer gain)*(1/Multi-Bit DAC gain)

The purpose of this additional feed-forward path is to cancel as much of the input signal energy from the delta-sigma loop as possible. Consequently, most of the voltage swing within the modulator will be quantization noise. In turn, the design constraints on the sub-circuits within modulator 200 can be relaxed. For example, the first integrator stage 202 a is typically the major contributor to the noise performance of the entire modulator. This feed-forward technique results in less signal energy at the outputs of the integrator stages and hence such parameters as the stage opamp DC gain can be reduced. In turn, the power consumption of the device as well as the die size can be reduced.

FIG. 3A is an electrical schematic diagram of a double sampling input sampling network/integrator 300 embodying the principles of the present invention. In one representative application, input sampling network/integrator 300 is advantageously utilized as input summer 201 and first stage 202 a of delta-sigma modulator 200 of FIG. 2 , although its utility is not limited thereto.

Input sampling network/integrator 300 of FIG. 3A generally operates in odd and even cycles, with each cycle including a charge sampling phase φ 1 and a charge transfer phase φ 2 . The odd and even cycles are performed at a rate which is at one-half (½) of the loop rate of delta-sigma modulator 200 , as defined by the MCLK signal. The sampling rate f S for discussion purposes is defined as the rate at which samples are streamed through integrator stages 202 a – 202 e , amplifiers 203 a – 203 e , summer 204 , multiple bit quantizer 205 , and DEM 206 . In the illustrated embodiment, the odd and even operating cycles of integrator stage 300 are performed at a rate of approximately half the sampling rate f S .

Generally, during sampling phase φ 1 of each odd cycle, charges proportional to the voltages AINL− and AINL+ at the inputs to input sampling network/integrator 300 are respectively sampled onto cross-coupled sampling capacitors 301 a and 301 b . During the charge transfer phase φ 2 of each odd cycle, the input voltages AIN+ and AINL− are coupled to the input plates of sampling capacitors 301 a and 301 b , such that the input plate to sampling capacitor 301 a is coupled to the positive input AINL+ and the input plate to sampling capacitor 301 b is coupled to the negative input AIN−. Consequently the charges sampled onto sampling capacitors 301 a and 301 b are respectively forced onto integration capacitors 302 a and 302 b.

During the sampling phase φ 1 of the immediately following even cycle, the inputs AIN+ and AINL− remain coupled to sampling capacitors 301 a and 301 b , respectively, such that a charge proportional to the voltage at the positive input AIN+ is sampled on to sampling capacitor 301 a and charge proportional to the voltage at the negative input AINL− is sampled onto capacitor 301 b . During the charge transfer phase of each even cycle, the output plates of sampling capacitors 301 a – 301 b are cross-coupled such that the charge on sampling capacitors 301 a is transferred to integration capacitor 302 b and the charge on sampling capacitor 301 b is transferred to integration capacitor 302 a . After the completion of the current even cycle, the next odd cycle is performed, as previously discussed. In the illustrated embodiment, a given sampling capacitor 301 a or 301 b is sampled from a given input AINL+ and AINL− every four (4) periods of the MCLK signal.

At the same time, charges from the outputs DAC+ and DAC− of DAC 207 of FIG. 2 are transferred respectively to the summing nodes of opamp 303 during every odd and even cycle. The resulting summed charges at the summing nodes of opamp 303 are then output from sampling/integrator stage 303 at the full modulator loop rate.

Advantageously, by performing the odd and even cycles at half the sampling rate f S , the input impedance into integrator stage 300 approximately doubles. Additionally, by alternately sampling charge onto sampling capacitors 301 a and 301 b from the inputs AIN+ and AINL−, the amount of charge which must be sampled onto each sampling capacitor 301 a and 301 b during a given odd or even phase is limited to the charge proportional to the change in voltage at the inputs AIN+ and AINL− between sampling phases, along with a small switching glitch. At high sampling frequencies, this difference in voltages is small. As a result, the time of each sampling phase φ 1 of each odd or even cycle may be shortened and the corresponding charge transfer phase φ 2 of each odd or even cycle may be lengthened. Advantageously, longer charge transfer phases φ 2 allow the transistors involved in the charge transfer operations to be smaller thereby reducing overall die area and power consumption. Furthermore, the smaller voltage differences sampled during sampling phases φ 1 reduce the charge kick on the buffers controlling the common mode voltage V CM .

The specific operation of exemplary input sampling network/integrator 300 can now be described in reference to the timing diagram of FIG. 3B . In FIG. 3B , the index “I” stands for signals related to operations of integrator stage 300 , the indices “E” and “O” correspond respectively for even and odd cycles, and the indices “R” and “F” correspond respectively to rough and fine subphases. Thus, for example, the signal φ 2r — E controls the rough subphase of charge transfer phase (φ 2 ) for an even cycle.

At the rising edge of the MCLK signal at time t 0 , the control signal φ 1 — I closes switches 304 a and 304 b . At the same time, for the odd cycle, the control signal φ 1 — O closes switches 305 a and 305 b such that the output plates of sampling capacitors 301 a and 301 b are connected to the common mode voltage V CM . During a short overlap period between time t 0 and t 1 the control signal φ 1 — E is also active, such that switches 307 a and 307 b also close. With switches 304 a – 304 b , 305 a – 305 b , and 307 a – 307 b all closed during the overlap period, the time required to settle the output plates of capacitors 301 a and 301 b is advantageously shortened.

The control signal xφ 2r — E , which is active at time t 0 , closes switches 306 a and 306 b such that capacitor 301 a charges from input AINL− and capacitor 301 b charges from the AIN+ input. During sampling phase φ 1 — O the control signals φ 2r — 0 and φ 2r — E are inactive, such that switches 308 a – 308 b and 309 a and 309 b are open. Shortly after time t 1 , the control signals φ 1 — I and xφ 2r — E transition to an inactive (low) state.

At time t 2 , at the next rising edge of the MCLK signal, the control signals φ 1 — O , φ 2r — O , and φ 2 — I are active, such that sampling capacitors 301 a and 301 b are respectively coupled to integration capacitors 302 a and 302 b through switches 305 a and 305 b . The control signal φ 1 — I is inactive such that switches 304 a and 304 b open. The rough charge transfer period of charge transfer phase φ 2 for the odd cycle, begins with the activation of the control signal φ 2r — 0 , which closes switches 308 a and 308 b . Rough buffer 310 a then charges the input plate to sampling capacitor 301 a from the AIN+ input to start forcing charge on sampling capacitor 301 a onto integration capacitor 302 a . Similarly, rough buffer 310 b charges the input plate of sampling capacitor 301 b from the AINL− input to start forcing charge from a sampling capacitor 301 b onto integration capacitor 302 b.

Shortly after time t 2 , the control signal φ 2r — O transitions to an inactive state and the control signal xφ 2r — O transitions to an active high state, such that switches 308 a and 308 b open and switches 312 a and 312 b close to start the fine charge period of the transfer phase. During the fine charge transfer phase, the input plates of sampling capacitors 301 a and 301 b are directly charged from the AIN+ and AINL− inputs, respectively, through switches 312 a and 312 b , under the control of the xφ 2r — O signal.

While the control signal is φ 2 — D active, during both the odd and even transfer phases, the charge from DAC 200 outputs DAC+ and DAC− from FIG. 2 are transferred to integration capacitors 302 a and 302 b , as discussed further below.

The even cycle begins at time t 4 , when the signals φ 1 and φ 1 — E are in an active state thereby closing switches 304 a – 304 b and 307 a – 307 b such that the output plates of sampling capacitors 301 a and 301 b are brought to the common mode voltage V CM . During a short overlap period at the start of the even cycle, between time t 3 and time t 4 , the signal φ 1 — O remains active and switches 305 a and 305 b remain closed to improve the settling time of the voltage at the output plates of sampling capacitors 301 a and 301 b.

The signal xφ 2 — O is active at time t 4 , such that switches 312 a and 312 b remain closed such that sampling capacitor 301 a charges from the AIN+ input and sampling capacitor 301 b charges from the AINL− input. Advantageously, the only charging which is required at the input plates of sampling capacitors 301 a and 301 b is the difference between the charge remaining on sampling capacitors 301 a and 301 b at time t 3 , at the end of the preceding odd cycle, and a charge proportional to the voltages at the inputs AIN+ and AINL− at time t 4 . Additionally, the amount of charge being sampled onto sampling capacitors 301 a and 301 b may include charge required to compensate for switching glitches caused by the capacitances of the various switches in input sampling network/integrator 300 . Between time t 5 and time t 6 , the sampling phase of the even cycle completes. In particular, the signals φ 2r — O and φ 1 — I transition to an inactive state such that switches 304 a – 304 b and 312 a – 312 b open.

The charge transfer phase of the even cycle begins shortly before time t 6 with the rough transfer of charge from sampling capacitor 301 a to cross-coupled integration capacitor 302 b through switch 307 a and from sampling capacitor 301 b through switch 307 b to cross-coupled integration capacitor 302 a . Specifically, during the rough portion of the charge transfer phase φ 2 of the even cycle, the signals φ 2 — I and φ 2r — E , are both in an active state and the control signal xφ 2r — E is in an inactive state. Thus, the input plate of sampling capacitor 301 a charges from the AIN+ input through switch 309 a and rough buffer 310 a to force charge onto cross-coupled integration capacitor 302 b . Similarly, the input plate of sampling capacitor 301 b charges from the AINL− input through rough buffer 310 b to force the charge sampled onto sampling capacitor 301 a during the sampling phase of the even cycle onto cross coupled integration capacitor 302 a.

During the fine portion of the charge transfer phase of the even cycle, at time t 7 , the control signal φ 2 — E becomes inactive and the control signal Xφ 2r — E becomes active, such that the input plate of capacitor 301 a charges directly from the AINL− input through switch 306 b and the input plate of sampling capacitor 301 b charges directly from the AIN+ input through switch 306 a , to complete the charge transfer from sampling capacitors 301 a and 301 b to cross-coupled integration capacitors 302 b and 302 a.

The odd and even cycles repeat in a similar fashion while integrator 300 is operating. For example, the next odd cycle begins at time t 8 . Hence, in the illustrated embodiment, each odd and each cycle is approximately two (2) periods of the MCLK signal long, although a given sampling capacitor 301 a or 301 b is only charged from a given input AIN+ or AIN− approximately every four (4) periods of the MCLK signal. At the same time, charge is transferred from DAC 207 outputs DAC+ and DAC— of FIG. 2 to the intermediate nodes at the inputs to switches 311 a and 311 b , every two (2) periods of the MCLK signal, generally as follows.

FIG. 4 is a timing diagram illustrating the transfer of charge from DAC 207 outputs DAC+ and DAC−. In FIG. 4 , the index “D” stands for signals related to operations of DAC 207 and the indices “R” and “F” correspond respectively to rough and fine subphases. Thus, for example, the signal φ 1R — D controls the rough subphase of each sampling phase (φ 1 ).

Generally, charge is transfer at the full modulator feedback loop rate. In the illustrated embodiment, charge is provided from DAC outputs DAC+ and DAC− every two periods of the MCLK signal. Each cycle of DAC 207 includes a sampling phase φ 1 , having both rough and fine subphases, and a charge transfer phase φ 2 . The depicted times t 0 –t 5 generally correspond to times t 0 –t 5 shown in FIG. 3B .

A representative sample/charge transfer cycle within DAC 207 begins at time t 0 , with the rising edge of the φ 1 — D signal. The rough subsampling phase is then triggered by the φ 1R — D signal, and is followed by the fine subsampling phase, which is controlled by the φ 1F — D signal. Slightly after time t 1 , the signals φ 1 — D and φ 1R — D transition to an inactive state and the charge transfer phase begins with the rising edge of the signal φ 2 — D , and charge begins to be transferred to the outputs DAC+ and DAC The charge transfer phase continues through times t 2 –t 3 and at time t 4 , the next charge sampling phase begins.

Hence, input sampling network/integrator 300 realizes a number of significant advantages over the prior art. For example, since input sampling network/integrator 300 samples the voltages at each input AIN+ or AINL− to a given sampling capacitor 306 a or 306 b at approximately half the sampling rate of the delta-sigma modulator 200 loop, the input impedance to input sampling network/integrator 300 approximately doubles. Additionally, since the sampling capacitors must only be charged with a charge proportional to the change in the input voltages between the odd and even cycles, the sampling phases (φ 1 ) of each cycle may be shortened. In turn, the charge transfer phase of each cycle may be increased such that the size of the switching transistors may be reduced, for all stages 202 a – 202 e of FIG. 2 , thereby saving die area and reducing power consumption. Additionally, the overlap between the odd and even cycles allows the output plates of the sampling capacitors to more rapidly settle to the common mode voltage prior to sampling to be driven by a smaller, less complicated, and/or less expensive driver circuit.

Although the invention has been described with reference to specific embodiments, these descriptions are not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed might be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.

It is therefore contemplated that the claims will cover any such modifications or embodiments that fall within the true scope of the invention.