Nonvolatile semiconductor static random access memory device

1. Field of the Invention

The present invention generally relates to a nonvolatile semiconductor memory device, and more specifically concerns a memory device combining a nonvolatile memory device with a Static Random Access Memory (hereinafter, referred to as “SRAM”).

2. Description of the Related Art

FIG. 1 is a circuit diagram illustrating a data register of a conventional SRAM. Here, a plurality of data registers are connected to form a SRAM.

The data register comprises a pull-up driving unit 2 , a pull-down driving unit 4 and a data input/output unit 6 .

The pull-up driving unit 2 comprises PMOS transistors PT 1 and PT 2 whose gates are cross-coupled with a latch type circuit.

The pull-down driving unit 4 comprises NMOS transistors NT 1 and NT 2 whose gates are cross-coupled with a latch type circuit.

The data input/output unit 6 comprises switches NT 3 and NT 4 configured to selectively input and output data with bit lines BL and /BL depending on a voltage applied to a word line WL. Here, the switches NT 3 and NT 4 are NMOS transistors whose gates are connected to the word line WL.

Hereinafter, the operation of the register of the conventional SRAM is described.

At a write mode, when high level data are loaded on the true bit line BL and a driving voltage Vpp is applied to the word line WL, the switches NT 3 and NT 4 of the data input/output unit 4 are turned on. Here, the complement bit line /BL is set at a low level.

In the pull-up driving unit 2 , the first PMOS transistor PT 1 is turned on, and the second PMOS transistor PT 2 is turned off.

In the pull-down driving unit 4 , the first NMOS transistor NT 1 is turned off, and the second NMOS transistor NT 2 is turned on.

Here, when the driving voltage Vpp applied to the word line WL is intercepted, the high level data are latched by the pull-up driving unit 2 and the pull-down driving unit 4 .

At a read mode, when the driving voltage Vpp is applied to the word line WL, the switches NT 3 and NT 4 of the data input/output unit 6 are turned on.

For example, when the high level data are stored, the first PMOS transistor PT 1 of the pull-up driving unit 2 is turned on, so that the high level data are loaded in the true bit line BL. Here, the second NMOS transistor NT 1 of the pull-down driving unit 4 is turned on, so that the complement bit line /BL is set at the low level.

Although the example where the high level data are stored or read is described herein, the low level data are also stored or read by the same operation as described above.

However, the conventional volatile data register loses the stored data when a power is turned off.

Various embodiments are directed at preventing stored data from being destroyed even when a power source is intercepted.

According to one embodiment of the present invention, a nonvolatile semiconductor memory device is provided with a plurality of data registers. Preferably, each of the plurality of data registers comprises a pull-up driving unit adapted and configured to pull up a storage node, a pull-down driving unit adapted and configured to pull down the storage node, a data input/output unit adapted and configured to selectively input and output data between a bit line and the storage node depending on a voltage applied to a word line, and a data storing unit adapted and configured to store data of the storage node depending on a voltage applied to a top word line and a bottom word line or to output the stored data to the storage node.

Other aspects and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 is a circuit diagram illustrating a data register of a conventional SRAM;

FIG. 2 is a circuit diagram illustrating a data register of a nonvolatile SRAM according to an embodiment of the present invention;

FIGS. 3 a and 3 b are cross-sectional diagrams illustrating a data cell of a data storing unit of FIG. 2 ;

FIGS. 4 a and 4 b are diagrams illustrating write and read operations on high level data “1” in the data cell of the data storing unit of FIG. 2 ;

FIGS. 5 a and 5 b are diagrams illustrating write and read operations on high level data “0” in the data cell of the data storing unit of FIG. 2 ;

FIG. 6 is a diagram illustrating a write operation of the data cell of the data storing unit of FIG. 2 ;

FIG. 7 is a diagram illustrating a read operation of the data cell of the data storing unit of FIG. 2 ;

FIG. 8 is a timing diagram illustrating the operation to preserve the high level data “1” or write the low level data “0” in the data cell of the data storing unit of FIG. 2 ; and

FIG. 9 is a timing diagram illustrating a recall operation at a power-on reset mode according to an embodiment of the present invention.

The present invention will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

FIG. 2 is a circuit diagram illustrating a data register of a nonvolatile SRAM according to an embodiment of the present invention. Here, a plurality of data registers are connected to form a nonvolatile SRAM.

In this embodiment, the data register comprises a pull-up driving unit 12 , a pull-down driving unit 14 , a data input/output unit 16 and a data storing unit 18 .

The pull-up driving unit 12 comprises PMOS transistors PT 11 and PT 12 whose gates are cross-coupled to storage terminals SN and /SN with a latch type circuit.

The pull-down driving unit 14 comprises NMOS transistors NT 11 and NT 12 whose gates are cross-coupled to the storage terminals SN and /SN with a latch type circuit.

The data input/output unit 16 comprises switches NT 13 and NT 14 configured to selectively input and output data between the bit lines BL, /BL and the storage terminals SN, /SN depending on a voltage applied to the word line WL. Here, the switches NT 13 and NT 14 are NMOS transistors whose gates are connected to the word line WL.

The data storing unit 18 comprises data cells C 1 and C 2 configured to store data of the storage nodes SN and /SN or output the stored data to the storage nodes SN and /SN depending on a voltage applied to a top word line TWL and a bottom word line BWL.

FIGS. 3 a and 3 b are cross-sectional diagrams illustrating the data cell C 1 of a data storing unit 18 of FIG. 2 .

FIG. 3 a is a cross-sectional diagram illustrating the data cell C 1 cut in a direction parallel to the top word line TWL and the bottom word line BWL.

In the data cell C 1 , an oxide film 20 , a float channel layer 22 and a ferroelectric layer 24 are sequentially deposited on the bottom word line BWL. The top word line TWL is formed on the ferroelectric layer 24 in parallel with the bottom word line BWL.

FIG. 3 b a cross-sectional diagram illustrating the data cell C 1 cut in a direction perpendicular to the top word line TWL and the bottom word line BWL.

The float channel layer 26 includes a P-type float channel 22 , a N-type region 28 that serves as a drain, and a N-type region 30 that serves as a source.

Preferably, the float channel layer 26 is formed of a carbon nano tube, silicon, Ge and an organic semiconductor.

As a result, a channel resistance of the float channel 22 is differentiated depending on the polarization of the ferroelectric layer 24 .

FIGS. 4 a and 4 b are diagrams illustrating write and read operations on high level data “1” in the data cell of the data storing unit of FIG. 2 .

FIG. 4 a is a diagram illustrating the write operation on the high level data “1”.

A positive voltage +V is applied to the bottom word line BWL, and a negative voltage −V is applied to the top word line TWL. Here, the drain region 28 and the source region 30 are configured to be at a ground voltage GND state.

When a voltage is applied between the ferroelectric layer 24 and the float channel layer 26 by voltage distribution of a capacitor between the oxide film 20 and the ferroelectric layer 24 , a polarization, which corresponds to the high level data “1”, forms in the ferroelectric layer 24 . The polarization formed in the ferroelectric layer 24 induces positive charges into the float channel 22 of the float channel layer 26 .

FIG. 4 b is a diagram illustrating the read operation on the high level data “1”.

When a ground voltage GND is applied to the bottom word line BWL and the top word line TWL, the polarization formed in the ferroelectric layer 24 induces positive charges into the float channel 22 of the float channel layer 26 . Here, since the drain region 28 and the source region 30 are at the ground state, the float channel 22 of the float channel layer 26 is turned off.

As a result, the data “1” stored in a memory cell can be read at a read mode. When a voltage difference is applied to the drain region 28 and the source region 30 , the float channel layer 26 is at a turn-off state, so that no current flows indicating an “off” state.

FIGS. 5 a and 5 b are diagrams illustrating write and read operations on low level data “0” in the data cell of the data storing unit of FIG. 2 .

FIG. 5 a is a diagram illustrating the write operation on the low level data “0”.

When the ground voltage GND is applied to the drain region 28 and the source region 30 and the positive voltage +V is applied to the bottom word line BWL and the top word line TWL, the polarization, which corresponds to the low level data “0”, of the ferroelectric layer 24 is formed. The polarization formed in the ferroelectric layer 24 induces negative charges into the float channel 22 of the float channel layer 26 .

Since a high voltage is formed between the ground voltage of the float channel layer 26 and the positive voltage +V of the top word line TWL, electrons of the float channel layer 26 move into the ferroelectric layer 24 , so that the electrons are accumulated in the ferroelectric layer 24 .

Meanwhile, when the positive voltage +V is applied to the drain region 28 and the source region 30 while the high level data “1” is stored in the ferroelectric layer 24 , the float channel layer 26 transitions to a turn-off state.

Since there is no voltage difference between the floated positive voltage of the float channel layer 26 and the positive voltage +V of the top word line TWL, electrons into the ferroelectric layer 24 does not move, so that the ferroelectric layer 24 maintains the previous state. As a result, the previously stored high level data “1” is maintained.

FIG. 5 b is a diagram illustrating the read operation of the low level data “0”.

When the ground voltage GND is applied to the bottom word line BWL and the top word line TWL and a voltage difference is applied between the drain 28 and the source 30 , the float channel layer 26 is turned on, so that current flows indicating an “on” state.

As a result, since by the ground voltage applied to the bottom word line BWL and the top word line TWL at the above-described read mode, a voltage potential is not applied to the ferroelectric layer 24 , so thereby improving the data retention characteristics of the memory cell.

Specifically, since a retaining characteristic of a ferroelectric memory register at a nano scale level becomes weakens at a low voltage potential, it is difficult to apply a random voltage to the top word line TWL at the read mode as with a conventional method.

However, the ferroelectric register according to an embodiment of the present invention can perform a low voltage operation at the nano scale.

FIG. 6 is a diagram illustrating a write operation of the data cell of the data storing unit of FIG. 2 .

A write operation cycle of the data cell C 1 is divided into two sub operation regions. That is, data “1” is written in the first sub operation region, and the data “1” written in the first sub operation region is preserved or the data “0” is written in the second sub operation region.

When the data “1” is required to be preserved, if a high voltage is applied to the bit line for a predetermined period, the data “1” written in the first sub operation region is preserved in the memory cell.

FIG. 7 is a diagram illustrating a read operation of the data cell of the data storing unit of FIG. 2 .

In a period t 0 as a precharge period of the memory cell, all signals and lines are precharged to a ground voltage VSS.

In a period t 1 , a high level voltage is applied to the word line WL.

In a period t 2 , a negative voltage VNEG is applied to the top word line TWL.

In a period t 3 , when a high level voltage is applied to the bottom word line BWL, a high voltage is applied to the ferroelectric layer 24 by voltage distribution between the top word line TWL and the bottom word line BWL.

In a period t 4 , the top word line TWL and the bottom word line BWL is set at a ground state.

In a period t 5 , the word line WL is set at the ground state.

FIG. 8 is a timing diagram illustrating the operation to preserve the high level data “1” or write the low level data “0” in the data cell of the data storing unit of FIG. 2 .

In a period t 0 as a precharge period of the memory cell, all signals and lines are precharged to the ground voltage VSS.

In a period t 1 , a high level voltage is applied to the word line WL.

In a period t 2 , a high level voltage is applied to the bottom word line BWL.

In a period t 3 , the true bit line BL is continuously maintained at the ground state when data to be written is a low level “0”, and a high level voltage is applied to the true bit line BL when the high level data “1” is preserved.

In a period t 4 , when a high level voltage is applied to the top word line TWL, electrons are accumulated in the floating channel layer 26 , and the voltage difference between the top word line TWL and the floating channel layer 26 attains a threshold voltage difference. As a result, the ferroelectric layer 24 has a polarity that induces electrons into the float channel layer 26 , and the low level data “0” is written.

Meanwhile, when a high level voltage is applied to the true bit line BL, a channel is prevented from being formed in the float channel layer 26 , so that the low level data “0” is not written and the high level data “1” is preserved.

In a period t 5 , the top word line TWL is set at the ground state.

In a period t 6 , the bottom word line BLW and the bit lines BL, /BL are set at the ground state.

In a period t 7 , the word line WL is set at the ground state.

FIG. 9 is a timing diagram illustrating a recall operation at a power-on reset mode according to an embodiment of the present invention.

In a period t 0 , before a reset signal RESET is generated at a power-on mode, the storage nodes SN and /SN are set at a high level and a low level depending on data stored in the data cell C 1 of the data storing unit 18 shown in FIG. 2 .

In a period t 1 , when a power voltage VCC sufficiently rises to generate the reset signal RESET, the bottom word line BWL is set at the high level, so that the data of the storage nodes SN and /SN are bypassed through a control terminal of the bottom word line BWL.

When the word line WL is maintained at the low level and the bit lines BL and /BL rise to the same level of a power voltage VCC, a register state is restored by a program state of the pull-up driving unit 12 .

As described above, in a nonvolatile semiconductor memory device according to an embodiment of the present invention, data are not destroyed even when a power source is intercepted.

Also, the nonvolatile semiconductor memory device according to an embodiment of the present invention restores a data state store at a power-on mode.

The foregoing description of various embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. Thus, the embodiments were chosen and described in order to explain the principles of the invention and its practical application to enable one skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated.