Methods for forming a P-type polysilicon layer in a semiconductor device

The present disclosure relates generally to methods of manufacturing semiconductor devices, and, more particularly, to methods for forming a P-type polysilicon layer in a semiconductor device.

During a typical process of manufacturing a semiconductor device, a gate oxide layer 102 is formed on a semiconductor substrate 100 . A doped polysilicon layer 104 a used as a gate electrode is formed on the gate oxide layer 102 as shown in FIG. 1 . A liner layer 106 and a spacer 108 are formed on the sidewalls of the doped polysilicon layer 104 a . In addition, an LDD source/drain 114 having a lightly doped region 110 and a heavily doped region 112 is formed under the liner layer 106 and the spacer 108 .

A P-type polysilicon layer is widely used for the gate electrode in a semiconductor device. The P-type polysilicon layer 104 a is, as shown in FIG. 2 , usually formed by a doping process using boron 116 with a mask pattern 109 having an opening exposing only the polysilicon layer 104 . Alternatively, as shown in FIG. 3 , the P-type polysilicon layer 104 a may be formed by a doping process using boron 116 after forming an isolation layer 101 , a gate oxide layer 102 , and a polysilicon layer 104 on the semiconductor substrate 100 .

The doping process using boron is performed by an in-situ process in a furnace, or by ion implantation of boron ions or BF 3 ions. In FIG. 1 to FIG. 3 , the same reference numerals indicate the same members.

The boron used for forming a P-type polysilicon layer is volatile, and thus, when the thickness of the P-type polysilicon layer is reduced, the concentration of the boron cannot be precisely obtained as desired.

FIG. 1 is a cross-sectional view of a typical prior art semiconductor device.

FIG. 2 and FIG. 3 are cross-sectional views showing a method for forming a P-type polysilicon layer used for a gate electrode in a semiconductor device such as that shown in FIG. 1 .

FIG. 4 to FIG. 6 are cross-sectional views illustrating an example method for forming a P-type polysilicon layer performed in accordance with the teachings of the present invention.

To clarify multiple layers and regions, the thickness of the layers are enlarged in the drawings. Wherever possible, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. As used in this patent, stating that any part (e.g., a layer, film, area, or plate) is in any way positioned on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, means that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween. Stating that any part is in contact with another part means that there is no intermediate part between the two parts.

FIG. 4 to FIG. 6 are cross-sectional views illustrating an example method for forming a P-type polysilicon layer performed in accordance with the teachings of the present invention.

Referring to FIG. 4 , in the illustrated example, an isolation layer 202 is formed on a semiconductor substrate 200 , such as a silicon substrate. Subsequently, a gate insulating layer 204 is formed on the semiconductor substrate 200 . The gate insulating layer 204 may be, for example, an oxide layer.

Referring to FIG. 5 , a gate stack 210 is formed by alternately depositing a plurality of silicon atom layers 206 and a plurality of group IIIA element atom layers 208 on the gate insulating layer 204 by atomic layer deposition (ALD).

In the illustrated example, the plurality of silicon atom layers are respectively deposited to a thickness of about 5-100 Å, and the plurality of group IIIA element atom layers are respectively deposited to a thickness of about 5-50 Å. The plurality of group IIIA element atom layers may comprise Al, Ga, In, or Tl. The thicknesses of the plurality of silicon atom layers 206 and the plurality of group IIIA element atom layers 208 depend on a desired dopant concentration.

Subsequently, the plurality of group IIIA element atom layers 208 in the gate stack 210 are diffused into the plurality of silicon atom layers 206 by a heat treatment process, and thus a P-type polysilicon layer 210 a (see FIG. 6 ) is formed.

FIG. 6 is a cross-sectional view of a semiconductor device having a P-type polysilicon layer 210 a constructed in accordance with the teachings of the present invention. In the example of FIG. 6 , reference numerals 212 and 214 respectively denote a liner layer and a spacer layer formed on the sidewalls of the P-type polysilicon layer 210 a . Reference numeral 216 denotes the first impurity region, and reference numeral 218 denotes the second impurity region. Reference numeral 220 denotes a source/drain region of an LDD structure.

As described above, a P-type polysilicon layer having a stable and desired resistivity can be formed by atomic layer deposition and heat treatment of alternating silicon atom layers and group IIIA element atom layers.

From the foregoing, persons of ordinary skill in the art will readily appreciate that example methods of manufacturing a semiconductor device have been provided which obtain precise resistivity of a P-type polysilicon layer even if the P-type polysilicon layer is thin.

An example method of manufacturing a semiconductor device includes alternately depositing a plurality of silicon atom layers and a plurality of group IIIA element atom layers on a semiconductor substrate by atomic layer deposition, and forming a P-type polysilicon layer by thermally diffusing the plurality of group IIIA element atom layers into the plurality of silicon atom layers. The plurality of silicon atom layers are respectively deposited to a thickness of about 5-100 Å, and the plurality of group IIIA element atom layers are respectively deposited to a thickness of about 5-50 Å. The plurality of group IIIA element atom layers may comprise Al, Ga, In, or Tl.

It is noted that this patent claims priority from Korean Patent Application Ser. No. 10-2004-0111043, which was filed on Dec. 23, 2004, and is hereby incorporated by reference in its entirety.

Although certain example methods, apparatus and articles of manufacture have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus and articles of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.