Trench IGBT for highly capacitive loads

This invention relates to Insulated Gate Bipolar Transistors (“IGBT”s) and more specifically relates to an IGBT structure for highly capacitive loads and Plasma Display Panels in particular.

IGBTs are well known, and are shown, for example, in U.S. Pat. Nos. 6,683,331 and 6,707,111 both of which are assigned to the assignee of the present invention. Trench IGBTs are also described in copending application Ser. No. 11/230,969, filed Sep. 20, 2005 (entitled TRENCH IGBT WITH INCREASED SHORT CIRCUIT CAPABILITY in our names (IR-2949) the contents of which are incorporated herein by reference.

IGBTs are replacing power MOSFETs in highly capacitive load applications. Thus, plasma display panels used, for example, in projection TV receivers, act as highly capacitive loads in two basic circuits of sustain and energy recover. The IGBT is useful for such loads because of its higher current conduction capability and reduced conduction loss compared to the power MOSFET.

It would be desirable to further increase the current conduction ability and further reduce the conduction loss of an IGBT to enable the use of smaller chip area IGBTs for such capacitive loads.

When the output circuit controlled by an IGBT is capacitive, the IGBT is turned on and off with little voltage applied (soft switching). It has been recognized by us that the safe operating area (“SOA”) of the IGBT operating into a capacitive load can therefore be traded in favor of faster turn-on and lower conduction-loss characteristics.

In accordance with the invention, a trench IGBT is arranged to provide improved operation for a highly capacitive load, in particular, a plasma display panel, in which device SOA is intentionally reduced in favor of faster turn-on times and lower conduction losses. This is accomplished, for a 300 volt illustrative device, through the control and reduction of substrate resistivity, buffer layer resistivity and thickness, and a reduction in the junction receiving epitaxial layer resistivity and thickness.

Preferably, the following design is employed for the 300 volt trench IGBT:

Substrate resistivity: <10 mohm.

Buffer resistivity: 0.05 to 0.1 ohm cm.

Buffer layer thickness: 8 μm.

Epi layer resistivity: 14 to 18 ohm cm.

Epi layer thickness: 31 to 37 μm.

FIG. 1 is a cross-section of a small portion of a starting wafer of the invention.

FIG. 2 is a diagram of the concentration of the various layers of the IGBT wafer of the invention (or IGBT die which is singulated from the wafer), targeted to a 300 volt device.

FIG. 3 is a cross-section of the finished IGBT according to the invention, showing a finished trench MOSgated structure in the top of the die or wafer.

FIGS. 1 and 2 show the starting wafer (or die) of the invention which is configured to produce a maximized turn-off speed, and a minimized conduction loss at the expense of SOA.

Thus, in FIGS. 1 and 2 , the wafer 10 has a P ++ substrate 11 . An epitaxially grown drift layer 13 is grown atop an N + buffer 12 diffused into substrate 11 , all using well known and conventional process techniques. The device junctions and trenches are formed in the epi drift layer 13 . However, the specific dimensions and resistivities are selected to impart improved turn-off speed and conduction-loss to make IGBT devices which are applicable for use with highly capacitive loads such as PDP displays with reduced silicon die area for a given application.

Thus, for a 300 volt IGBT, the following characteristics are selected:

Resistivity of substrate 11 : <10 mohm cm.

Resistivity of buffer 12 : 0.05-0.1 ohm cm.

Buffer 12 thickness: 8 μm.

Resistivity of drift layer 13 : 14-18 ohm cm.

Thickness of drift layer: 31-37 μm.

FIG. 3 shows the finished IGBT after trenches, junctions and contacts are formed on the wafer (or die) of FIGS. 1 and 2 .

Thus, using any desired process, an N type trench receiving region 19 is formed and receives a plurality of trenches 20 , 21 , 22 which are formed in the device active area and contain polysilicon gates 23 , 24 , 25 respectively which are separated from the trench walls by suitable gate oxides. The trenches 20 , 21 , 22 are typical of any desired number of trenches used in the device active area.

Trenches 20 , 21 , 22 pass through P 30 channel diffusion 29 . The polysilicon masses 23 , 24 and 25 are capped by capping oxides 30 , 31 , 32 respectively and N 30 emitter regions 33 , 34 and 35 are provided in the usual manner. P ++ source contact diffusions 40 , 41 , 42 and 43 are also provided to make contact to the aluminum source contact 45 which contacts the emitter regions 33 , 34 and 35 and the P + channel 30 .

A P + termination region 60 is formed and is covered by oxide layer 61 and is connected to the source (or emitter) 45 at P ++ region 43 . The source 45 is then passivated by the Am Si layer 70 and silicon nitride layer 71 . These are etched to expose a contact area to the electrode 45 .

After the top surface is completed in FIG. 3 , the backside of the wafer is conventionally furnished as shown and collector contact 80 (Al/Ti/Ni/Ag) is applied to the wafer bottom surface.

Note that any desired junction pattern and topology can be employed to finish the die without departing from the invention.

Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.