Memory cell driver circuits

A memory cell driver circuit may be used to write a value to and/or read a value from a memory cell. In the case of a One-Time Programmable (OTP) memory cell, which is a type of Programmable Read Only Memory, a value is written to the memory cell once and cannot be overwritten during conventional operation. Writing values to (i.e., programming) arrays of conventional OTP memory cells requires high voltages and currents. Driver circuits for these arrays may use thick-oxide transistors to supply the currents and to withstand the voltages. Some OTP memory cells, such as poly-Si-fuse memory cells, are programmed using a dedicated driver circuit for each cell. Each dedicated driver circuit typically includes a large VDNMOS device. Such implementations may be inefficient in terms of one or more of fabrication cost, die footprint, power consumption and other factors.

FIG. 1A is a schematic diagram of an OTP memory cell array.

FIG. 1B is a table of voltages for reading and programming an OTP memory cell according to some embodiments.

FIG. 2A is a schematic diagram of a pull-up circuit of a driver according to some embodiments.

FIG. 2B is a table of control, internal and output voltages corresponding to different functions of the FIG. 2A circuit according to some embodiments.

FIG. 3 is a schematic diagram of a pull-up circuit of a driver according to some embodiments.

FIG. 4 is a schematic diagram of a pull-down circuit of a driver according to some embodiments.

FIG. 5A is a schematic diagram of a pull-down circuit of a driver according to some embodiments.

FIG. 5B is a table of control, internal and output voltages corresponding to different functions of the FIG. 5A circuit according to some embodiments.

FIG. 6A is a schematic diagram of a driver for programming and reading a read-only memory cell according to some embodiments.

FIG. 6B is a table of control, internal and output voltages corresponding to different functions of the FIG. 6A circuit according to some embodiments.

FIG. 7 is a schematic diagram of a voltage regulator according to some embodiments.

FIG. 8A is a schematic diagram of a level shifter according to some embodiments.

FIG. 8B is a schematic diagram of a bypass circuit according to some embodiments.

FIG. 9 is a block diagram of a system according to some embodiments.

FIG. 1A is a schematic-diagram showing a 2×2 array of OTP memory cells according to some embodiments. The gate of each of memory cells 10 through 40 is coupled to one of Word Lines WL 0 and WL 1 , and the drain of each of memory cells 10 through 40 is coupled to one of Bit Lines BL 0 and BL 1 . Voltages on Word Lines WL 0 and WL 1 are controlled by associated Word Line Drivers (WLDs) 50 and 60 , and voltages on Bit Lines BL 0 and BL 1 are controlled by associated Bit Line Drivers (BLDs) 70 and 80 . Bit Lines BL 0 and BL 1 are also respectively coupled to Sense Amplifiers (SAs) 90 and 100 for use during a read operation.

FIG. 1B illustrates table 150 of Bit Line and Word Line voltages for reading and writing (i.e. programming) an OTP memory cell such as cells 10 through 40 . Depending on the mode of operation, Bit Line or Word Line can be connected to one of four nodes: GND; V prog ; V cc ; or sense (i.e., the sense amplifier input). In a read mode, each cell is either enabled for reading or not enabled. The voltages on Bit Lines BL 0 and BL 1 and Word Lines WL 0 and WL 1 are determined from table 150 based on whether an attached cell is enabled or not enabled. Table 150 also shows Bit Line and Word Line voltages for programming a cell and for preventing programming of “non-enabled” cells. As shown, both the BLDs and the WLDs are required to generate V prog . In some embodiments, V prog =4V cc .

FIG. 2A is a schematic diagram of PMOS-based high-side (pull-up) switch 200 according to some embodiments. Switch 200 may be implemented by any of drivers 50 , 60 , 70 and 90 to provide V prog to an appropriate memory cell. Switch 200 includes level shifter 210 to receive control signal d (range 0-V cc ), rail voltages V 4 =4V cc , V 3 =3V cc , V 2 =2V cc , and supply voltage V 1 =V cc . Based on the received signals, components U 1 , U 2 , Rx 1 , Rx 2 , Mm 1 , and Mm 2 of level shifter 210 ) generate control signal V G4 (range 4V cc -˜3V cc ).

Cascode stage 220 receives control signal V G4 from level shifter 210 . Cascode stage 220 comprises a plurality of PMOS transistors Mh 4 , Mh 3 , Mh 2 , and Mh 1 . A gate voltage of transistor Mh 4 is controlled by control signal V G4 , a gate voltage of transistor Mh 3 is controlled by control signal V G3 =V 3 =3V cc , a gate voltage of transistor Mh 2 is controlled at least in part by V 2 =2V cc , and a gate voltage of transistor Mh 1 is controlled at least in part by V 1 =V cc . Resistive network R 1 through R 5 is coupled to transistors Mh 1 through Mh 4 to ensure that the transistors' gate-to-source voltage and drain-to-source voltage are maintained at less than or equal to a maximum operational voltage. In some embodiments, R 1 =R 2 =R 3 =R 4 =R 5 . Cascode stage 220 also includes output node y for providing cell programming voltage signal V prog .

FIG. 2B illustrates table 250 of gate and drain voltages for transistors Mh 1 through Mh 4 during two functions of pull-up circuit 200 . According to the first function, control signal d is 0 to indicate that no programming voltage is required from output node y. Control signal d may be switched to 1 to provide cell programming voltage signal V prog =4V cc . As shown in table 250 , |V G −V D | for each of transistors Mh 1 through Mh 4 is substantially equal to V cc during each function. According to some embodiments, the foregoing features of circuit 200 may reduce or eliminate a need for thick-oxide transistors to handle high-voltage/high-current switching in OTP memory cell drivers.

FIG. 3 is a schematic diagram of high-side pull-up switch 300 according to some embodiments. Switch 300 may be implemented by any of drivers 50 , 60 , 70 and 90 to provide V prog to an appropriate memory cell via output node y. Switch 300 includes level shifter 310 , signal conditioning circuit 315 , and cascode stage 320 . Level shifter 310 is similar to level shifter 210 of switch 200 , with elements Rx 1 and Rx 2 being replaced with PMOSFETs Mx 1 through Mx 4 and Mx 5 through Mx 8 , respectively. This replacement may improve the output swing and power supply rejection of level shifter 310 as compared to level shifter 210 .

Transistors Ma 1 -Ma 4 of signal conditioning circuit 315 receive V G4 from level shifter 310 and, in a case that cell programming voltage signal V prog is not to be output, amplifies V G4 to V 4 =4V cc . The amplified value ensures that transistor Mh 4 is turned off.

PMOSFETs Mr 1 through Mr 9 of cascode stage 320 replace resistor network R 1 through R 5 of cascode stage 210 . PMOSFETs Mr 1 through Mr 9 are connected in such a way that Mr 1 through Mr 5 are safely on for d=0 and the gates of transistors Mh 1 through Mh 4 are therefore held in place. Moreover, for d=1, the gate-to-source voltage of each Mr 1 through Mr 9 is equal to the drain-to-source voltage, which in turn is equal to V cc . The foregoing arrangement may correctly implement the required voltage divider ratios despite the nonlinearity of Mr 1 through Mr 9 .

FIG. 4 is a schematic diagram of PMOS-based low-side (pull-down) switch 400 according to some embodiments. Switch 400 may be implemented by any of drivers 50 , 60 , 70 and 90 to sink current from an appropriate memory cell via output node y. Voltage divider 410 comprising resistors R 0 through R 3 receives control voltage x and outputs voltage signals V Gp3 , V Gp2 , V Gp1 , and V Gp0 based thereon. PMOS cascode stage 420 comprises transistors Mp 0 through Mp 3 , each of which is controlled by one of voltage signals V Gp3 , V Gp2 , V Gp1 , and V Gp0 . A source of transistor Mp 3 may receive current from a memory cell via a Bit Line.

In operation, pulling control voltage x to 4V cc (e.g., using high-side switch 200 ) may cause output node y to range from V x -V cc to V x +V t without turning on cascode stage 420 and without any of transistors Mp 0 through Mp 3 exceeding their maximum voltage rating. V t as used herein denotes a gate-to-source voltage that will cause current flow when a corresponding drain-to-source voltage is non-zero. When x=0, cascode stage 420 turns on and pulls y down to ˜V t . The use of PMOS transistors in low-side switch 400 may reduce or eliminate a need for VDNMOS devices to sink high programming currents in some embodiments.

FIG. 5A shows pull-down circuit 500 according to some embodiments. As described with respect to switch 400 , circuit 500 may be implemented by any of drivers 50 , 60 , 70 and 90 to sink current from an appropriate memory cell via output node y. With respect to circuit 400 , PMOSFET Mp 4 has been added to allow application of V cc at the output, which may be required on a Word Line during a read mode, as shown in table 150 . If circuit 500 is used in a BLD, VDNMOS transistor Ml 3 ensures current flow for V y <V t during the read mode. A Sense Amplifier input may be connected to node s, which does not exceed V cc .

The resistors R 0 through R 3 of divider 410 are replaced by transistors Mr 6 through Mr 8 and M 1 through M 3 , which ensure that V Gp1 , V Gp2 and V Gp3 are pulled to ground when switch 500 is on (i.e., Function=GND). The level shifter U 3 provides |V gs |<=V cc for M 2 , M 3 and M 13 . The pull-down current of switch 500 at a given area can be improved by adding an NMOS cascode such as Ml 1 and Ml 2 controlled by c 0 n:c 0 n=V cc |x=0, c 0 n=0|x=4V cc . FIG. 5B shows table 550 of voltages within circuit 500 that correspond to each function specified in table 150 of FIG. 1B . Control signals c 0 n, c 0 p and d may be generated by combinatorial logic or any other systems.

FIG. 6A is a schematic diagram of a driver according to some embodiments. Driver 600 roughly combines switch 300 of FIG. 3 with switch 500 of FIG. 5A . Accordingly, driver 600 may comprise any of drivers 50 , 60 , 70 and 90 of FIG. 1A . Transistors Mr 6 through Mr 8 are shared between high-side and low-side portions of driver 600 , and transistor Mr 9 of circuit 300 is omitted. A PMOSFET, Mi 1 , pulls V Gp3 (node x of FIG. 4 ) to 4V cc when the high-side portion is on.

FIG. 6B shows a table of control signals c 0 n, c 0 p and d and corresponding outputs for driver 600 . The control signals can be generated by combinatorial logic or any other systems, including but not limited to firmware and software.

FIG. 7 is a schematic diagram of voltage regulator 700 to generate the rail voltages V 1 through V 4 in some embodiments. Transistors Mg 1 through Mg 4 generally operate as stacked shunt regulators, which support currents through transistors Mr 1 through Mr 5 and Ma 1 through Ma 4 , and also supply level shifter U 5 . Rail voltages V 2 thru V 4 are required only during programming (/w=0). Accordingly, V 4 may be grounded during a read mode (/w=1), reducing the currents drawn by the voltage divider networks of circuit 600 , while the low-side switches continue to work as WLDs and BLDs for the read operation.

FIG. 8A shows level shifter U 5 of circuit 600 according to some embodiments. In some embodiments, output node y of level shifter U 5 is coupled to node d of bypass circuit 800 shown in FIG. 8B . Such an arrangement allows the collapse of V 4 , V 3 , and V 2 to 0V during a read mode. For example, bypass circuit 800 passes the output of level shifter U 5 through to node y if V 2 =2V cc , and holds node y at V cc if V 2 =0V.

FIG. 9 illustrates a block diagram of system 900 according to some embodiments. System 900 includes integrated circuit (IC) 902 which may comprise a microprocessor. IC 902 includes OTP memory 904 for storing an IC identifier, IC speed, and/or any other suitable information. OTP memory 904 may include an array of OTP memory cells and associated BLDs and WLDs such as driver 600 .

Integrated circuit 902 may communicate with memory 906 via chipset 908 . Memory 906 may comprise any type of memory for storing data, such as a Single Data Rate Random Access Memory, a Double Data Rate Random Access Memory, or a Programmable Read Only Memory. Other off-die functional units, such as graphics controller 910 and Network Interface Controller (NIC) 912 , may communicate with integrated circuit 902 via appropriate busses or ports.

Some embodiments may provide high-voltage driver circuits that avoid heavy usage of VDNMOS devices and large reverse-bias voltages across source/drain-to-substrate junctions. Some embodiments perform high-voltage/high-current switching with cascoded PMOS transistors, and use VDNMOS devices only to control and signal transmission.

The several embodiments described herein are solely for the purpose of illustration. Embodiments may include any currently or hereafter-known versions of the elements described herein. Therefore, persons in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.