Method for dynamically changing the frequency of clock signals

The present invention relates to the field of electronic circuits; more specifically, a method and circuit for dynamically changing the frequency of clock signals.

Modern integrated circuit chips contain circuits in different regions of the integrated circuit chip running at different clock frequencies and often these circuits must send signals to each other. The clock frequencies in the different regions of the integrated circuit chip may or may not be integer ratios of each other. Further, it is often desirable to change the frequency of one or more clocks while the integrated circuits are active. Presently, methods to effect clock frequency changes require reliance on stored information of the ratio of the clock frequencies, cause glitches when the clock frequencies are changed (elongated or shorted transitional clock pulses are generated), require a system wide reset or limit the frequencies of the clock signal in some manner, all of which are not desirable in many circuit applications.

Therefore, there is a need for a method and circuit that allows dynamic clock frequency changes that does not require reliance on stored information of the ratio of the clock frequencies, cause glitches when the clock frequencies are changed, require a system wide reset or limit the frequencies of the clock signals.

A first aspect of the present invention is: a method, comprising: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second clock signal using the first clock signal; detecting coincident edges of the first and the second clock signals; and changing the second frequency to a third frequency different from the second frequency upon detection of the coincident edges.

A second aspect of the present invention is the first aspect of the present invention wherein all the coincident edges are rising edges.

A third aspect of the present invention is the first aspect of the present invention, wherein all the coincident edges are falling edges.

A fourth aspect of the present invention is the first aspect of the present invention, wherein the first and the second frequencies are different.

A fifth aspect of the present invention is the first aspect of the present invention, wherein the first and the third frequencies are different.

A sixth aspect of the present invention is the first aspect of the present invention, wherein the first, the second and the third frequencies are different from each other.

A seventh aspect of the present invention is the first aspect of the present invention, wherein the first and third frequencies are whole integer multiples of one another.

An eighth aspect of the present invention is the first aspect of the present invention, wherein the first frequency and third frequencies are not whole integer multiples of one another.

A ninth aspect of the present invention is the first aspect of the present invention, further including: generating the first clock frequency by dividing a third clock signal operating at a fourth frequency and generating the second clock signal by dividing a fourth clock signal operating at a fifth frequency.

A tenth aspect of the present invention is the ninth aspect of the present invention further including: generating the third clock signal and the fourth clock signal by dividing a fifth clock signal operating at a sixth frequency.

The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is an exemplary schematic circuit diagram of a circuit for dynamically changing clock frequencies according to a first embodiment of the present invention;

FIGS. 2A and 2B are schematic circuit diagrams of clock network divider circuits according to the first embodiment of the present invention;

FIG. 3 is an exemplary schematic circuit diagram of a coincident clock edge detector circuit according to the first embodiment of the present invention;

FIG. 4 is a timing diagram of the circuit of FIG. 1 ;

FIG. 5 is an exemplary schematic circuit diagram of a circuit for dynamically changing clock frequencies according to a second embodiment of the present invention;

FIGS. 6A and 6B are schematic circuit diagrams of clock network divider circuits according to the second embodiment of the present invention;

FIG. 7 is an exemplary schematic circuit diagram of a coincident clock edge detector circuit according to the second embodiment of the present invention;

FIG. 8 is a timing diagram of the circuit of FIG. 5 ; and

FIG. 9 is an exemplary schematic circuit diagram of a circuit for dynamically changing clock frequencies in three different clock domains according to a third embodiment of the present invention.

FIG. 1 is an exemplary schematic circuit diagram of a circuit for dynamically changing clock frequencies according to a first embodiment of the present invention. In FIG. 1 , a clock circuit 100 includes a phase locked loop circuit (PLL) 105 coupled to a coincident rising edge detector circuit (CRED) 110 and coupled to an CLK A divider network 115 A and a CLK B divider network 115 B. CLK A divider network 115 A and CLK B divider network 115 B are each coupled to CRED 110 . PLL 105 includes a voltage controlled oscillator (VCO) 120 coupled to an A clock divider 125 A and to a B clock divider 125 B.

VCO 120 generates a oscillator signal (OSC) which is supplied to A and B clock dividers 125 A and 125 B. A clock divider 125 A generates an A clock signal (CLK A) from OSC and passes CLK A to CRED 110 and A clock divider 115 A. B clock divider 125 B generates a B clock signal (CLK B) and passes CLK B to CRED 110 and B clock divider 115 B. Clock A divider network 115 A generates an X clock signal (CLK X), a Y clock signal (CLK Y) and a delayed A clock signal CLK A′ from CLK A, CLK A′ being coupled to CRED 110 . Clock A divider network 115 A also generates a CLK A coincident edge in one CLK A′ cycle signal (ACE 1 ) which is coupled to CRED 110 . Clock B divider network 115 B generates an L clock signal (CLK L), an M clock signal (CLK M) and a delayed B clock signal CLK B′ from CLK B, CLK B′ being coupled to CRED 110 . Clock B divider network 115 B also generates a CLK B coincident edge in one CLK B′ cycle signal (BCE 1 ) which is coupled to CRED 110 .

CRED 110 generates an ALLROSE A signal which indicates that CLK A and all clocks derived from CLK A (CLK X and CLK Y) and CLK B and all clocks derived from CLK B (CLK L and CLK M) have just had coincident rising edges. ALLROSE A is coupled to A clock divider network 115 A. ALLROSE A is asserted until the next rising edge of CLK A and is valid in the CLK A domain. CRED 110 generates an ALLROSE B signal which indicates that CLK B and all clocks derived from CLK B (CLK L and CLK M) and CLK A and all clocks derived from CLK A (CLK X and CLK Y) have just had coincident rising edges. ALLROSE B is coupled to B clock divider network 115 B. ALLROSE B is asserted until the next rising edge of CLK B and is valid in the CLK B domain. ALLROSE A may be used to adjust the CLK X, CLK Y frequencies. ALLROSE B may be used to adjust the CLK L, CLK M frequencies.

ACE 1 provide an early sample of CLK A rising edges, BCE 1 provide an early sample of CLK B rising edges, ALLROSE A indicates when CLK A, CLK X, CLK Y, CLK B, CLKL and CLK M have coincident rising edges and ALLROSE B indicates when CLK B, CLK L, CLK M, CLK A, CLK X and CLK Y have coincident rising edges as illustrated in FIGS. 2A , 2 B, 3 and 4 and described infra.

FIGS. 2A and 2B are schematic circuit diagrams of clock network divider circuits according to the first embodiment of the present invention. In FIG. 2A , CLK A divider network 115 A includes a state logic circuit 135 A coupled to a multi-bit Register 140 A and a clock A tree 145 A also coupled to the same multi-bit register 140 A. Clock A tree 145 A generates multiple CLK A′ signals coupled to the respective clock inputs of multi-bit register 140 A. CLK A′ is delayed very slightly relative to CLK A (and almost insignificantly to one another) because of the inverters in clock A tree 145 A. The outputs of multi-bit register 140 A include CLK X, CLK Y and ACE 1 which signals are coupled back to state logic circuit 135 A. State logic circuit 135 A generates a CLK A coincident edge in two CLK A′ cycles signal (ACE 2 ) as well as CLK X and CLK Y. State logic circuit 135 A and multi-bit register 140 A constitute an A clock domain finite state machine (FSM) who outputs include the signals CLK X, CLK Y and ACE 1 . ACE 1 is derived from ACE 2 because multi-bit register 140 A delays ACE 2 by one CLK A′ cycle. One of ordinary skill in the art would be able to design a FSM as described supra.

In the present example, ALLROSE A is coupled to state logic circuit 135 A and, state logic circuit 135 A includes frequency divider circuits responsive to a control signal CNTFREQA to change the frequencies of CLK X or CLK Y, but only on a rising edge of ALLROSE A.

FIG. 2B is similar to FIG. 2A except the CLK B domain is described. In FIG. 2B , CLK B divider network 115 B includes a state logic circuit 135 B coupled to a multi-bit Register 140 B and a clock B tree 145 B also coupled to the same form of multi-bit register 140 B. Clock B tree 145 B generates multiple CLK B′ signals coupled to the respective clock inputs of multi-bit register 140 B. CLK B′ is delayed very slightly relative to CLK B (and almost insignificantly to one another) because of the inverters in clock B tree 145 B. The output of multi-bit register 140 A include CLK L, CLK M and BCE 1 , which signals are coupled back to state logic circuit 135 B. State logic circuit 135 B generates a CLK B coincident edge in two CLK B′ cycles signal (BCE 2 ) as well as CLK L and CLK M. State logic circuit 135 B and multi-bit register 140 B constitute a B clock domain finite state machine (FSM) who outputs include the signals CLK L, CKL M and BCE 1 BCE 1 is derived from BCE 2 because multi-bit register 140 B delays BCE 2 by one CLK B′ cycle.

In the present example, ALLROSE B is coupled to state logic circuit 135 B and, state logic circuit 135 B includes frequency divider circuits responsive to a control signal CNTFREQB to change the frequencies of CLK L or CLK M, but only on a rising edge of ALLROSE B.

FIG. 3 is an exemplary schematic circuit diagram of a coincident clock edge detector circuit according to the first embodiment of the present invention. In FIG. 3 , CRED 110 includes delay elements DELAY 1 and DELAY 2 , AND gates A 1 , A 2 and A 3 , inverters I 1 , I 2 , I 3 and I 4 and rising-edge triggered flip-flops F 1 , F 2 , F 3 , F 4 , F 5 and F 6 .

CLK A is coupled to the input of DELAY 1 , the clock input of flip-flop F 2 and the data input of flip-flop F 4 . CLK B is coupled to the input of DELAY 2 , the clock input of flip-flop F 5 and the data input of flip-flop F 1 . CLK A′ is coupled to the clock input of flip-flop F 3 and CLK B′ is coupled to the clock input of flip-flop F 6 . The output of DELAY 1 is coupled to the input of inverter I 1 . The output of inverter I 1 is coupled to the input of inverter I 2 and the data input of flip-flop F 5 . The output of inverter I 2 is coupled to the clock input of flip-flop F 1 . The output of DELAY 2 is coupled to the input of inverter I 3 . The output of inverter I 3 is coupled to the input of inverter I 4 and the data input of flip-flop F 2 . The output of inverter I 4 is coupled to the clock input of flip-flop F 4 . ACE 1 and BCE 2 are coupled to respective inputs of AND gate A 3 and the output of AND gate A 3 is coupled to the data inputs of flip-flops F 3 and F 6 . The data outputs of flip-flops F 1 , F 2 and F 3 are coupled to respective inputs of AND gate A 1 . The output of AND gate A 1 is the signal ALLROSE A. The data outputs of flip-flops F 4 , F 5 and F 6 are coupled to respective inputs of AND gate A 2 . The output of AND gate A 2 is the signal ALLROSE B.

In a first example, DELAY 1 and DELAY 2 are about one quarter of the period of one cycle of signal OSC if CLK A is OSC/K 1 and if CLK B is equal to OSC/K 2 when K 1 and K 2 are independently any whole positive integer. In a second example, DELAY 1 and DELAY 2 are about one half of the period of one cycle of signal OSC if CLK A is OSC/K 1 and if CLK B is equal to OSC/K 2 when K 1 and K 2 are independently any whole positive integer greater than or equal to 2

In operation, flip-flop F 1 captures CLK B using a delayed rising edge of CLK A and flip-flop F 2 captures delayed and inverted CLK B using a rising edge of CLK A. When flip-flop F 1 latches a 1 and flip-flop F 2 latches a 1, a rising edge of CLK B has been captured by a rising edge of CLK A. Flip-flop F 4 captures CLK A using a delayed rising edge of CLK B and flip-flop F 5 captures delayed and inverted CLK A using a rising edge of CLK B. When flip-flop F 4 latches a 1 and flip-flop F 5 latches a 1, a rising edge of CLK A has been captured by a rising edge on CLK B.

The output of AND gate A 3 is a 1 only when both ACE 1 and BCE 1 are 1. ACE 1 can only be 1 when the FSM of FIG. 2A detects CLK X and CLK Y will have coincident rising edges in one CLK A cycle. BCE 1 can only be 1 when the FSM of FIG. 2B detects CLK L and CLK M will have coincident rising edges in one CLK B cycle. Both flip-flops F 3 and F 6 latch data from AND gate A 3 .

Thus, all clocks of all clock domains (e.g. CLK A, CLK X, CLK Y, CLK B, CLK L and CLK M) have coincident rising edges only when ALLROSE A and ALLROSE B have coincident rising edges.

By measuring the period between ALLROSE A and ALLROSE B having coincident rising edges, the next occurrence of ALLROSE A and ALLROSE B coincident rising edges can be determined and any or all of the clock frequencies (in the present example CLK X, CLK Y, CLK L and CLK M) may be changed via CNTFRQA and CNTFRQB (see FIGS. 2A and 2B ) with no extraneous short or long pulses or data glitches.

It should be understood, that the flip-flop of multi-bit register 140 A (see FIG. 2A ) latching ACE 1 and well as state logic circuits 135 A (see FIG. 2A ) may be moved from A clock network divider 115 A (see FIG. 1 ) to CRED 110 (see FIG. 1 ). Likewise, the flip-flop of multi-bit register 140 B (see FIG. 2B ) latching BCE 1 and well as state logic circuits 135 A (see FIG. 2A ) may be moved from B clock network divider 115 B (see FIG. 1 ) to CRED 110 (see FIG. 1 ).

Alternatively, flip flops F 3 and F 6 (see FIG. 3 ) may be moved from CRED 110 (see FIG. 1 ) to respective A clock divider network 115 A (see FIG. 1 ) and B clock divider network 115 B (see FIG. 1 ).

FIG. 4 is a timing diagram of the circuit of FIG. 1 . The timing diagram of FIG. 4 is exemplary of only one of an almost limitless number of clock frequency change scenarios. In FIG. 4 , CLK Y and CLK X are divided down from CLK A and CLK L and CLK M are divided down from CLK B. Initially, CLK A, CLK B, CLK X, (CLK Y and CLK L) and CLK M are running at different frequencies with CLK Y and CLK L at the same frequency. The first time CLK A, CLK B, CLK X, CLK Y, CLK L and CLK M have coincident rising edges is at time T 1 . The second time CLK A, CLK B, CLK X, CLK Y, CLK L and CLK M have coincident rising edges is at time T 2 , at which time the frequencies of CLK X and CLK M are changed and CLK X, CLK Y, CLK L and CLK M are the same frequency. Thereafter, CLK A, CLK B, CLK X, CLK Y, CLK L and CLK M have coincident rising edges at times T 3 , T 4 . . . etc. All the clock duty cycles are illustrated as 50%. The only requirement to maintain a 50% duty cycle when a clock is changed is that both the CLK A and CLK B duty cycles be 50%. Other duty cycles may be used.

While the first embodiment of the present invention utilized coincident rising clock edges, the second embodiment of the present invention utilizes coincident falling clock edges.

FIG. 5 is an exemplary schematic circuit diagram of a circuit for dynamically changing clock frequencies according to a second embodiment of the present invention. In FIG. 5 , a clock circuit 200 is similar to clock circuit 100 of FIG. 1 , except CRED 110 is replaced with a coincident falling edge detector (CFED) 210 , CLK A divider network 115 A is replaced with an CLK A divider network 215 A, CLK B divider network 115 B is replaced with a CLK B divider network 215 B and CFED 210 generates ALLFELL A and ALLFELL B signals instead of ALLROSE A and ALLROSE B signal, however, CLK A divider network 215 A and CLK B divider network 215 B respond to rising edges of ALLFELL A and ALLFELL B.

FIGS. 6A and 6B are schematic circuit diagrams of clock network divider circuits according to the second embodiment of the present invention. In FIG. 6A , CLK A divider network 215 A is similar to CLK A divider network 115 A of FIG. 2A except multi-bit register 140 A of FIG. 2A is replaced with multi-bit register 240 A which has an inverted clock input, state logic circuit 135 A is replaced with state logic circuit 235 A and ALLROSE A is replaced with ALLFELL A. Also, the FSM comprised of state logic circuit 235 A and multi-bit register 240 A is modified to change state on falling rather than rising clock edges.

In FIG. 6B , CLK B divider network 215 B is similar to CLK B divider network 115 B of FIG. 2B except multi-bit register 140 B of FIG. 2B is replaced with multi-bit register 240 B which has an inverted clock input, state logic circuit 135 B is replaced with state logic circuit 235 B and ALLROSE B is replaced with ALLFELL B. Also, the FSM comprised of state logic circuit 235 B and multi-bit register 240 B is modified to change state on falling rather than rising clock edges.

FIG. 7 is an exemplary schematic circuit diagram of a coincident clock edge detector circuit according to the second embodiment of the present invention. In FIG. 7 , CFED 210 is similar to CRED 110 of FIG. 3 except flip-flops F 1 , F 2 , F 3 , F 4 , F 5 and F 6 of FIG. 3 are replaced respectively with flip-flops F 7 , F 8 , F 9 , F 10 , F 11 and F 12 all of which have inverting clock inputs, and gates A 1 and A 2 of FIG. 3 are replaced with respective NOR gates N 1 and N 2 whose outputs are ALLFELL A and ALLFELL B respectively.

FIG. 8 is a timing diagram of the circuit of FIG. 5 . The timing diagram of FIG. 8 is similar to the timing diagram of FIG. 4 except times T 1 , T 2 , T 3 . . . etc occur on coincident falling edges of CLK A, CLK X, CLK Y, CLK B, CLK L, CLK M and coincident rising edges of ALLFELL A and ALL FELL B.

FIG. 9 is an exemplary schematic circuit diagram of a circuit for dynamically changing clock frequencies in three different clock domains according to a third embodiment of the present invention. In FIG. 9 , a CRED 310 includes delay elements DELAY 1 , DELAY 2 and DELAY 3 , AND gates A 4 , A 5 , A 6 and A 7 , inverters I 1 , I 2 , I 3 , I 4 , I 5 and I 6 and edge triggered flip-flops F 13 , F 14 , F 15 , F 16 , F 17 , F 18 , F 19 , F 20 , F 21 , F 22 , F 23 , F 24 , F 25 , F 26 and F 27 .

CLK A is coupled to the input of DELAY 1 , the clock inputs of flip-flops F 13 and F 15 and the data inputs of flip-flops F 19 and F 24 . CLK B is coupled to the input of DELAY 2 , the clock inputs of flip-flops F 18 and F 20 and the data inputs of flip-flops F 14 and F 26 . CLK C is coupled to the input of DELAY 3 , the clock inputs of flip-flops F 23 and F 25 and the data inputs of flip-flops F 16 and F 21

CLK A′ is coupled to the clock input of flip-flop F 17 , CLK B′ is coupled to the clock input of flip-flop F 22 and CLK C′ is coupled to the clock input of flip-flop F 27 .

The output of DELAY 1 is coupled to the input of inverter I 1 . The output of inverter I 1 is coupled to the input of inverter I 2 and the data inputs of flip-flops F 18 and F 23 . The output of inverter I 2 is coupled to the clock inputs of flip-flops F 14 and F 16 . The output of DELAY 2 is coupled to the input of inverter I 3 . The output of inverter I 3 is coupled to the input of inverter I 4 and the data inputs of flip-flops F 13 and F 25 . The output of inverter I 4 is coupled to the clock inputs of flip-flops F 19 and F 21 . The output of DELAY 3 is coupled to the input of inverter I 5 . The output of inverter I 5 is coupled to the input of inverter I 6 and the data inputs of flip-flops F 15 and F 20 . The output of inverter I 6 is coupled to the clock inputs of flip-flops F 24 and F 26 .

ACE 1 , BCE 1 and CCE 1 are coupled to respective inputs of AND gate A 7 and the output of AND gate A 7 is coupled to the data inputs of flip-flops F 17 , F 22 and F 27 .

The data outputs of flip-flops F 13 , F 14 , F 15 , F 16 and F 17 are coupled to respective inputs of AND gate A 4 . The output of AND gate A 4 is the signal ALLROSE A. The data outputs of flip-flops F 18 , F 19 , F 20 , F 21 and F 22 are coupled to respective inputs of AND gate A 5 . The output of AND gate A 5 is the signal ALLROSE B. The data outputs of flip-flops F 23 , F 24 , F 25 , F 26 and F 27 are coupled to respective inputs of AND gate A 6 . The output of AND gate A 6 is the signal ALLROSE C. One of ordinary skill in the art would be able to design circuits for generating CLK C, CLK C′ and CCE 1 (and CCE 2 ) similar to the circuits described supra for generating CLK A, CLK B, CLK A′, CLK B′, ACE 1 , BCE 1 (and ACE 2 and BCE 2 ).

The third embodiment of the present invention was described using coincident rising clock edges. One of ordinary skill in the art could revise the circuit of FIG. 9 to function on coincident falling clock edges.

The more general case of N clock domains 1 through N is more easily understood by an algorithm for designing a clock circuit of N clock domains according to a fourth embodiment of the present invention which while described in terms of coincident rising clock edges may be modified by one of ordinary skill in the art to use coincident falling clock edges.

For a coincident rising edge detector for N clocks there would be N outputs designated ALLROSE 1 through ALLROSEN. Each ALLROSE signal would be the logical AND of the Q outputs of (2*(N−1)+1) flip-flops. Designating the clock inputs to the flip-flops as C 1 , C 2 , C 3 through CN. There are three versions of each of the N clocks, a first to arrive in time, a non-delayed clock (CLK 1 through CLK N), a delayed and inverted clock (CLK 1 D, CLK 2 D, CLK 3 D through CLK ND, and a delayed clock from the clock tree in the clock divider network, (CLK 1 ′, CLK 2 ′, CLK 3 ′ through CLK N′). Each clock domain has a FSM which it drives. These FSMs divide down the clocks to generate some number of other integer divides of each clock. The FSMs also generate, respectively, signals 1 CE 2 , 2 CE 2 , 3 CE 2 through NCE 2 , which indicates that two of its clock cycles in the future, all of the clocks it generates will have a coincident rising edge.

Each of the signals 1 CE 2 , 2 CE 2 , 3 CE 2 through NCE is coupled to the data input of a flip-flop clocked by CLK 1 ′, CLK 2 ′, CLK 3 ′ through CLK N′ respectively so we now have N signals which indicate each corresponding FSM will generate all rising edges on its outputs in one of its respective clock cycles. These N flip-flops may just as easily be located inside each respective FSM as inside the coincident edge detector. By ANDing the N flip-flop outputs a signal P is generated. P is sampled by N flip flops, one each clocked by respective signals CLK 1 ′, CLK 2 ′, CLK 3 ′ through CLK N′. The output of the N flip-flops are coupled to AND logic which generates the ALLROSE 1 , ALLROSE 2 , ALLROSE 3 through ALLROSE N signals. In fact, each flip-flop whose input P is the “+1” flip-flop in the formula (2*(N−1)+1). In FIG. 3 , these are flip-flops F 3 and F 6 . In FIG. 5 , these are flip-flops F 9 and F 12 . In FIG. 9 , these are flip flops F 17 , F 22 and F 27 . In general, the “+1” flip-flops are those whose data inputs are connected to the ANDed 1 CE 1 through NCE 1 signals.

The other 2*(N−1) flip-flops are as follows: For each clock domain, there will be N−1 pairs of flip-flops. Each pair of flip-flops process information from the other clock domains, which is why there are N−1 pairs. Within each pair, the clock input of one flip-flop is coupled to an un-delayed clock and the clock input of the other flip-flop is coupled to the delayed clock. The data input of each pair of flip-flops of inputs will be another clock, or another clock delayed and inverted, such that each flip-flop receives both a clock and a delayed clock. The output of all these 2*(N−1) flip-flop are coupled to 2*(N−1) other inputs of the AND logic which generates the ALLROSE signals.

Algorithmically:

Thus, embodiments of the present invention provide a method and circuit that allows dynamic clock frequency changes that does not require reliance on stored information of the ratio of the clock frequencies, cause glitches when the clock frequencies are changes, require a system wide reset or limit the frequencies of the clock signals.

The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.