Inventor
David W. Milton
Inventor
Underhill, VT, US
Overview
Patents· 45 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing49%
G01RMeasuring electric variables14%
H04LTransmission of digital information, e.g. telegraphic communication8%
H03KPulse technique6%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses6%
G11CStatic stores4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
D06HMarking, inspecting, seaming or severing textile materials3%
B65GTransport or storage devices, e.g. conveyors for loading or tipping, shop conveyor systems or pneumatic tube conveyors1%
D06FLaundering, drying, ironing, pressing or folding textile articles1%
PatentTitleYear
10,169,500Critical path delay prediction201910,006,964Chip performance monitoring system and method20189,383,766'Chip performance monitoring system and method'20169,367,493'Method and system of communicating between peer processors in SoC environment'20169,188,643'Flexible performance screen ring oscillator within a scan chain'20159,128,151'Performance screen ring oscillator formed from paired scan chains'20159,097,765'Performance screen ring oscillator formed from multi-dimensional pairings of scan chains'20158,754,696'Ring oscillator'20148,736,340'Differential clock signal generator'20148,464,199'Circuit design using design variable function slope sensitivity'20138,416,900'Method and circuit for dynamically changing the frequency of clock signals'20138,341,588'Semiconductor layer forming method and structure'20128,300,752'Method, circuit, and design structure for capturing data across a pseudo-synchronous interface'20128,189,723'Method, circuit, and design structure for capturing data across a pseudo-synchronous interface'20128,181,148'Method for identifying and implementing flexible logic block logic for easy engineering changes'20128,140,314'Optimal bus operation performance in a logic simulation environment'20128,141,028'Structure for identifying and implementing flexible logic block logic for easy engineering changes'20128,060,845'Minimizing impact of design changes for integrated circuit designs'20117,996,807'Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method'20117,917,348'Method of switching external models in an automated system-on-chip integrated circuit design verification system'20117,863,949'Circuit and design structure for synchronizing multiple digital signals'20117,849,362'Method and system of coherent design verification of inter-cluster interactions'20107,768,325'Circuit and design structure for synchronizing multiple digital signals'20107,729,877'Method and system for logic verification using mirror interface'20107,711,534'Method and system of design verification'20107,536,496'Method and apparatus for transmitting data in an integrated circuit'20097,529,962'System for expanding a window of valid data'20097,515,666'Method for dynamically changing the frequency of clock signals'20097,480,888'Design structure for facilitating engineering changes in integrated circuits'20097,451,070'Optimal bus operation performance in a logic simulation environment'20087,353,131'Method and system for logic verification using mirror interface'20087,353,156'Method of switching external models in an automated system-on-chip integrated circuit design verification system'20087,240,266'Clock control circuit for test that facilitates an at speed structural test'20077,065,602'Circuit and method for pipelined insertion'20066,865,502'Method and system for logic verification using mirror interface'20056,539,522'Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs'20036,507,230'Clock generator having a deskewer'20036,487,699'Method of controlling external models in system-on-chip verification'20026,427,224'Method for efficient verification of system-on-chip integrated circuit designs including an embedded processor'20026,075,415'Digital frequency multiplier'20005,727,180'Memory including master and local word lines coupled to memory cells storing access information'19985,717,648'Fully integrated cache architecture'19985,640,339'Cache memory including master and local word lines coupled to memory cells'19975,046,844'Apparatus for inspecting and hangering shirts'19914,873,878'Apparatus for inspecting and hangering pants'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989–1991Based in Middletown, OH, US· patent location history
1997–2019Patents assigned to IBM (42)· patent assignee history
1997–2019Based in Underhill, VT, US· patent location history
2011–2019Patents assigned to MILTON DAVID W (12)· patent assignee history
2011–2019Patents assigned to OGILVIE CLARENCE R (9)· patent assignee history
2011–2019Patents assigned to HERZL ROBERT D (7)· patent assignee history
2011–2019Patents assigned to WILDER TAD J (7)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 42 | 1997–2019 |
| MILTON DAVID Wself | 12 | 2011–2019 |
| OGILVIE CLARENCE R | 9 | 2011–2019 |
| HERZL ROBERT D | 7 | 2011–2019 |
| WILDER TAD J | 7 | 2011–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Underhill, VT, US | 43 | 1997–2019 |
| Middletown, OH, US | 2 | 1989–1991 |