Method for making an integrated circuit substrate having laminated laser-embedded circuit layers

The present application is a divisional of U.S. patent application Ser. No. 10/392,738 entitled “INTEGRATED CIRCUIT SUBSTRATE HAVING LAMINATED LASER-EMBEDDED CIRCUIT LAYERS”, now U.S. Pat. No. 6,930,257, issued Aug. 16, 2005, which is a Continuation-in-Part of U.S. patent application entitled “INTEGRATED CIRCUIT SUBSTRATE HAVING LASER-EMBEDDED CONDUCTIVE PATTERNS AND METHOD THEREFOR”, Ser. No. 10/138,225 filed May 1, 2002, now U.S. Pat. No. 6,930,256, issued Aug. 16, 2005, by the same inventors and assigned to the same assignee. The above-referenced parent application is also a Continuation-in-Part of U.S. patent application entitled “INTEGRATED CIRCUIT FILM SUBSTRATE HAVING EMBEDDED CONDUCTIVE PATTERNS AND VIAS”, Ser. No. 10/261,868 filed Oct. 1, 2002, now abandoned, having at least one common inventor and assigned to the same assignee. The specifications of the above-referenced patent applications are herein incorporated by reference.

The present invention relates generally to semiconductor packaging, and more specifically, to a substrate having laminated circuit layers added to a prepared substrate for providing electrical inter-connection within an integrated circuit package.

Semiconductors and other electronic and opto-electronic assemblies are fabricated in groups on a wafer. Known as “dies”, the individual devices are cut from the wafer and are then bonded to a carrier. The dies must be mechanically mounted and electrically connected to a circuit. For this purpose, many types of packaging have been developed, including “flip-chip”, ball grid array and leaded grid array among other mounting configurations. These configurations typically use a planar printed circuit etched on the substrate with bonding pads and the connections to the die are made by either wire bonding or direct solder connection to the die.

Multi-layer substrates have been used to increase interconnect density, as a high interconnect density is required in present-day integrated circuits such as very-large-scale-integrated (VLSI) circuits. However, the cost of a typical multi-layer substrate is substantially higher than a single or double-sided circuit substrate. The thickness of a typical multi-layer substrate is generally a sum of equal dielectric layers along with the metal conductor layers.

Multi-layer substrate also typically have the same layer thickness and are limited to line pitch and conductor spacing without incorporating the advantages disclosed in the above-referenced patent applications.

Therefore, it would be desirable to provide a method and substrate having multiple conductive layers without the associated cost and thickness of a typical multi-layer substrate. It would further be desirable to provide increased conductor density and reduced inter-conductor spacing within an integrated substrate having multiple layers.

The above objectives of providing a thin, low-cost multi-layer substrate having increased interconnect density is provided in a substrate having laminated layers including laser-embedded conductive patterns and a method for manufacturing.

The substrate comprises a prepared substrate layer that may be a rigid dielectric layer or a film having conductive patterns disposed on one or more surfaces. One or more thin-film dielectric sheets are laminated on one or more sides of the prepared substrate and laser-embedding is used to generate a circuit pattern within the one or more thin-film dielectric sheets in order to embed conductors in channels beneath the surface of the thin-film dielectric sheets. Conductive material is then plated or paste screened into the channels. The process can be extended to multiple layers to create a sandwich structure for very high conductor density applications.

FIG. 1A is a pictorial diagram depicting a cross sectional side view of a prepared substrate for forming a laminated substrate in accordance with an embodiment of the invention;

FIG. 1B is a pictorial diagram depicting a top view of a prepared substrate for forming a laminated substrate in accordance with an embodiment of the invention;

FIGS. 2A-2D are pictorial diagrams depicting cross-sectional side views of various stages of preparation of a laminated substrate in accordance with an embodiment of the invention; and

FIGS. 3A and 3B are pictorial diagrams depicting integrated circuits in accordance with embodiments of the invention.

The invention, as well as a preferred mode of use and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein like reference numerals indicate like parts throughout.

The above-incorporated patent applications disclose various processes and structures for manufacturing low-cost substrates having high conductor density and electrical integrity by laser-embedding conductive patterns below the surface of a substrate. The present invention transforms a prepared substrate having conductors etched, printed or plated on surfaces thereof into a laminated multi-layer substrate having laser-embedded conductors in the laminated layers. The addition of laser-embedded laminated layers provides a very high conductor density, while adding a low incremental cost to a low-cost substrate.

Referring now to the figures and in particular to FIG. 1A , a side view of prepared substrate 10 for use in forming a laminated substrate in accordance with an embodiment of the present invention is depicted. Circuit patterns are provided on both sides of substrate 10 by metal layers 16 A and 16 B with via connections 14 providing interconnectivity between metal layers 16 A and 16 B, but the present invention may be implemented with single-sided or multi-layer prepared substrates, as well. FIG. 1B shows a top view of prepared substrate 10 showing an exemplary pattern formed by metal layers 16 A and 16 B.

Referring now to FIG. 2A , the first stage in laminating the prepared substrate to form a modified substrate 10 A is shown. Adhesive layers 20 A and 20 B are applied to each side of substrate 10 for attachment of thin-film dielectric layers. FIG. 2B shows application of thin film dielectric layers 22 A and 22 B to each side of substrate 10 A to form laminated substrate 10 B. While the depicted embodiment of the process shows a separate application of adhesive 20 A and 20 B and thin-film layers 22 A and 22 B, a single application of a film having an adhesive backing may be applied to prepared substrate 10 in accordance with another embodiment of the process of the present invention, yielding the structure depicted in FIG. 2B (substrate 10 B) in a single application step.

Referring now to FIG. 2C , laminated substrate 10 B is laser-ablated on each side to form apertures 24 A and 24 B for vias, and channels 26 A and 26 B for circuit patterns. Channels 26 A and 26 B are shown as having a bottom within thin-film dielectric layers 22 A and 22 B, but laser-ablation may be performed to place the bottom of channels 26 A and 26 B at the top of or within adhesive layers 20 A and 20 B, providing direct contact with adhesive layers 20 A and 20 B and metal that will be subsequently deposited within channels 26 A and 26 B, improving the adhesion of the deposited metal to the substrate. In an alternative embodiment of the present invention, a thin-film dielectric layer having laser-ablated channels 26 A and 26 B and via apertures 24 A and 24 B may be aligned with and applied to substrate 10 A in one step. Further, the alternative thin-film process may apply a thin-film dielectric layer having laser-ablated channels 26 A and 26 B and via apertures 24 A and 24 B along with an adhesive backing as described above may be aligned and applied to substrate 10 in a single step.

After substrate 10 C is formed, metal is plated or paste-screened within channels 26 A and 26 B and via apertures 24 A and 24 B to form circuit patterns 29 A, 29 B and vias 28 A, 28 B beneath the top surface of substrate 10 C forming substrate 10 D. Metal may be over-plated and subsequently etched to conform with the outside surfaces of thin-film dielectric layers 22 A and 22 B, or may be slightly over-etched to place the outside surfaces of circuit patterns 29 A, 293 and vias 28 A, 288 below the outside surfaces of thin-film dielectric layers 22 A and 22 B. Alternatives to metal such as conductive polymers or materials having conductive fibers suspended in a mixture may also be applied within channels 26 A and 26 B and via apertures 24 A and 24 B to form circuit patterns 29 A, 29 B and vias 28 A, 28 B in accordance with alternative embodiments of the present invention.

The above-described process may be extended to the application of multiple thin-film laminations on a prepared substrate. Additional adhesive/thin-film/conductor layers may be applied as described above to substrate 10 D with connections to channel 29 A, 29 B and via 28 A, 28 B conductors provided by vias laser-ablated through the additional thin-film dielectric layers. Via apertures may be laser-ablated through multiple thin-film laminations in one step, providing a uniform aperture wall for vias extending through multiple thin-film dielectric layers.

Referring now to FIG. 3A , an integrated circuit 30 A in accordance with an embodiment of the present invention is depicted. An integrated circuit die 32 A is attached to substrate 10 D using a bonding agent such as epoxy. While die 32 A is depicted as mounted above substrate 10 D, a die mounting recess may also be laser-ablated or otherwise provided in substrate 10 D, reducing the package height. For example, a die mounting aperture may be provided completely through thin-film dielectric layer 22 A in an area free of channels and vias, to reduce the package height by the thickness of thin film-dielectric layer 22 A. A cavity in prepared substrate 10 may also be provided and aligned with an aperture in thin-film dielectric layer 22 A to further reduce package height.

Electrical interconnects 34 A (wires) from die 32 A are wire bonded to the circuit pattern on the top side of substrate 10 D electrically connecting die 32 A to bonding areas 36 A provided by channel circuit patterns 29 A and/or vias 28 A. External terminals 38 , depicted as solder balls, are attached to BGA lands 36 B provided by channel circuit patterns 29 B and/or vias 28 B, providing a complete integrated circuit that may be encapsulated.

Referring now to FIG. 43B , an integrated circuit 30 B in accordance with an alternative embodiment of the invention is depicted. Die 32 B is a “flip-chip” die that is directly bonded to bonding areas 36 C of a substrate 10 E via solder balls 34 B. External solder ball terminals 38 are provided as in the embodiment of FIG. 3A . Substrate 10 E is fabricated in the same manner as substrate 10 D, but may have a differing configuration to support the flip-chip die 32 B interconnect.

The above description of embodiments of the invention is intended to be illustrative and not limiting. Other embodiments of this invention will be obvious to those skilled in the art in view of the above disclosure and fall within the scope of the present invention.