Nonvolatile ferroelectric memory device

1. Field of the Invention

The present invention generally relates to a nonvolatile ferroelectric memory device, and more specifically, to a technology of improving speed of read/write operations depending on a process of serial data of a nonvolatile ferroelectric memory device having a multi-bit serial cell structure.

2. Description of the Related Art

In general, circuits having various functions are positioned together in a chip having a small area as a system structure has been complicated and developed to have high performance. However, the number of buses for transmitting data increases, which results in degradation of high integration. As a result, a method for transmitting serial data using a serial bus is applied.

FIG. 1 is a diagram illustrating a conventional nonvolatile ferroelectric memory device.

The conventional nonvolatile ferroelectric memory device comprises a 4-bit serial cell 1 and a switching transistor T 5 . Here, the serial cell 1 , which is connected serially between a bit line BL and the switching transistor T 5 , comprises a plurality of NMOS transistors T 1 ˜T 4 whose switching operations are controlled by each of word lines WL 1 ˜WL 4 .

The plurality of ferroelectric capacitors FC 1 ˜FC 4 are connected in parallel between the word lines WL 1 ˜WL 4 and nodes N 1 ˜N 4 , respectively. Also, the switching transistor T 5 , which is connected between the serial cell 1 and the bit line BL, has a gate to receive a write enable control signal WEC.

The serial cell 1 comprises a plurality of unit cells C which share one bit line BL. As a result, the write enable control signal WEC is activated in a write or restore operation, so that write data are written sequentially in four unit cells C.

Referring to FIGS. 2 and 3 , the operation of the above-described conventional nonvolatile ferroelectric memory device is explained.

At a read mode, the four unit cells are sequentially accessed to store sensed data sequentially in a register 2 . On the other hand, at a write (restore) mode, the data stored in the register 2 are sequentially restored in each unit cell C.

More specifically, in a period t 1 , when the word line WL 1 is activated at the read mode, the NMOS transistor T 1 is turned on. Then, a sense amplifier senses cell data applied through the bit line BL, and stores first cell data D 1 in the register 2 .

Thereafter, in a period t 2 , when the word line WL 2 is activated, the NMOS transistor T 2 is turned on. Then, the sense amplifier senses the cell data applied through the bit line BL, and stores second cell data D 2 in the register 2 . Here, the word line WL 1 is continuously kept at an active state, so that the cell data stored in the ferroelectric capacitor FC 2 are transmitted to the bit line BL.

Thereafter, in a period t 3 , when the word line WL 3 is activated, the NMOS transistor T 3 is turned on. Then, the sense amplifier senses cell data applied through the bit line BL, and stores third cell data D 3 in the register 2 . Here, the word lines WL 1 and WL 2 are continuously kept at an active state, so that the cell data stored in the ferroelectric capacitor FC 3 are transmitted to the bit line BL.

Next, in a period t 4 , when the word line WL 4 is activated, the NMOS transistor T 4 is turned on. Then, the sense amplifier senses the cell data applied through the bit line BL, and stores fourth cell data D 4 in the register 2 . Here, the word lines WL 1 ˜WL 3 are continuously kept at an active state, so that the cell data stored in the ferroelectric capacitor FC 4 are transmitted to the bit line BL.

Here, a restore operation is not performed at the read mode in the periods t 1 ˜t 4 . After the final cell data D 4 is read in the period t 4 , the first cell data D 1 is restored in the cell C from a period t 5 .

That is, at a write (restore) mode, when the write enable control signal WEC is activated, the switching transistor T 5 is turned on.

Then, in the period t 5 , the first cell data D 1 stored in the register 2 is stored in the ferroelectric capacitor FC 1 through the bit line BL. Thereafter, when the word line WL 1 transits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC 1 . Here, the word lines WL 2 ˜WL 4 are continuously kept at the active state, so that the cell data D 1 is transmitted to a node ND 1 .

Thereafter, in a period t 6 , the second cell data D 2 stored in the register 2 is stored in the ferroelectric capacitor FC 2 through the bit line BL. Then, the word line WL 2 transits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC 2 . Here, the word lines WL 3 ˜WL 4 are continuously kept at the active state, so that the cell data D 2 is transmitted to a node ND 2 .

Next, in a period t 7 , the third cell data D 3 stored in the register 2 is stored in the ferroelectric capacitor FC 3 through the bit line BL. Then, the word line WL 3 transmits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC 3 . Here, the word line WL 4 is continuously kept at the active state, so that the cell data D 3 is transmitted to a node ND 3 .

Then, in a period t 8 , the fourth cell data D 4 stored in the register 2 is stored in the ferroelectric capacitor FC 4 through the bit line BL. Thereafter, the word line WL 4 transits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC 4 .

However, in the conventional nonvolatile ferroelectric memory device, the read operation is required after the write operation of the four cell data D 1 ˜D 4 is performed. In other words, other cells cannot be accessed while the write operation is performed on the four cell data D 1 ˜D 4 .

As a result, since the conventional nonvolatile ferroelectric memory device requires an additional restore time after the sensing operation of the cell data, the data transmission speed is degraded in transmission of the successive serial data.

Accordingly, it is an object of the present invention to improve a successive transmission operation of serial data by dividing read bit lines and write bit lines in a multi-bit serial cell structure to individually control read/write paths.

In an embodiment, a nonvolatile ferroelectric memory device comprises a serial cell, a write switching element and a read switching element. The serial cell comprises a plurality of ferroelectric capacitors connected in parallel to a plurality of serially connected switching elements whose switching operations are selectively controlled depending on states of a plurality of word lines. The write switching element outputs cell data applied from a write bit line to the serial cell when a write enable control signal is activated. The read switching element outputs the cell data stored in the serial cell to a read bit line when a read enable control signal is activated.

In another embodiment, a nonvolatile ferroelectric memory device comprises a plurality of multi-bit serial cells, a plurality of read switching elements, a plurality of write switching elements, a plurality of sense amplifiers, a read control unit, a plurality of registers and a write control unit. The plurality of multi-bit serial cells are connected in serial between a pair of a plurality of read bit lines and a plurality of write bit lines which are arranged in row and column directions. The plurality of read switching elements selectively control connection of the plurality of read bit lines and the plurality of multi-bit serial cells. The plurality of write switching elements selectively control connection of the plurality of write bit lines and the plurality of multi-bit serial cells. The plurality of sense amplifiers are connected one by one to the plurality of read bit lines. The read control unit, connected one by one to the plurality of sense amplifiers, controls sensing operations of the plurality of sense amplifiers at a read mode. The plurality of registers store cell data sensed from the plurality of sense amplifiers. The write control unit, connected one by one to the plurality of write bit lines, outputs the cell data stored in the plurality of registers to the plurality of write bit lines at a write mode. Here, each of the plurality of multi-bit serial cells comprises: a plurality of switching elements whose switching operations are selectively controlled depending on states of a plurality of word lines; and a plurality of ferroelectric capacitors, connected in parallel to the plurality of switching elements, for storing the cell data.

In still another embodiment, a nonvolatile ferroelectric memory device comprises a plurality of sub bit lines, a plurality of serial cells, a global sense amplifier, a plurality of sub sense amplifiers, a register, a plurality of write switching elements and a plurality of read switching elements. The plurality of sub bit lines are connected to a read bit line. The plurality of serial cells are connected serially between the plurality of sub bit lines and a write bit line. The global sense amplifier, connected to one by one to the read bit line, senses and amplifies cell data applied to the read bit line. The plurality of sub sense amplifiers, connected one by one to the plurality of sub bit lines, sense cell data applied to the plurality of sub bit lines to output the cell data to the global sense amplifier. The register, connected between the global sense amplifier and the write bit line, stores the cell data applied from the global sense amplifier. The plurality of write switching elements outputs the cell data applied from the write bit line to the serial cell when a write enable control signal is activated. The plurality of read switching elements outputs the cell data stored in the plurality of serial cells to the plurality of sub bit lines when a read enable control signal is activated. Here, each of the plurality of serial cells comprises: a plurality of switching elements whose switching operations are selectively controlled depending on states of a plurality of word lines; and a plurality of ferroelectric capacitors, connected in parallel to the plurality of switching elements, for storing the cell data.

Other aspects and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 is a diagram illustrating a conventional nonvolatile ferroelectric memory device;

FIGS. 2 and 3 are diagrams illustrating the operation of the conventional nonvolatile ferroelectric memory device;

FIG. 4 is a diagram illustrating a nonvolatile ferroelectric memory device according to an embodiment of the present invention;

FIGS. 5 and 6 are diagrams illustrating the operation of the nonvolatile ferroelectric memory device according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating another example of the nonvolatile ferroelectric memory device according to an embodiment of the present invention;

FIG. 8 is a timing diagram illustrating the nonvolatile ferroelectric memory device of FIG. 7 ; and

FIGS. 9 to 11 are diagrams illustrating other examples of the nonvolatile ferroelectric memory device according to an embodiment of the present invention.

The present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a diagram illustrating a nonvolatile ferroelectric memory device according to an embodiment of the present invention.

In an embodiment, the nonvolatile ferroelectric memory device comprises a 4-bit serial cell 10 , a read switching element RT 1 and a write switching element WT 1 . Here, the read switching element RT 1 , which is connected between a read bit line R_BL and the serial cell 10 , has a gate to receive a read enable control signal REC. The write switching element WT 1 , which is connected between a write bit line W-BL and the serial cell 10 , has a gate to a write enable control signal WEC.

The serial cell 10 comprises NMOS transistors T 5 ˜T 8 which are connected serially between the read switching element RT 1 and the write switching element WT 1 and whose switching operations are controlled by word lines WL 1 ˜WL 4 , respectively. Also, the serial cell 10 comprises a plurality of ferroelectric capacitors FC 5 ˜FC 8 connected in parallel between the word lines WL 1 ˜WL 4 and nodes N 5 ˜N 8 .

The serial cell 10 is connected through the read switching element RT 1 to the read bit line R_BL and through the write switching element WT 1 to the write bit line W_BL.

Referring to FIGS. 5 and 6 , the operation of the nonvolatile ferroelectric memory device according to an embodiment of the present invention is explained.

At a read mode, when the read enable control signal REC is activated, four cell data are sequentially outputted to the read bit line R_BL and stored in a register 20 . On the other hand, at a write (restore) mode, a write enable control signal WEC is activated, the four cell data applied from the register 20 through the write bit line W_BL are sequentially stored in the serial cell 10 .

At the read mode, the read enable control signal REC is kept at an active state in periods t 1 ˜t 4 , so that the read switching element RT 1 is turned on.

In the period t 1 , when the word line WL 1 is activated, the NMOS transistor T 5 is turned on. Then, a sense amplifier senses the cell data applied through the read bit line R_BL, and stores first cell data D 1 in the register 20 .

Thereafter, in the period t 2 , when the word line WL 2 is activated, the NMOS transistor T 6 is turned on. Then, the sense amplifier senses the cell data applied through the read bit line R_BL, and stores second cell data D 2 in the register 20 . Here, the word line WL 1 is continuously kept at the active state, so that the cell data stored in the ferroelectric capacitor FC 6 are transmitted to the read bit line R_BL.

Thereafter, in the period t 3 , when the word line WL 3 is activated, the NMOS transistor T 7 is turned on. Then, the sense amplifier senses cell data applied through the read bit line R_BL, and stores third cell data D 3 in the register 20 . Here, the word lines WL 1 and WL 2 are continuously kept at the active state, so that the cell data stored in the ferroelectric capacitor FC 7 are transmitted to the read bit line R_BL.

Next, in the period t 4 , when the word line WL 4 is activated, the NMOS transistor T 8 is turned on. Then, the sense amplifier senses the cell data applied through the read bit line R_BL, and stores fourth cell data D 4 in the register 20 . Here, the word lines WL 1 ˜WL 3 are continuously kept at the active state, so that the cell data stored in the ferroelectric capacitor FC 8 are transmitted to the read bit line R_BL.

Here, a restore operation is not performed at the read mode in the periods t 1 ˜t 4 . After the final data D 4 is read in the period t 4 , the first cell data D 1 is restored in the cell C from a period t 5 .

That is, at a write (restore) mode, when the write enable control signal WEC is kept at the active state in periods t 5 ˜t 8 , the write switching transistor WT 1 is turned on.

Then, in the period t 5 , the first cell data D 1 stored in the register 20 is stored in the ferroelectric capacitor FC 5 through the write bit line W_BL. Thereafter, when the word line WL 1 transits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC 5 . Here, the word lines WL 2 ˜WL 4 are continuously kept at the active state, so that the cell data D 1 is transmitted to a node ND 5 .

Thereafter, in the period t 6 , the second cell data D 2 stored in the register 20 is stored in the ferroelectric capacitor FC 6 through the write bit line W_BL. Then, the word line WL 2 transits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC 6 . Here, the word lines WL 3 ˜WL 4 are continuously kept at the active state, so that the cell data D 2 is transmitted to a node ND 6 .

Next, in the period t 7 , the third cell data D 3 stored in the register 20 is stored in the ferroelectric capacitor FC 7 through the write bit line W_BL. Then, the word line WL 3 transmits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC 7 . Here, the word line WL 4 is continuously kept at the active state, so that the cell data D 3 is transmitted to a node ND 8 .

Then, in the period t 8 , the fourth cell data D 4 stored in the register 20 is stored in the ferroelectric capacitor FC 8 through the write bit line W_BL. Thereafter, the word line WL 4 transits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC 8 .

FIG. 7 is a diagram illustrating another example of the nonvolatile ferroelectric memory device according to an embodiment of the present invention.

In an embodiment, the nonvolatile ferroelectric memory device of FIG. 7 has a structure where serials cells 10 and 11 that have the same configuration as that of FIG. 4 are repeated in column direction. A plurality of serial cells 10 and 11 arranged in the column direction are connected in common to a read bit line R_BL and a write bit line W_BL.

Here, the 4-bit serial cell 10 comprises NMOS transistors T 5 ˜T 8 and ferroelectric capacitors FC 5 ˜FC 8 . The 4-bit serial cell 11 comprises NMOS transistors T 9 ˜T 12 and ferroelectric capacitors FC 9 ˜FC 12 .

The 4-bit serial cell 10 is connected through a read switching element RT 1 to the read bit line R_BL and through a writing switching element WT 1 to the write bit line W_BL. The 4-bit serial cell 11 is connected through a read switching element RT 2 to the read bit line R_BL and through a write switching element WT 2 to the write bit line W_BL.

FIG. 8 is a timing diagram illustrating the nonvolatile ferroelectric memory device of FIG. 7 .

At a read mode, when a read enable control signal REC is activated, four cell data are sequentially outputted to the read bit line R_BL. On the other hand, at a write (restore) mode, a write enable control signal WEC is activated, the four cell data applied from the register 20 through the write bit line W_BL are sequentially stored in the serial cells 10 and 11 .

At the read mode, a read enable control signal REC 1 is kept at an active state in periods t 1 ˜t 4 , so that the read switching element RT 1 is turned on.

In the period t 1 , when a word line WL 1 is activated, the NMOS transistor T 5 is turned on. Then, a sense amplifier senses the cell data applied through the read bit line R_BL, and stores first cell data D 1 in a register 20 .

Thereafter, in the period t 2 , when a word line WL 2 is activated, the NMOS transistor T 6 is turned on. Then, the sense amplifier senses the cell data applied through the read bit line R_BL, and stores second cell data D 2 in the register 20 . Here, the word line WL 1 is continuously kept at the active state, so that the cell data stored in the ferroelectric capacitor FC 6 are transmitted to the read bit line R_BL.

Thereafter, in the period t 3 , when a word line WL 3 is activated, the NMOS transistor T 7 is turned on. Then, the sense amplifier senses cell data applied through the read bit line R_BL, and stores third cell data D 3 in the register 20 . Here, the word lines WL 1 and WL 2 are continuously kept at the active state, so that the cell data stored in the ferroelectric capacitor FC 7 are transmitted to the read bit line R_BL.

Next, in the period t 4 , when a word line WL 4 is activated, the NMOS transistor T 8 is turned on. Then, the sense amplifier senses the cell data applied through the read bit line R_BL, and stores fourth cell data D 4 in the register 20 . Here, the word lines WL 1 ˜WL 3 are continuously kept at the active state, so that the cell data stored in the ferroelectric capacitor FC 8 are transmitted to the read bit line R_BL.

Here, a restore operation is not performed at the read mode in the periods t 1 ˜t 4 . After the final cell data D 4 is read in the period t 4 , the first cell data D 1 is restored in the serial cell C from a period t 5 .

That is, at a write (restore) mode, when a write enable control signal WEC 1 is kept at the active state in periods t 5 ˜t 8 , the write switching transistor WT 1 is turned on. At the same time, at the read mode of the serial cell 11 , a read enable control signal REC 2 is kept at an active state in the periods t 5 ˜t 8 , so that the read switching element RT 1 is turned on.

As a result, the write (restore) operation of the serial cell 10 and the read operation of the serial cell 11 can be simultaneously performed in the periods t 5 ˜t 8 .

At the write mode of the serial cell 10 , in the period t 5 , the first cell data D 1 stored in the register 20 is stored in the ferroelectric capacitor FC 5 through the write bit line W_BL. Thereafter, when the word line WL 1 transits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC 5 . Here, the word lines WL 2 ˜WL 4 are continuously kept at the active state, so that the cell data D 1 is transmitted to a node ND 5 .

Thereafter, in the period t 6 , the second cell data D 2 stored in the register 20 is stored in the ferroelectric capacitor FC 6 through the write bit line W_BL. Then, the word line WL 2 transits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC 6 . Here, the word lines WL 3 ˜WL 4 are continuously kept at the active state, so that the cell data D 2 is transmitted to a node ND 6 .

Next, in the period t 7 , the third cell data D 3 stored in the register 20 is stored in the ferroelectric capacitor FC 7 through the write bit line W_BL. Then, the word line WL 3 transmits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC 7 . Here, the word line WL 4 is continuously kept at the active state, so that the cell data D 3 is transmitted to a node ND 8 .

Then, in the period t 8 , the fourth cell data D 4 stored in the register 20 is stored in the ferroelectric capacitor FC 8 through the write bit line W_BL. Thereafter, the word line WL 4 transits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC 8 .

Meanwhile, at the read mode of the serial cell 11 , the read enable control signal REC 2 is continuously kept at an active state in the periods t 5 ˜t 8 , so that the read switching element RT 2 is turned on.

In the period t 5 , when a word line WL 5 is activated, the NMOS transistor T 9 is turned on. Then, the sense amplifier senses the cell data applied through the read bit line R_BL, and stores first cell data D 5 in the register 20 .

Thereafter, in the period t 6 , when a word line WL 6 is activated, the NMOS transistor T 10 is turned on. Then, the sense amplifier senses the cell data applied through the read bit line R_BL, and stores second cell data D 6 in the register 20 . Here, the word line WL 5 is continuously kept at an active state, so that the cell data stored in the ferroelectric capacitor FC 10 are transmitted to the read bit line R_BL.

Thereafter, in the period t 7 , when a word line WL 7 is activated, the NMOS transistor T 11 is turned on. Then, the sense amplifier senses cell data applied through the read bit line R_BL, and stores third cell data D 7 in the register 20 . Here, the word lines WL 5 and WL 6 are continuously kept at the active state, so that the cell data stored in the ferroelectric capacitor FC 11 are transmitted to the read bit line R_BL.

Next, in the period t 8 , when a word line WL 8 is activated, the NMOS transistor T 12 is turned on. Then, the sense amplifier senses the cell data applied through the read bit line R_BL, and stores fourth cell data D 8 in the register 20 . Here, the word lines WL 5 ˜WL 7 are continuously kept at the active state, so that the cell data stored in the ferroelectric capacitor FC 12 are transmitted to the read bit line R_BL.

Here, after the final cell data D 8 of the serial cell 11 is read in the period t 8 , the first cell data D 5 of the serial cell 11 is restored in the cell C from a period t 9 .

At the write mode of the serial cell 11 , the first cell data D 5 stored in the register 20 is stored in the ferroelectric capacitor FC 9 through the write bit line W_BL in the period t 9 . Thereafter, when the word line WL 5 transits from ‘high’ to ‘low’, low data are written for a half cycle and high data are written in the ferroelectric capacitor FC 5 for the rest half cycle. Here, the word lines WL 6 ˜WL 8 are continuously kept at the active state, so that the cell data D 5 is transmitted to a node ND 9 .

Then, in a period t 10 , the second cell data D 6 stored in the register 20 is stored in the ferroelectric capacitor FC 10 through the write bit line W_BL. Next, when the word line WL 6 transits from ‘high’ to ‘low’, low data are written for a half cycle, and high data are written in the ferroelectric capacitor FC 10 for the rest half cycle. Here, the word lines WL 7 ˜WL 8 are continuously kept at the active state, so that the cell data D 6 is transmitted to a node ND 10 .

In a period t 11 , the third cell data D 7 stored in the register 20 is stored in the ferroelectric capacitor FC 11 through the write bit line W_BL. Then, when the word line WL 7 transits from ‘high’ to ‘low’, low data are written for a half cycle, and high data are written in the ferroelectric capacitor FC 11 for the rest half cycle. Here, the word line WL 8 is continuously kept at the active state, so that the cell data D 7 is transmitted to a node ND 12 .

Next, in a period t 12 , the fourth cell data D 8 stored in the register 20 is stored in the ferroelectric capacitor FC 12 through the write bit line W_BL. Then, when the word line W 18 transits from ‘high’ to ‘low’, low data are written for a half cycle, and high data are written in the ferroelectric capacitor FC 12 for the rest half cycle.

FIG. 9 is a diagram illustrating still another example of the nonvolatile ferroelectric memory device according to an embodiment of the present invention.

In an embodiment, the nonvolatile ferroelectric memory device of FIG. 9 has a structure where a plurality of 4-bit serial cells 10 and 11 are repeated in row and column directions. The plurality of serial cells 10 and 11 arranged in the column direction are connected in common to a read bit line R_BL and a write bit line W_BL, respectively.

Here, the read bit line R_BL is connected to a sense amplifier 30 , and the write bit line W_BL is connected to a register 20 . A read control unit 40 connected to the sense amplifier 30 controls read operations of the serial cells 10 and 11 . A write control unit 50 connected to the register 20 and the write bit line W_BL controls write operations of the serial cells 10 and 11 .

In the embodiment of FIG. 9 , at a read mode, when a read enable control signal REC is activated, four cell data applied from the serial cell 10 or 11 are sequentially outputted to the read bit line R_BL and applied to the sense amplifier 30 . The sense amplifier 30 stores the cell data applied from the read bit line R_BL in the register 20 depending on the control of the read control unit 40 .

On the other hand, at a write (restore) mode, when a write enable control signal WEC is activated, the cell data stored in the register 20 are outputted to the write bit line W_BL depending on the control of the write control unit 50 . The four cell data applied from the write bit lien W_BL are sequentially stored in the serial cell 10 or 11 .

FIG. 10 is a diagram illustrating still another example of the nonvolatile ferroelectric memory device according to an embodiment of the present invention.

In the embodiment of FIG. 10 , a multi-bit serial cell 60 comprises a plurality of NMOS transistors T 1 ˜Tm which are connected serially between a read switching element RT 1 and a write switching element WT 1 and whose switching operations are controlled by word lines WL 1 ˜WLm, respectively. The plurality of ferroelectric capacitors FC 1 ˜FCm are connected in parallel between the word lines WL˜WLm and nodes N 1 ˜Nm.

Here, the multi-bit serial cell 60 is connected through the read switching element RT 1 to a read bit line R_BL and through the write switching element WT 1 to a write bit line W_BL.

Also, the nonvolatile ferroelectric memory device of FIG. 10 has a structure where a plurality of the multi-bit serial cells 60 are repeated in row and column directions. The plurality of the multi-bit serial cells 60 arranged in the column direction are connected in common to the read bit line R_BL and the write bit line W_BL.

FIG. 11 is a diagram illustrating still another example of the nonvolatile ferroelectric memory device according to an embodiment of the present invention.

In the embodiment of FIG. 11 , one read bit line R_BL is connected one by one to one global sense amplifier 80 . The nonvolatile ferroelectric memory device of FIG. 11 has a hierarchical bit line structure including one read bit line R_BL connected through a plurality of sub sense amplifiers 90 to a plurality of sub bit lines S_BL. As a result, the sub sense amplifier 90 senses cell data applied from the sub bit line S_BL to output the cell data to the read bit line R_BL.

A plurality of 4-bit serial cells 70 and 71 are connected to one sub bit line S_BL. The plurality of 4-bit serial cells 70 and 71 are repeatedly arranged in row and column directions. The write bit line W_BL is connected to a register 100 , and the cell data stored in the register 100 are written through the write bit line W_BL in the plurality of 4-bit serial cells 70 and 71 .

As described above, in a nonvolatile ferroelectric memory device according to an embodiment of the present invention, read/write paths are individually controlled, so that an additional restore time is not required after a sensing operation of cell data, thereby improving a successive transmission operation of serial data.

While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that the invention is not limited to the particular forms disclosed. Rather, the invention covers all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined in the appended claims.