Rectifier circuit

This application is based upon and claims the benefits of priority from the prior Japanese Patent Application No. 2004-287606, filed on Sep. 30, 2004, the entire contents of which are incorporated herein by reference.

1. Field of the Invention

The present invention relates to a rectifier circuit, and particularly to a rectifier circuit for rectifying a voltage.

2. Description of the Related Art

At present, importance of rectifier circuits that operate at a low voltage is growing with a tendency toward compact and portable systems. Such rectifier circuits are used, for example, in IC cards or ID chips which cannot contain a battery as a power supply. In the IC cards or ID chips, an electric power is taken out from radio wave radiation energy, and voltage reduction is prevented by the rectifier circuits that operate at a low voltage, whereby a wider communicable range is realized. A diode or Metal Oxide Semiconductor (MOS) transistor that is turned on and off according to the magnitude relation in voltages between two terminals is used in the rectifier circuit (see, e.g., Udo Karthaus et al., “Fully Integrated Passive UHF RFID Transponder IC with 16.7-uW Minimum RF Input Power”, IEEE J. Solid-State Circuits, Vol.38, No. 10, p.1602-1608, October 2003, Yasuo Nantoh, “Electronic Circuit and Analogue IC”, p.174, Kougakutosho Ltd.).

FIG. 17 is a circuit diagram of a diode-connected NMOS transistor. As shown in the diagram, a gate and a drain are connected in an NMOS transistor M 101 . Herein, a voltage of the drain is designated as a voltage Va, a voltage of the source is designated as a voltage Vb, and a threshold voltage of the transistor M 101 is designated as a threshold voltage Vthn. In this case, when the following formula (1) is satisfied, a current flows from the drain to the source.

Va≧Vb+Vthn   (1)

More specifically, when the voltage Va of the drain is higher than the voltage Vb of the source by the threshold voltage Vthn, the transistor M 101 is turned on and a current is allowed to flow. On the other hand, when the voltage Va of the drain is not higher than the voltage Vb of the source by the threshold voltage Vthn, the transistor M 101 is turned off and no current is allowed to flow.

FIG. 18 is a circuit diagram of a diode-connected PMOS transistor. As shown in the diagram, a gate and a drain are connected in a PMOS transistor M 102 . Herein, a voltage of the source is designated as a voltage Va, a voltage of the drain is designated as a voltage Vb, and a threshold voltage of the transistor M 102 is designated as a threshold voltage Vthp. In this case, when the following formula (2) is satisfied, a current flows from the source to the drain.

Va≧Vb+Vthp   (2)

More specifically, when the voltage Va of the source is higher than the voltage Vb of the drain by the threshold voltage Vthp, the transistor M 102 is turned on and a current is allowed to flow. On the other hand, when the voltage Va of the source is not higher than the voltage Vb of the drain by the threshold voltage Vthp, the transistor M 102 is turned off and no current is allowed to flow.

In a diode, when a voltage of an anode is higher than one of a cathode by a forward voltage Vf or more, a current is allowed to flow.

As described above, since the threshold voltage for turning on a switch (transistor or diode) is present in the rectifier circuit, a conduction loss occurs during the rectification. This conduction loss can be improved by reducing the threshold voltage. Further, it means that accuracy of the determination of whether a switch is turned on/off at the input of a small signal can be improved by reducing the threshold voltage. For reducing the threshold voltage, a schottky diode having a low forward voltage and a MOS transistor having a low threshold voltage are used.

However, when configuring the rectifier circuit by employing a semiconductor integrated circuit, the following problems arise. The schottky diode or the MOS transistor having a low threshold voltage is realized by addition of process steps and as a result, costs are increased.

In addition, the diode or the transistor is different from other diodes or MOS transistors in the manufacturing process and therefore, variation in the devices is caused.

In view of the foregoing, it is an object of the present invention to provide a rectifier circuit that realizes a low threshold voltage without using a process step so as to enable reduction in costs and in variation of devices.

To accomplish the above object, according to the present invention, there is provided a rectifier circuit for rectifying a voltage. This rectifier circuit comprises a transistor, and a threshold voltage generator that outputs a voltage near a threshold voltage to a gate of the transistor, the voltage near the threshold voltage being based on one of two nodes serving as a drain and a source.

The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.

FIG. 1 is a circuit diagram of a rectifier circuit according to a first embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of a threshold voltage generator of FIG. 1 .

FIG. 3 is a circuit diagram where an attenuator is added to the circuit of FIG. 2 .

FIG. 4 is a detailed circuit diagram of the attenuator of FIG. 3 .

FIG. 5 is a diagram of a circuit for controlling an attenuator.

FIG. 6 shows voltage-current characteristics of a diode-connected transistor.

FIG. 7 is a circuit diagram of a rectifier circuit according to a second embodiment of the present invention.

FIG. 8 is a detailed circuit diagram of a threshold voltage generator of FIG. 7 .

FIG. 9 is a circuit diagram where an attenuator is added to the circuit of FIG. 8 .

FIG. 10 is a detailed circuit diagram of the attenuator of FIG. 9 .

FIG. 11 is a diagram showing rectification results.

FIG. 12 is a diagram of a circuit for controlling an attenuator.

FIG. 13 is a circuit diagram of a half-wave double voltage rectifier to which the rectifier circuits according to the first and second embodiments of the present invention are applied.

FIG. 14 is a circuit diagram of a half-wave quadruple voltage rectifier to which rectifier circuits according to the first and second embodiments of the present invention are applied.

FIG. 15 is a circuit diagram of a bipolar rectifier to which the rectifier circuits according to the first and second embodiments of the present invention are applied.

FIG. 16 is a block diagram of an IC card.

FIG. 17 is a circuit diagram of a diode-connected NMOS transistor.

FIG. 18 is a circuit diagram of a diode-connected PMOS transistor.

A first embodiment of the present invention will be described in detail below with reference to the accompanying drawings, wherein like reference numerals refer to like elements throughout.

FIG. 1 is a circuit diagram of a rectifier circuit according to the first embodiment of the present invention. An NMOS transistor M 1 shown in the diagram has a threshold voltage Vthn 1 . Nodes N 1 and N 2 serve as a drain and source of the transistor M 1 . A voltage Va to be rectified is inputted to the node N 2 and a rectified voltage Vb is outputted to the node N 1 .

A threshold voltage generator 11 is connected to a gate of the transistor M 1 and the node N 1 . The threshold voltage generator 11 generates a voltage Vth 1 and outputs it to the gate of the transistor M 1 . The voltage Vth 1 is a voltage which is elevated by the threshold voltage Vthn 1 with respect to a voltage of the node N 1 and is decreased by a voltage ΔVthn sufficiently small with respect to the threshold voltage Vthn 1 .

In this circuit, when the voltage Va is lower than the voltage Vb, an electron flows from the node 2 to the node 1 . Therefore, the node N 2 serves as the source. Therefore, when the voltage at the gate of the transistor M 1 is higher than the voltage Va of the node N 2 by the threshold voltage Vthn 1 , the transistor M 1 is turned on to allow a current to flow from the node N 1 to the node N 2 . As described above, to the gate of the transistor M 1 , the voltage Vth 1 is inputted, which is higher than the voltage of the node N 1 by the threshold voltage Vthn 1 of the transistor M 1 and is lower than the threshold voltage Vthn 1 by the voltage ΔVthn. Therefore, when the voltage Va is lower than the voltage Vb by the voltage ΔVthn, the transistor M 1 is turned on. More specifically, when the voltage Va is lower than the voltage Vb by the voltage ΔVthn or more, a voltage equal to or more than the threshold voltage Vthn 1 is applied to the node N 2 and the gate of the transistor M 1 . As a result, the transistor Ml is turned on.

On the other hand, when the voltage Va is higher than the voltage Vb, an electron flows from the node N 1 to the node N 2 . Therefore, the node N 1 serves as the source. To the gate of the transistor M 1 , the threshold voltage generator 11 inputs the voltage Vth 1 which is higher than a voltage of the node N 1 by the threshold voltage Vthn 1 of the transistor M 1 and is lower than the threshold voltage Vthn 1 by the voltage ΔVthn. Therefore, the transistor M 1 is not turned on.

As described above, the circuit is designed such that to the gate of the transistor M 1 , the threshold voltage generator 11 inputs the voltage Vth 1 which is lower than the threshold voltage Vthn 1 by the voltage ΔVthn. Therefore, the threshold voltage Vthn 1 can be reduced to the voltage ΔVthn not by a process step but by the circuit for generating a voltage. As a result, the cost and the variation in devices can be reduced. As the voltage ΔVthn is smaller, the threshold voltage that turns on the transistor M 1 is more reduced.

The threshold voltage generator 11 is described in detail.

FIG. 2 is a detailed circuit diagram of the threshold voltage generator of FIG. 1 . In the diagram, the same elements as those in FIG. 1 are indicated by the same reference numerals as in FIG. 1 and their descriptions are omitted. As shown in the diagram, a series circuit of a diode-connected NMOS transistor M 2 and a resistor R 1 is connected to the node N 1 . A connection point of the transistor M 2 and the resistor R 1 is connected to the gate of the transistor M 1 . A capacitor C 1 for keeping the rectified voltage Vb constant is connected in parallel to the series circuit of the transistor M 2 and the resistor RI. The connection point of the transistor M 2 and the resistor R 1 is designated as a node N 3 . An end of the resistor R 1 , which is not connected to the transistor M 2 , is designated as a node N 4 . The rectifier circuit shown in the diagram is formed into one semiconductor integrated circuit. In the transistors M 1 and M 2 , gate lengths and gate widths are formed so that the threshold voltage Vthn 1 of the transistor M 1 may be a little larger than the threshold voltage Vthn 2 of the transistor M 2 (larger than the Vthn 2 by the voltage ΔVthn). The transistors M 1 and M 2 are almost the same in values of the threshold voltages Vthn 1 and Vthn 2 and therefore, are almost the same also in the gate length and the gate width. As a result, the transistors M 1 and M 2 can be formed by the same process step.

A voltage higher than that of the node N 1 is applied to the node N 4 so that the transistor M 2 may be turned on. By doing so, a current flows from the node N 4 to the node N 1 . As a result, the voltage of the node N 3 is elevated by the threshold voltage Vthn 2 with respect to that of the node N 1 by means of the diode-connected transistor M 2 . Further, a voltage higher than that of the node N 1 by the threshold voltage Vthn 2 is inputted to the gate of the transistor M 1 .

When the voltage Va of the node N 2 is lower than the voltage Vb of the node N 1 by the voltage ΔVthn, a potential difference of the threshold voltage Vthn 1 is applied between the node N 2 and the gate of the transistor M 1 . By doing so, the transistor M 1 is turned on and as a result, the threshold voltage Vthn 1 of the transistor M 1 can be reduced to the voltage ΔVthn.

Operations in FIG. 2 are described using specific values. Assume that the threshold voltage Vthn 1 of the transistor M 1 and the threshold voltage Vthn 2 of the transistor M 2 are 0.6 volt and 0.5 volt, respectively. Also, assume that the voltage Vb is 0 volt and that the voltage ΔVthn is 0.1 volt.

When the voltage Va of the node N 2 is equal to or less than −0.1 volt, an electron flows from the node N 2 to the node N 1 . Therefore, the node N 2 serves as the source. Since a voltage of 0.5 volt is inputted to the gate of the transistor M 1 by the diode-connected transistor M 2 , a potential difference between the node N 2 and the gate of the transistor M 1 is equal to or more than 0.6 volt. As a result, the transistor M 1 is turned on and a current is allowed to flow from the node N 1 to the node N 2 .

On the other hand, when the voltage Va is from −0.1 to 0 volt, the potential difference between the node N 2 and the gate of the transistor M 1 is smaller than the threshold voltage Vthn 1 of 0.6 volt. As a result, the transistor M 1 is turned off. Further, when the voltage Va is larger than 0 volt, an electron flows from the node N 1 to the node N 2 . Therefore, the node N 1 serves as the source. With respect to a voltage of the node N 1 of 0 volt, a voltage of 0.5 volt is inputted to the gate of the transistor M 1 by the transistor M 2 . Therefore, the transistor M 1 is in an off-state.

As described above, even if the voltage of the node N 2 fails in decreasing to 0.6 volt or more lower than the voltage of the node N 1 , when the voltage ΔVthn decreases by 0.1 volt or more, the transistor M 1 is turned on. Thus, the threshold voltage that turns on the transistor M 1 can be reduced.

FIG. 3 is a circuit diagram where an attenuator is added to a circuit of FIG. 2 . In the diagram, the same elements as those in FIG. 2 are indicated by the same reference numerals as in FIG. 2 and their descriptions are omitted. As shown in the diagram, an attenuator 12 connected to the gate of the transistor M 1 is connected to a connection point of the transistor M 2 and the resistor R 1 .

A voltage higher than that of the node N 1 is applied to the node N 4 so that the transistor M 2 may be turned on. By doing so, a current flows from the node N 3 to the node N 1 . As a result, the voltage of the node N 3 is elevated by the threshold voltage Vthn 2 with respect to that of the node N 1 by means of the diode-connected transistor M 2 . The attenuator 12 attenuates the voltage of the node N 3 by a voltage ΔVde and outputs the resulting voltage to the gate of the transistor M 1 . More specifically, the transistor M 1 is turned on when the voltage Va of the node N 2 is lower than the voltage Vb of the node N 1 by a voltage obtained by addition of the voltage ΔVthn and the voltage ΔVde.

When the threshold voltage Vthn 1 of the transistor M 1 is fairly close to the threshold voltage Vthn 2 of the transistor M 2 , it is feared that a leakage current flows through the transistor M 1 . Therefore, when a voltage inputted to the gate of the transistor M 1 is attenuated by the attenuator 12 , the leakage current can be suppressed and the rectification efficiency can be enhanced.

Operations in FIG. 3 are described by using specific values. Assume that the threshold voltage Vthn 1 of the transistor M 1 and the threshold voltage Vthn 2 of the transistor M 2 are 0.6 volt and 0.5 volt, respectively. Assume that the attenuator 12 attenuates the voltage of the node N 3 by a voltage of 0.1 volt and outputs the resulting voltage to the gate of the transistor M 1 . Also, assume that the voltage Vb is 0 volt. Accordingly, the voltage of the node N 3 is determined to be 0.5 volt by the transistor M 2 . To the gate of the transistor M 1 , a voltage of 0.4 volt is inputted by the attenuator 12 .

When the voltage Va of the node N 2 is equal to or less than −0.2 volt, an electron flows from the node N 2 to the node N 1 . Therefore, the node N 2 serves as the source. Since a voltage of 0.4 volt is inputted to the gate of the transistor M 1 , a potential difference between the node N 2 and the gate of the transistor M 1 is equal to or more than 0.6 volt. As a result, the transistor M 1 is turned on and a current is allowed to flow from the node N 1 to the node N 2 .

On the other hand, when the voltage Va is from −0.2 to 0 volt, the potential difference between the node N 2 and the gate of the transistor M 1 is smaller than the threshold voltage Vthn 1 of 0.6 volt. As a result, the transistor M 1 is turned off. Further, when the voltage Va is larger than 0 volt, an electron flows from the node N 1 to the node N 2 . Therefore, the node N 1 serves as the source. With respect to a voltage at the node N 1 of 0 volt, a voltage of 0.4 volt is inputted to the gate of the transistor M 1 by the transistor M 2 and the attenuator 12 . Therefore, the transistor M 1 is in an off-state.

As described above, in the case of using no attenuator 12 , the transistor M 1 is turned on when the voltage of the node N 2 is lower than that of the node N 1 by 0.1 volt or more. On the other hand, in the case of using the attenuator 12 of FIG. 3 , the transistor M 1 is turned on when the voltage of the node N 2 is lower than that of the node N 1 by 0.2 volt or more by means of the attenuator 12 . More specifically, when the attenuator 12 reduces a voltage inputted to the gate of the transistor M 1 , a threshold voltage that turns on the transistor M 1 can be increased.

When using the attenuator 12 , the transistors M 1 and M 2 can be formed into one semiconductor integrated circuit so as to have the same threshold voltage. This is because the attenuator 12 can determine the threshold voltage that turns on the transistor M 1 . This leads to facilitation of the design and the manufacture.

The attenuator 12 is described in detail.

FIG. 4 is a detailed circuit diagram of the attenuator of FIG. 3 . In the diagram, the same elements as those in FIG. 3 are indicated by the same reference numerals as in FIG. 3 and their descriptions are omitted. As shown in the diagram, a resistor R 2 is connected between the node N 3 and the gate of the transistor M 1 . Further, a resistor R 3 is connected between the gate of the transistor M 1 and the node N 1 . The resistors R 2 and R 3 correspond to the attenuator 12 of FIG. 2 .

A current scarcely flows through the gate of the transistor M 1 . Therefore, the voltage at the gate of the transistor M 1 is determined by a resistance ratio between the resistors R 2 and R 3 . For example, in an example of the numerical values described above, the voltage of the node N 3 is 0.5 volt and the voltage of the node N 1 is 0 volt. Accordingly, the resistance values of the resistors R 2 and R 3 may be determined such that the voltage at the gate of the transistor M 1 becomes 0.4 volt.

By thus dividing the voltage between the node N 1 and the node N 3 by the resistors R 2 and R 3 , the attenuator 12 can be readily configured. Therefore, the rectifier circuit is readily designed and manufactured.

When the rectifier circuit is applied to an IC card or an ID tag, the voltage Va inputted is extremely reduced depending on the distance between the card or the tag and a reader/writer that supplies power. In this case, in the rectifier circuits shown in FIGS. 3 and 4 , the threshold voltage that turns on the transistor M 1 is increased by the attenuator 12 and therefore, the voltage Va cannot be rectified in some cases. Accordingly, when the voltage Va inputted is small, the attenuator 12 is inactivated to allow the voltage of the node N 3 to be directly inputted to the gate of the transistor M 1 .

FIG. 5 is a diagram of a circuit for controlling an attenuator. In the diagram, the same elements as those in FIG. 4 are indicated by the same reference numerals as in FIG. 4 and their descriptions are omitted. As shown in the diagram, an NMOS transistor M 3 is connected between the node N 1 and the resistor R 3 . The gate of the transistor M 3 is connected to the node N 4 .

A voltage proportional to the voltage Vb is inputted to the node N 4 . When the voltage Va is reduced to a voltage that turns off the transistor M 1 , the transistor M 3 is turned off to thereby cut off the connection between the resistor R 3 and the node N 1 . More specifically, when the voltage Va is reduced to a voltage that turns off the transistor M 1 , the threshold voltage Vthn 2 of the diode-connected transistor M 2 is inputted to the gate of the transistor M 1 without the attenuation. As a result, the threshold voltage that turns on the transistor M 1 is reduced. Thus, the voltage Va inputted can be rectified even if it is reduced. In addition, a communicable range of IC cards or ID tags can be widened.

The voltage Vth 1 inputted to the gate of the transistor M 1 is described below.

FIG. 6 shows voltage-current characteristics of a diode-connected transistor. In the diagram, a VGS of the horizontal axis shows a voltage between the gate and the source, and an ID of the vertical axis shows a drain current. In the diode-connected transistor, the drain current flows when the VGS exceeds the threshold voltage Vthn as shown in the diagram. Therefore, as shown in FIGS. 1 to 5 , a voltage that is lower than the threshold voltage Vthn 1 by the voltage ΔVthn is inputted to the gate of the transistor M 1 and thereby, a threshold voltage that turns on the transistor M 1 is reduced. The voltage inputted to the gate of the transistor M 1 is preferably a voltage infinitely close to the threshold voltage Vthn 1 . However, the voltage is more preferably about 95% of the threshold voltage Vthn 1 , with a tolerance not to allow the transistor M 1 to be turned on due to a leakage current. Further, when the lower limit of the voltage inputted to the gate of the transistor M 1 is excessively reduced, the threshold voltage that turns on the transistor M 1 is increased. Therefore, the lower limit thereof is preferably about 50% of the threshold voltage Vthn 1 .

A second embodiment of the present invention will be described in detail below with reference to the accompanying drawings, wherein like reference numerals refer to like elements throughout. The NMOS transistor is described in the first embodiment. Next, a PMOS transistor is described in the second embodiment.

FIG. 7 is a circuit diagram of a rectifier circuit according to the second embodiment of the present invention. A PMOS transistor M 11 shown in the diagram has a threshold voltage Vthp 1 . Nodes N 11 and N 12 each serve as a drain and source of the transistor M 11 . The voltage Va to be rectified is inputted to the node N 12 and the rectified voltage Vb is outputted to the node N 11 .

The threshold voltage generator 21 is connected to the gate of the transistor M 11 and the node N 11 . The threshold voltage generator 21 generates a voltage Vthh and outputs it to the gate of the transistor M 11 . The voltage Vthh is a voltage which is decreased by the threshold voltage Vthp 1 with respect to a voltage of the node N 11 and is elevated by a voltage ΔVthp sufficiently small with respect to the threshold voltage Vthp 1 .

In the circuit, when the voltage Va is higher than the voltage Vb, a positive charge flows from the node N 12 to the node N 11 . Therefore, the node N 12 serves as the source. Accordingly, when the voltage of the gate of the transistor M 11 is lower than the voltage Va of the node N 12 by the threshold voltage Vthp 1 , the transistor M 11 is turned on to allow a current to flow from the node N 12 to the node N 11 . As described above, to the gate of the transistor M 11 , the voltage Vthh is inputted, which is lower than a voltage of the node N 11 by the threshold voltage Vthp 1 of the transistor M 11 and is higher than the threshold voltage Vthp 1 by a sufficiently small voltage ΔVthp. When the voltage Va is higher than the voltage Vb by the voltage ΔVthp, the transistor M 11 is turned on. More specifically, when the voltage Va is higher than the voltage VB by the voltage ΔVthp or more, a voltage equal to or more than the threshold voltage Vthp 1 is applied to the node N 12 and the gate of the transistor M 11 . As a result, the transistor M 11 is turned on.

When the voltage Va is lower than the voltage Vb, a positive charge flows from the node N 11 to the node N 12 . Therefore, the node N 11 serves as the source. To the gate of the transistor M 11 , the threshold voltage generator 21 inputs the voltage Vthh which is lower than a voltage of the node N 11 by the threshold voltage Vthp 1 of the transistor M 11 and is higher than the threshold voltage Vthp 1 by the voltage ΔVthp. Therefore, the transistor M 11 is not turned on.

As described above, the circuit is designed such that to the gate of the transistor M 11 , the threshold voltage generator 21 inputs the voltage Vthh which is higher than the threshold voltage Vthp 1 by the voltage ΔVthp. Therefore, the threshold voltage Vthp 1 can be reduced to the voltage ΔVthp not by a process step but by the circuit. As a result, the cost and the variation in devices can be reduced. As the voltage ΔVthp is smaller, the threshold voltage that turns on the transistor M 11 is more reduced.

The threshold voltage generator 21 is described in detail.

FIG. 8 is a detailed circuit diagram of a threshold voltage generator of FIG. 7 . In the diagram, the same elements as those in FIG. 7 are indicated by the same reference numerals as in FIG. 7 and their descriptions are omitted. As shown in the diagram, a series circuit of a diode-connected PMOS transistor M 12 and a resistor R 11 is connected to the node N 11 . A connection point of the transistor M 12 and the resistor R 11 is connected to the gate of the transistor M 11 . A capacitor C 11 that keeps the rectified voltage Vb constant is connected in parallel to the series circuit of the transistor M 12 and the resistor R 11 . The connection point of the transistor M 12 and the resistor R 11 is designated as the node N 13 . An end of the resistor R 11 , which is not connected to the transistor M 12 , is designated as a node N 14 . Further, a rectifier circuit shown in the diagram is formed into one semiconductor integrated circuit. In the transistors M 11 and M 12 , gate lengths and gate widths thereof are formed so that the threshold voltage Vthp 1 of the transistor M 11 may be a little larger than the threshold voltage Vthp 2 of the transistor M 12 (larger than the Vthp 2 by the voltage ΔVthp). The transistors M 11 and M 12 are almost the same in values of the threshold voltages Vthp 1 and Vthp 2 and therefore, are almost the same also in the gate length and the gate width. As a result, the transistors M 11 and M 12 can be formed by the same process step.

A voltage lower than that of the node N 11 is applied to the node N 14 so that the transistor M 12 may be turned on. By doing so, the current flows from the node N 11 to the node N 14 . As a result, the voltage of the node N 13 is decreased by the threshold voltage Vthp 2 with respect to that of the node N 11 by means of the diode-connected transistor M 12 . Further, a voltage lower than that of the node N 11 by the threshold voltage Vthp 2 is inputted to the gate of the transistor M 11 .

When the voltage Va of the node N 12 is higher than the voltage Vb of the node N 11 by the voltage ΔVthp, a potential difference of the threshold voltage Vthp 1 is applied between the node N 12 and the gate of the transistor M 11 . By doing so, the transistor M 11 is turned on, and as a result the threshold voltage Vthp 1 of the transistor M 11 can be reduced to the voltage ΔVthp.

Operations in FIG. 8 are described by using specific values. Assume that the threshold voltage Vthp 1 of the transistor M 11 and the threshold voltage Vthp 2 of the transistor M 12 are 1.1 volts and 1.0 volt, respectively. Also, assume that the voltage Vb is 2 volts and that the voltage ΔVthp is 0.1 volt.

When the voltage Va of the node N 12 is equal to or more than 2.1 volts, a positive charge flows from the node N 12 to the node N 11 . Therefore, the node N 12 serves as the source. Since a voltage of 1.0 volt is inputted to the gate of the transistor M 11 by the diode-connected transistor M 12 , a potential difference between the node N 12 and the gate of the transistor M 11 is equal to or more than 1.1 volts. As a result, the transistor M 11 is turned on and a current is allowed to flow from the node N 12 to the node N 11 .

On the other hand, when the voltage Va is from 2.1 to 2 volts, the potential difference between the node N 12 and the gate of the transistor M 11 is smaller than the threshold voltage Vthp 1 of 1.1 volts. As a result, the transistor M 11 is turned off. Further, when the voltage Va is smaller than 2 volts, a positive charge flows from the node N 11 to the node N 12 . Therefore, the node N 11 serves as the source. With respect to the voltage of the node N 11 of 2 volts, a voltage of 1.0 volt is inputted to the gate of the transistor M 11 by the transistor M 12 . Therefore, the transistor M 11 is in an off-state.

As described above, even if the voltage of the node N 12 fails in increasing to 1.1 volts or more higher than the voltage of the node N 11 , when the voltage ΔVthp increases by 0.1 volt or more, the transistor M 11 is turned on. Thus, the threshold voltage that turns on the transistor M 11 can be reduced.

FIG. 9 is a circuit diagram where an attenuator is added to the circuit of FIG. 8 . In the diagram, the same elements as those in FIG. 8 are indicated by the same reference numerals as in FIG. 8 and their descriptions are omitted. As shown in the diagram, the attenuator 22 connected to the gate of the transistor M 11 is connected to a connection point of the transistor M 12 and the resistor R 11 .

A voltage lower than that of the node N 11 is applied to the node N 14 to turn on the transistor 12 . By doing so, a current flows from the node N 11 to the node N 13 . The voltage of the node N 13 is decreased by the threshold voltage Vthp 2 with respect to the voltage of the node N 11 by means of the diode-connected transistor M 12 . The attenuator 22 attenuates the voltage at the gate of the transistor M 11 by a voltage ΔVde and outputs the resulting voltage to the node N 13 . More specifically, the transistor M 11 is turned on when the voltage Va of the node N 12 is higher than the voltage Vb of the node N 11 by a voltage in which the voltage ΔVthp and the voltage ΔVde are added.

When the threshold voltage Vthp 1 of the transistor M 11 is fairly close to the threshold voltage Vthp 2 of the transistor M 12 , it is feared that a leakage current flows through the transistor M 11 . Therefore, when a voltage inputted to the gate of the transistor M 11 is raised by the attenuator 22 , the leakage current can be suppressed and the rectification efficiency can be enhanced.

Operations in FIG. 9 are described by using specific values. Assume that the threshold voltage Vthp 1 of the transistor M 11 and the threshold voltage Vthp 2 of the transistor M 12 are 1.1 volts and 1.0 volt, respectively. The attenuator 22 attenuates the voltage at the gate of the transistor M 11 by a voltage of 0.1 volt and outputs the resulting voltage to the node N 13 . Also, assume that the voltage Vb is 2 volts. Accordingly, the voltage of the node N 13 is determined to be 1.0 volt by the transistor M 12 . To the gate of the transistor M 11 , a voltage of 1.1 volts is inputted by means of the attenuator 22 .

When the voltage Va of the node N 12 is equal to or more than 2.2 volts, a positive charge flows from the node N 12 to the node N 11 . Therefore, the node N 12 serves as the source. Since a voltage of 1.1 volts is inputted to the gate of the transistor M 11 , a potential difference between the node N 12 and the gate of the transistor M 11 is equal to or more than 1.1 volts. As a result, the transistor M 11 is turned on and a current is allowed to flow from the node N 12 to the node N 11 .

On the other hand, when the voltage Va is from 2.2 to 2 volts, the potential difference between the node N 12 and the gate of the transistor M 11 is lower than the threshold voltage Vthp 1 of 1.1 volts. Therefore, the transistor M 11 is turned off. Further, when the voltage Va is lower than 2 volts, the positive charge flows from the node N 11 to the node N 12 . Therefore, the node N 11 serves as the source. With respect to a voltage at the node 11 of 2 volts, a voltage of 1.1 volts is inputted to the gate of the transistor M 11 by the transistor M 12 and the attenuator 22 . Therefore, the transistor M 11 is in an off-state.

As described above, in the case of using no attenuator 22 , the transistor M 12 is turned on when the voltage of the node N 12 is higher than that of the node N 11 by a voltage of 0.1 volt or more. On the other hand, in the case of using the attenuator 22 of FIG. 9 , the transistor M 12 is turned on when the voltage of the node N 12 is higher than that of the node N 11 by a voltage of 0.2 volt or more by means of the attenuator 22 . More specifically, when the attenuator 22 raises a voltage inputted to the gate of the transistor M 11 , a threshold voltage that turns on the transistor M 11 can be increased.

When using the attenuator 22 , the transistors M 11 and M 12 can be formed into one semiconductor integrated circuit so as to have the same threshold voltage. This is because that the attenuator 22 can determine the threshold voltage that turns on the transistor M 11 . This leads to facilitation of the design and the manufacture.

The attenuator 22 is described in detail.

FIG. 10 is a detailed circuit diagram of an attenuator of FIG. 9 . In the diagram, the same elements as those in FIG. 9 are indicated by the same reference numerals as in FIG. 9 and their descriptions are omitted. As shown in the diagram, a resistor R 12 is connected between the node N 13 and the gate of the transistor M 11 . Further, a resistor R 13 is connected between the gate of the transistor M 11 and the node N 11 . The resistors R 12 and R 13 correspond to the attenuator 22 of FIG. 9 .

A current scarcely flows through the gate of the transistor M 11 . Therefore, the voltage at the gate of the transistor M 11 is determined by a resistance ratio between the resistors R 12 and R 13 . For example, in an example of the numerical values described above, the voltage of the node N 13 is 1.0 volt and the voltage of the node N 11 is 2 volts. Accordingly, the resistance values of the resistors R 12 and R 13 may be determined such that the voltage at the gate of the transistor M 11 becomes 1.1 volts.

By thus dividing the voltage between the node N 11 and the node N 13 by the resistors R 12 and R 13 , the attenuator 22 can be readily configured. Therefore, the rectifier circuit is readily designed and manufactured.

A relationship among the voltage Va inputted, the rectified voltage Vb and the resistors R 12 and R 13 is described below.

FIG. 11 is a diagram showing rectification results. The diagram shows a waveform A 1 of the voltage Va inputted between the nodes N 12 and N 14 of FIG. 10 . Further, the diagram also shows waveforms B 1 to B 3 of the voltage Vb outputted from between the nodes N 11 and N 14 . The waveform B 1 shows one formed when a resistance ratio between the resistors R 12 and R 13 is 1:9. The waveform B 2 shows one formed when a resistance ratio between the resistors R 12 and R 13 is 5:5. The waveform B 3 shows one formed when a resistance ratio between the resistors R 12 and R 13 is 10:0.

As shown in the waveforms B 1 to B 3 , as a resistance ratio of the resistor 12 to the resistor 13 is smaller, the voltage value of the voltage Vb is more increased. More specifically, as a voltage inputted to the gate of the transistor M 11 is closer to the threshold voltage Vthp 1 , the threshold voltage that turns on the transistor M 11 is more reduced. As a result, the conduction loss is reduced, and the voltage Vb is increased.

When the rectifier circuit is applied to an IC card or an ID tag, the voltage Va inputted is extremely reduced depending on the distance between the card or the tag and the reader/writer that supplies power. In this case, in the rectifier circuits shown in FIGS. 9 and 10 , the threshold voltage that turns on the transistor M 11 is increased by the attenuator 22 and therefore, the voltage Va cannot be rectified in some cases. Accordingly, when the voltage Va inputted is small, the attenuator 22 is inactivated to allow the voltage of the node N 13 to be directly inputted to the gate of the transistor M 11 .

FIG. 12 is a diagram of a circuit for controlling an attenuator. In the diagram, the same elements as those in FIG. 10 are indicated by the same reference numerals as in FIG. 10 and their descriptions are omitted. As shown in the diagram, a PMOS transistor M 13 is connected between the node N 11 and the resistor R 13 . The gate of the transistor M 13 is connected to the node N 14 .

A voltage proportional to the voltage Va is inputted to the node N 14 . When the voltage Va is reduced to a voltage that turns off the transistor M 11 , the transistor M 13 is turned off to thereby cut off the connection between the resistor R 13 and the node N 11 . More specifically, when the voltage Va is reduced to a voltage that turns off the transistor M 1 , the threshold voltage Vthp 2 of the diode-connected transistor M 12 is inputted to the gate of the transistor M 11 without the attenuation. As a result, the threshold voltage that turns on the transistor M 11 is reduced. Thus, the voltage Va inputted can be rectified even if it is reduced. In addition, a communicable range of IC cards or ID tags can be widened.

Rectifiers to which the rectifier circuits shown in FIGS. 1 to 5 , 7 to 10 and 12 are applied are described below.

FIG. 13 is a circuit diagram of a half-wave double voltage rectifier to which the rectifier circuits according to the first and second embodiments of the present invention are applied. As shown in the diagram, rectifier circuits 31 and 32 are connected in series. A capacitor C 21 is connected between an input terminal (a) and a connection point of the rectifier circuits 31 and 32 . An input terminal (b) and an output terminal (d) are common, and a capacitor C 22 is connected between the output terminals (c) and (d).

The rectifier circuit 31 is one according to the first embodiment of the present invention, shown in FIGS. 1 to 5 . The rectifier circuit 32 is one according to the second embodiment of the present invention, shown in FIGS. 7 to 10 and 12 . The rectifier circuit 31 allows a current to flow when the voltage of the input terminal (a) is lower than that of the input terminal (b), and thereby charging the capacitor C 21 . The rectifier circuit 32 allows a current to flow when the voltage of the input terminal (a) is higher than that of the output terminal (c), and thereby charging the capacitor C 22 with a voltage charged in the capacitor C 21 . As a result, a voltage which is twice as much as that between the input terminals (a) and (b) is outputted between the output terminals (c) and (d).

As described above, when the rectifier circuits according to the first and second embodiments of the present invention are applied to the half-wave double voltage rectifier, the conduction loss due to the threshold voltage can be reduced. Further, even if a small voltage is inputted, the voltage can be rectified.

FIG. 14 is a circuit diagram of a half-wave quadruple voltage rectifier to which the rectifier circuits according to the first and second embodiments of the present invention are applied. As shown in the diagram, rectifier circuits 41 and 42 are connected in series. A capacitor C 31 is connected between an input terminal (a) and a connection point of the rectifier circuits 41 and 42 . An input terminal (b) and an output terminal (d) are common, and a capacitor C 33 is connected in parallel between the rectifier circuits 41 and 42 .

Rectifier circuits 43 and 44 are connected in series to the rectifier circuit 42 . A capacitor C 32 is connected between the capacitor C 31 and the connection point of the rectifier circuits 43 and 44 . A capacitor C 34 that is connected in series to a capacitor C 33 is connected in parallel between the rectifier circuits 43 and 44 .

A rectifier of FIG. 14 configured by the rectifier circuits 41 and 42 and the capacitors C 31 and C 33 corresponds to the rectifier of FIG. 13 . A rectifier of FIG. 14 configured by the rectifier circuits 43 and 44 and the capacitors C 32 and C 34 corresponds to the rectifier of FIG. 13 . In FIG. 14 , a negative pole-side output of the rectifier configured by the rectifier circuits 43 and 44 and the capacitors C 32 and C 34 is connected in series to a positive pole-side output of the rectifier configured by the rectifier circuits 41 and 42 and the capacitors C 31 and C 33 . Therefore, a voltage which is four times as much as that between the input terminals (a) and (b) is outputted between the output terminals (c) and (d).

As described above, when the rectifier circuits according to the first and second embodiments of the present invention are applied to the half-wave quadruple voltage rectifier, the conduction loss due to the threshold voltage can be reduced. Further, even if a small voltage is inputted, the voltage can be rectified.

FIG. 15 is a circuit diagram of a bipolar rectifier to which the rectifier circuits according to the first and second embodiments of the present invention are applied. As shown in the diagram, rectifier circuits 51 and 52 are connected in series. A capacitor C 41 is connected between an input terminal (a) and a connection point of the rectifier circuits 51 and 52 . An input terminal (b) and an output terminal (d) are common, and a capacitor C 43 is connected in parallel between the output terminals (c) and (d).

Rectifier circuits 53 and 54 are connected in series to the rectifier circuit 51 . A capacitor C 42 is connected between the input terminal (a) and the connection point of the rectifier circuits 53 and 54 . A capacitor C 44 is connected in parallel between the output terminals (d) and (e).

A rectifier of FIG. 15 configured by the rectifier circuits 51 and 52 and the capacitors C 41 and C 43 corresponds to the rectifier of FIG. 13 . A rectifier of FIG. 15 configured by the rectifier circuits 53 and 54 and the capacitors C 42 and C 44 corresponds to the rectifier of FIG. 13 . In FIG. 15 , a negative pole-side output of the rectifier configured by the rectifier circuits 53 and 54 and the capacitors C 42 and C 44 is connected in series to a negative pole-side output of the rectifier configured by the rectifier circuits 51 and 52 and the capacitors C 41 and C 43 . Therefore, a positive voltage which is twice as much as that between the input terminals (a) and (b) is outputted to the output terminal (c). Further, a negative voltage which is twice as much as that between the input terminals (a) and (b) is outputted to the output terminal (e).

As described above, when the rectifier circuits according to the first and second embodiments of the present invention are applied to the bipolar rectifier, the conduction loss due to the threshold voltage can be reduced. Further, even if a small voltage is inputted, the voltage can be rectified.

In FIGS. 13 and 14 , the half-wave double voltage rectifier and the half-wave quadruple voltage rectifier are described. Of course, the rectifier circuits according to the first and second embodiments of the present invention can be applied to a half-wave n-times voltage (n is a positive integer) rectifier.

In FIG. 15 , the bipolar rectifier configured by combining two rectifier circuits is described. Of course, a rectifier with a multiple output structure can also be configured by combining three or more rectifier circuits. For example, a new rectifier may be connected in series to the rectifier configured by the rectifier circuits 51 and 52 and the capacitors C 41 and C 43 , as shown in FIG. 14 .

An IC card to which the rectifiers shown in FIGS. 13 to 15 are applied is described.

FIG. 16 is a block diagram of the IC card. As shown in the diagram, the IC card has an antenna 61 , modulator 62 , rectifier 63 , shunt regulator 64 , demodulator 65 and digital signal processor 66 .

The antenna 61 transmits and receives data to and from a reader/writer. The modulator 62 modulates the data processed by the digital signal processor 66 , and transmits the data to the reader/writer through the antenna 61 . The rectifiers of FIGS. 13 to 15 are applied to the rectifier 63 . The rectifier 63 takes out high-frequency power from high-frequency energy fed by the reader/writer. The rectifier transforms the power into a DC power supply (DC voltage) and outputs the power supply to the modulator 62 , the shunt regulator 64 , the demodulator 65 and the digital signal processor 66 . The shunt regulator 64 controls the power supply voltage to be constant. The digital signal processor 66 transmits and receives the data to and from the reader/writer and performs a predetermined digital processing on the data.

The power (voltage) received by the antenna 61 varies depending on a distance between the antenna and the reader/writer. Even if the distance between the IC card and the reader/writer is far and the voltage taken out from the antenna 61 is small, the voltage can be sufficiently rectified because the threshold voltage in the rectifier circuit of the rectifier 63 is small. Thus, when the high-frequency power is taken out from the high-frequency energy and transformed into the DC power supply, conversion efficiency of the electric power can be improved.

In the above instance, a case is described where the rectifiers shown in FIGS. 13 to 15 are applied to the IC card. The rectifiers can be applied also to a device having no its own power supply such as an ID tag.

In the first and second embodiments, the transistors M 1 , M 2 , M 11 and M 12 are configured using the MOS transistor (MOS-FET). However, these transistors can also be configured using a MES (Metal semiconductor)-FET, a MIS (Metal Insulator Silicon)-FET and a bipolar transistor.

In the rectifier circuit of the present invention, the threshold voltage of the current that starts flowing between the source and drain of the transistor is reduced not by a process step but by the voltage near the threshold voltage outputted to the gate of the transistor. As a result, the cost and the variation in devices can be reduced.

The foregoing is considered as illustrative only of the principles of the present invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and applications shown and described, and accordingly, all suitable modifications and equivalents may be regarded as falling within the scope of the invention in the appended claims and their equivalents.