Overvoltage tolerant input buffer

The present invention relates to a CMOS input buffer protection circuit and, more particularly, to a CMOS input buffer protection circuit formed in low voltage CMOS technology (e.g., 3.3 V) that is tolerant to high input voltages (e.g., 5 V).

As a result of the many technologies and processes available to manufacture integrated circuits, a variety of circuits capable of operating in a variety of conditions, such as supply voltages, input/output voltages etc., became possible and with the adoption of several integrated circuit voltage standards, incompatibility became an issue. For example, circuits that operate at the earlier 5 V power supply standard may be incompatible with those operating under the newer standard of 3.3 V. Overvoltage is the condition where a voltage greater than which a technology was designed to support, for example, when a higher 5 V signal is applied to a circuit designed with lower 3.3 V. The problem of overvoltage is described in U.S. Pat. No. 6,064,231 to Kothandaraman et al., which is incorporated by reference in its entirety as if fully set forth herein. Numerous solutions have been proposed to solve the overvoltage problem but a need to improve the art remains.

We have discovered that when a P-channel pass gate transistor is added in parallel to an N-channel pass gate, the resulting circuit improves overvoltage tolerance of an input buffer. In this configuration, signal to the input buffer would be rail-to-rail, ensuring that the P-channel pass gate in a first stage is fully turned OFF in a high state. A simple bias circuit including two small transistors controls a gate of this P-channel pass gate transistor in such a way that it is turned OFF when an overvoltage is applied, but turned ON when a normal voltage is applied.

These and other objects, features and advantages of the present invention are more readily understood from the following detailed description in conjunction with the accompanying drawings, where like numbers represent like parts and wherein,

FIG. 1 shows a non-overvoltage tolerant input buffer;

FIG. 2 shows an overvoltage tolerant input buffer with an N-channel transistor added as a pass gate between input PAD and buffer;

FIG. 3 shows a P-channel feedback transistor added to an N-channel pass gate transistor of FIG. 2 ;

FIG. 4 shows an embodiment in which a P-channel pass gate is added in parallel to an N-channel pass gate; and

FIG. 5 shows a simple circuit generating “vback” voltage; and

FIG. 6 shows another embodiment of a circuit in which a leakage path is provided to a pass gate.

In the description below, with reference to the drawings, MX represents a transistor where X is a number, and “ON” and “OFF” denote two states of a transistor. Drain voltage (V DD ) represents supply voltage, and source voltage (V SS ) represents the ground. Threshold voltages of transistors are represented as Vtn for N-channel transistor and Vtp for a P-channel transistor. Note that the instant discussion uses transistors fabricated using the CMOS technology, but the invention applies to other technologies as well.

FIG. 1 shows a circuit without overvoltage tolerance. A typical CMOS buffer has two inverters—one comprising transistors M 1 and M 2 , and another comprising transistors M 3 and M 4 —connected in series as shown. Note that M 1 and M 3 are P-channel transistors whereas M 2 and M 4 are N-channel transistors. PAD denotes an input to buffer. When PAD is high, node N 1 , the output of the first inverter and the input of the second inverter, is low and output Z of the buffer is high. When overvoltage is applied at input PAD of the buffer, overvoltage stresses gate oxide of transistor M 2 , thereby degrading the buffer's reliability.

FIG. 2 shows an overvoltage tolerant buffer, where an N-channel transistor M 5 is added as a pass gate between input PAD and buffer. This transistor M 5 , whose gate is connected to power supply V DD , acts as a source-follower voltage clamp, and prevents voltage at node N 2 from exceeding V DD −Vtn, where Vtn is the threshold voltage of an N-channel transistor, the typical value of which is 0.6V. For instance, if 5V is applied to PAD, and V DD is 3.3V, then node N 1 will have a voltage 3.3V-Vtn, or about 2.7V. This circuit works reliably because the placement of the transistor M 5 ensures that no single transistor in the circuit has more than 3.3V across its gate or source-to-drain terminals.

But this circuit poses a problem. In a “high” state, i.e., when PAD is 3.3V, node N 2 is still clamped at V DD −Vtn. Thus, P-channel transistor M 1 will have a gate bias of V DD −Vtn. If Vtp (that is, threshold voltage of a P-channel transistor) is less than Vtn, which is possible because of process variations, transistor M 1 will not be fully turned OFF, and DC power will flow from V DD to V SS through transistors M 1 and M 2 , thereby consuming direct current (DC) power in a “high” state. Thus, undesired power consumption occurs because a P-channel in a first stage of buffer is not fully turned OFF.

FIG. 3 shows a solution to this problem where a P-channel feedback transistor M 6 is added to N-channel pass gate transistor M 5 of FIG. 2 . By coupling gate of transistor M 6 to output of inverter formed by transistors M 1 and M 2 , feedback effect is achieved. Transistor M 6 ensures that a first stage P-channel transistor is completely turned OFF. This works as follows.

Feedback transistor M 6 acts to pull node N 2 all the way up to V DD when input PAD is “high.” Note that M 6 may be a small, weak transistor. In a “high” state, node N 1 is “low,” which turns ON transistor M 6 and pulls node N 2 up to V DD . In a “low” state, input PAD is “low,” node N 2 is “low,” and node N 1 is “high.” A drawback of this configuration is that during state transitions feedback transistor M 6 causes a leakage DC current from input PAD-via transistors M 5 and M 6 —to power supply V DD . This DC leakage current is typically several tens of microamperes, which is more than permitted leakage in some specifications. Additionally, transistor M 6 requires a large gate length to operate properly, which can take up a large amount of area.

FIG. 4 shows a circuit that allows node N 2 to go all the way up to V DD . Three transistors M 7 , M 8 and M 9 are added to the circuit of FIG. 2 . M 7 is a P-channel pass gate transistor, M 8 is an N-channel transistor and M 9 is a P-channel transistor. M 7 is placed in parallel with N-channel pass gate M 5 . When M 7 is ON, it permits the voltage at PAD to go all the way up to V DD . Transistors M 8 and M 9 are connected in parallel as pass gates from PAD to node N 3 , which is gate of transistor M 7 , thereby providing a bias voltage at gate of transistor M 7 . Gates of both M 8 and M 9 are connected to V DD . In normal operation, when PAD voltage does not exceed V DD , transistor M 9 is always OFF. When PAD voltage is “high,” that is, it goes to V DD , transistor M 8 acts as a source follower and sets node N 3 equal to V DD −Vtn. This turns transistor M 7 ON, albeit rather weakly, which in turn permits N 2 to go all the way up to V DD , thereby completely turning OFF transistor M 1 .

During an overvoltage event, for instance when 5V is applied to PAD and V DD =3.3V, transistor M 9 will turn ON. This allows the voltage on PAD to pass through to node N 3 . This voltage turns OFF transistor M 7 , and the circuit performs identically to the circuit of FIG. 2 .

Note that P-channel transistors shown in FIGS. 1–3 have their back gates tied to a common node, V DD . But if the node to which gates of P-channel devices are connected to a node such as PAD at which voltage can exceed V DD , as is possible in an overvoltage condition, a parasitic diode inherent in the transistor structure turns ON. This means that devices M 7 and M 9 in FIG. 4 must have their back gates connected to some other voltage, which is typically called the “vback” voltage.

FIG. 5 shows a “vback” voltage generating circuit, where two P-channel transistors M 10 and M 11 are connected in series between PAD and V DD . Their common node, which is also connected to their back gates, is “vback.” Their gates are cross-coupled. When PAD voltage is less than V DD , transistor M 11 is ON and transistor M 10 is OFF. This connects vback to V DD . When PAD voltage is greater than V DD , such as when PAD=5V and V DD =3.3V, M 1 is OFF and M 10 is ON. In this case, vback is connected to PAD. Therefore vback is always equal to the greater of V DD or PAD voltage. This circuit may be used to bias back-gates of P-channel transistors in an output stage of overvoltage tolerant buffer of FIG. 4 .

FIG. 6 shows another overvoltage protection buffer circuit. Note that FIG. 4 is an independent solution to the overvoltage problem. FIG. 6 has two N-channel devices M 12 and M 13 coupled in series with each other. N-channel device M 12 has a gate connected to power supply voltage V DD , its drain to node N 3 , and its source to the drain of M 13 . N-channel device M 13 is “turned off”, i.e., its input is at or near ground V SS .

M 12 protects M 13 from overvoltage as follows. As seen above, in connection with FIG. 4 , node N 3 will go to V DD −Vtn when voltage at PAD exceeds V DD . If M 13 were directly connected to N 3 , voltage across its gate would be too “high” to tolerate. The purpose of the “turned-off” N-channel device M 13 is to act as a small leakage path from N 3 to ground. Because all MOS devices leak to some extent—i.e., even when they are turned “off”—M 13 provides a very high resistance path from N 3 to ground. This non-zero resistance helps maintain N 3 at a voltage of V DD −Vtn, since small current through M 8 helps to set its gate-to-source voltage at Vtn. Other leakage paths from N 3 to ground may also help maintain this voltage V DD −Vtn at N 3 . Adding M 12 and M 13 is a way to ensure that N 3 is maintained at desired voltage level V DD −Vtn.

The foregoing describes an overvoltage tolerant buffer, which may be used in integrated circuits in general, and CMOS circuits in particular. Persons of ordinary skill in the art may make variations and modifications to the structure and operation of the disclosed apparatus without departing from the scope or spirit of the description herein or without undue experimentation. For example, the states described as OFF and ON or “high” and “low” could be logical states. Alternatively, OFF means that the circuit is turned off in the ordinary sense of the word, that is, no electric conduction takes place, and ON may mean an opposite condition to OFF. Similarly, in an alternative embodiment, “high” may mean that a higher voltage, for example, 5V, and “low” may mean that a lower voltage, e.g., the ground, or some other power supply voltage such as 3.3V is applied at a designated point. Likewise, devices M 5 , M 8 and M 9 have their gates connected to the power supply voltage V DD . In alternative embodiments, these devices may be connected to the power supply V DD via a resistor, which makes the circuit more robust, that is, tolerant to damage caused by electrostatic discharge (ESD). All such and similar modifications, departures and variations fall within the scope of the appended claims.