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Inventor

Dipankar Bhattacharya

Inventor
Macungie, PA, US

Overview

45→
Patents
1994–2013
Patent span
Electricity
Primary field (CPC H)

Patents· 45 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary
H03KPulse technique34%
G06FElectric digital data processing19%
H04LTransmission of digital information, e.g. telegraphic communication14%
H10DInorganic electric semiconductor devices10%
G05FSystems for regulating electric or magnetic variables5%
H03FAmplifiers3%
E06BFixed or movable closures for openings in buildings, vehicles, fences or like enclosures in general, e.g. doors, windows, blinds, gates2%
G01RMeasuring electric variables2%
G11CStatic stores2%
H01CResistors2%
PatentTitleYear
8,598,941'Hybrid impedance compensation in a buffer circuit'20138,536,925'Voltage level translator circuit'20138,362,803'Mode latching buffer circuit'20138,159,262'Impedance compensation in a buffer circuit'20128,089,739'Electrostatic discharge protection circuit'20127,936,209'I/O buffer with low voltage semiconductor devices'20117,902,904'Bias circuit scheme for improved reliability in high voltage supply with low voltage device'20117,720,107'Aligning data in a wide, high-speed, source synchronous parallel link'20107,642,807'Multiple-mode compensated buffer circuit'20107,551,020'Enhanced output impedance compensation'20097,529,071'Circuit for selectively bypassing a capacitive element'20097,529,070'Power pin to power pin electro-static discharge (ESD) clamp'20097,511,550'Method and apparatus for improving reliability of an integrated circuit having multiple power domains'20097,498,860'Buffer circuit having multiplexed voltage level translation'20097,495,873'Electrostatic discharge protection in a semiconductor device'20097,432,762'Circuit having enhanced input signal range'20087,430,100'Buffer circuit with enhanced overvoltage protection'20087,397,279'Voltage level translator circuit with wide supply voltage range'20087,391,825'Comparator circuit having reduced pulse width distortion'20087,382,168'Buffer circuit with multiple voltage range'20087,369,489'Unbiased token bucket'20087,350,020'Generating and merging lookup results to apply multiple features'20087,276,957'Floating well circuit having enhanced latch-up performance'20077,248,079'Differential buffer circuit with reduced output common mode variation'20077,218,169'Reference compensation circuit'20077,196,561'Programmable reset signal that is independent of supply voltage ramp rate'20077,177,978'Generating and merging lookup results to apply multiple features'20077,145,364'Self-bypassing voltage level translator circuit'20067,139,928'Method and system for providing redundancy within a network element'20067,106,107'Reliability comparator with hysteresis'20067,098,694'Overvoltage tolerant input buffer'20067,068,074'Voltage level translator circuit'20067,057,545'Semiconductor resistance compensation with enhanced efficiency'20067,047,385'High-speed memory for use in networking systems'20067,034,653'Semiconductor resistor'20066,992,489'Multiple voltage level detection circuit'20066,826,150'Distriburted QoS policing system and method'20046,774,698'Voltage translator circuit for a mixed voltage circuit'20045,918,072'System for controlling variable length PCI burst data using a dummy final data phase and adjusting the burst length during transaction'19995,805,905'Method and apparatus for arbitrating requests at two or more levels of priority using a single request line'19985,577,214'Programmable hold delay'19965,469,555'Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system'19955,463,759'Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system'19955,448,742'Method and apparatus for local memory and system bus refreshing with single-port memory controller and rotating arbitration priority'19955,371,880'Bus synchronization apparatus and method'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–1999Patents assigned to OPTI INC (7)· patent assignee history
1994–1999Based in Santa Clara, CA, US· patent location history
2004–2012Patents assigned to AGERE SYSTEMS INC (25)· patent assignee history
2004–2013Based in Macungie, PA, US· patent location history
2004–2010Based in Saratoga, CA, US· patent location history
2006–2010Patents assigned to CISCO TECH INC (6)· patent assignee history
2011Based in Maoungie, PA, US· patent location history
2012–2013Patents assigned to BHATTACHARYA DIPANKAR (5)· patent assignee history
2012–2013Patents assigned to KOTHANDARAMAN MAKESHWAR (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
AGERE SYSTEMS INC252004–2012
OPTI INC71994–1999
CISCO TECH INC62006–2010
BHATTACHARYA DIPANKARself52012–2013
KOTHANDARAMAN MAKESHWAR42012–2013
Locations
LocationPatentsSpan
Macungie, Pennsylvania, US302004–2013
Saratoga, California, US72004–2010
Santa Clara, California, US71994–1999
Maoungie, Pennsylvania, US12011