Method for temperature control in a rapid thermal processing system

This invention relates, in general, to processes involved in the manufacture of semiconductor devices. More particularly, the present invention relates to methods and apparatus for performing rapid thermal processing (RTP).

The processing of silicon wafers to produce integrated circuits generally includes one or more stages of wafer heating. One approach for wafer heating is Rapid Thermal Processing (RTP), which is presently used for a variety of applications including silicidation, oxide formation, and anneal processes. A typical RTP system includes a heating chamber in which a wafer is positioned for thermal processing. High-intensity heating lamps are controlled for generating radiant heat for heating the wafer, and temperature sensing equipment is provided for sensing the temperature in the chamber and/or for feedback-control of the heating lamps. The wafer is rapidly heated and cooled (e.g., 50° to 250° C./sec), usually maintaining a peak temperature (e.g., 150° to 1200° C.) for a short period of time (e.g., 10 to 120 sec) according to a prescribed RTP recipe.

An important factor in the thermal processing of wafers is maintaining temperature uniformity within the wafer. A temperature difference across a wafer can cause Vt variations within the wafer and/or stress that leads to device damage, resulting in decreased product yield. For this reason, temperature uniformity during RTP is a subject of considerable interest, and Temperature uniformity during RTP is often inferred from the sheet-resistance uniformity of the wafer post-processing. Sheet resistance varies according to the temperature to which the wafer is heated, so variations in sheet resistance can serve as an accurate indicator of variations in temperature that occurred during RTP.

One of the ways of monitoring the annealing temperature within the heating chamber is to calibrate the heating chamber with a thermal coupled standard consisting of temperature sensors that display the exact temperature depending on the location of these sensors while the thermal coupled standard is seated inside the heating chamber. However, thermal coupled standard monitor and calibration cannot be performed while wafers are being processed inline, and often requires the RTP system be taken offline in order to perform the calibrations which can be costly as well as time consuming.

A more time and cost efficient method of monitoring the annealing temperature uniformity within the heating chamber is to use the Rs-49 point contour map. The Rs-49 point contour map method assesses wafer heating uniformity by measuring the sheet resistance (Rs) of 49 uniformly distributed points across the semiconductor substrate after the semiconductor substrate has been annealed inside the heating chamber. The measurements can be done on batches of processed wafers and provide a quick and accurate assessment of the annealing temperature uniformity by plotting a contour map of the Rs values based on their position on the semiconductor substrate. The measurements can then be used to calibrate or fine-tune the RTP system for improving heating uniformity. However, while the Rs-49 point contour map method is an efficient method to monitor and fine tune RTP systems, there remains considerable room for improvement. Thus, there exists a need for improved techniques for calibrating or fine-tuning RTP systems in order to provide for more ideal heating uniformity during RTP processes.

For RTP systems that utilize a multi-zone tungsten-halogen lamp module, it has been recognized that strong temperature coupling effects exist among the internal temperature probes located within the RTP system itself. Conventional methods of calibrating RTP systems, including those based on the Rs-49 point contour map, do not account for this coupling effect, resulting in less-than-ideal system tuning. Accordingly, an improved calibration/tuning method and system is disclosed herein that accounts for zone coupling. This method is also referred to as a multi-zone interference correction process. Generally, the multi-zone interference correction process includes steps of establishing baseline characteristic data and zone characteristic data, and then using the baseline and zone characteristic data to determine lamp-control parameters for temperature probes of the RTP system. The baseline characteristic data includes information regarding baseline heating uniformity of an RTP system. The zone characteristic data is collected for a plurality of heating zones within the heating chamber of the RTP system, each zone being associated with a respective temperature probe. The zone characteristic data is collected based on controlled temperature sensor variations. The lamp-control parameters for temperature probes of the RTP system are then calculated based on the baseline characteristic data and the zone characteristic data.

Embodiments are illustrated by way of example in the accompanying figures, in which like reference numbers indicate similar parts, and in which:

FIG. 1 shows a schematic block diagram of a Rapid Thermal Processing (RTP) system;

FIG. 2 shows a plot diagram illustrating measurement points used for an Rs-49 calibration method;

FIG. 3 shows an example of a 49-point contour map created during an Rs-49 calibration method;

FIG. 4 shows a flowchart of steps in a multi-zone interference correction process;

FIG. 5 shows a flowchart of steps in a process of establishing baseline characteristic data;

FIG. 6 shows a flowchart of steps in a process of generating baseline characteristic data;

FIG. 7 shows a plan view of a wafer, illustrating measurement points used for the process of FIG. 6 ;

FIG. 8 shows a system for performing steps of the process shown in FIG. 4 ;

FIG. 9 shows a flowchart of steps in a process of generating zone characteristic data;

FIG. 10 shows a flowchart of steps in a process of generating lamp-control parameters; and

FIGS. 11A-11F show graphs of the normalized offset arrays generated during the process of FIG. 10 .

FIG. 1 shows a schematic block diagram of a Rapid Thermal Processing (RTP) system 10 . The RTP system 10 includes lamp module 12 , provided with an array of multiple halogen, silicon carbide, or arc lamps 14 . A wafer edge ring 16 is supported by a support cylinder 18 and is adapted for supporting the edges of a semiconductor wafer 20 . An upward-facing, circular reflector plate 22 , circumscribed by the support cylinder 18 , is provided for reflecting infrared heat radiation from the lamps 14 . It will be apparent to those skilled in the art that the concepts disclosed herein are equally applicable to other semiconductor fabrication equipment and single-wafer processing configurations.

A plurality of temperature probes 24 (e.g., fiber optic probes connected to pyrometers) extend through the reflector plate 22 for temperature monitoring of respective zones. The RTP system 10 includes six temperature probes 24 used for temperature control. The temperature-control probes 24 are designated individually from the wafer center towards the wafer edge as probes T 1 -T 6 . It will be appreciated by those skilled in the art that the RTP system can also include additional temperature probes (not shown) used for purposes other than feedback temperature control. The temperature probes 24 provide temperature data to a control system 26 for feedback control of the lamps 14 , particularly those having like designations T 1 -T 6 . During a rapid thermal process, such as annealing or oxidation, the semiconductor wafer 20 is rapidly heated to a prescribed temperature by operation of the lamps 14 , according to a preset processing recipe programmed into the control system 26 . Infrared or heat radiation beams from the lamps 14 penetrate the semiconductor wafer 20 and strike the reflector plate 22 , with the frequency or energy level of the beams striking the reflector plate 22 depending upon the emissivity of the wafer 20 . The emissivity, or measure of the relative quantities of energy absorbed and reflected by the wafer 20 , is highly material- and position-dependent, as various areas of the wafer 20 may include various oxides, polysilicon or other components. After initially striking the reflector plate 22 , the energy beams are reflected back toward the backside of the wafer 20 , and strike the backside of the wafer 20 and are reflected back toward the reflector plate 22 . Eventually, the energy beams strike and are absorbed by one of the temperature probes 24 , which can measure the temperature of the heat radiating from the wafer 20 and provide continuous data input to the control system 26 for precise temperature control of the wafer 20 .

In order to prevent damage to the wafer 20 , the wafer 20 should be heated very uniformly across its entire surface. Using data received from the temperature probes 24 , the control system 26 can perform feedback control of the lamps 14 in order to uniformly to heat the wafer 20 . However, the temperature probes 24 do not give an exact image of the temperature of the wafer 20 . Rather, they are brought to temperatures that are different from those of the wafer 20 . These temperatures therefore may be used only as information for correcting and regulating the temperature of the wafer 20 . The control system 26 processes the data received from the temperature probes 24 for control of the lamps 14 according to preset operating parameters programmed into the control system during manufacturing or periodic system calibration. Periodic calibration of the RTP system 10 allows for adjustments in the processing of the control system 26 to account for such things as variations in the temperature probes 24 or lamps 14 .

Since the temperature variations across the wafer 20 are not directly measured during thermal processing, characteristics of the wafer 20 that vary with temperature can instead be measured and used to deduce the temperature variation measurements. One such characteristic is sheet resistance. There are known relationships between the sheet resistance of a semiconductor wafer and the maximum temperature to which it has been subjected. Thus, one method of calibrating the RTP system 10 involves measuring the sheet resistance of the wafer 20 at numerous points (e.g., 49 points on a 200 mm wafer) dispersed somewhat equally across a surface of the wafer 20 after thermal processing is complete (Rs-49 calibration method). The sheet resistance of the wafer 20 is measured at 49 points according to a plot diagram, for example as shown in FIG. 2 , using a commercially-available tool, for example a four-point sheet-resistance measure tool such as the KLA Tencor Rs-75 resistivity measurement system. The measured sheet resistance at each of the designated points is used to create a 49-point contour map, for example as shown in FIG. 3 , for graphically illustrating the measurement results. In FIG. 3 , the “−” sign indicates a point where the sheet resistance is below a calculated mean sheet resistance value, the “+” sign indicates a point where the sheet resistance is above the calculated mean sheet resistance value, and the contour lines provide general indications of lines of common sheet resistance values. This way, the 49-point contour map provides a visual indication of the sheet-resistance variations, thereby conveying information related to how well the control system 26 is controlling the lamps 14 to maintain temperature uniformity across the wafer 20 . This information can then be used according to known methods to generate lamp-control parameter data for calibration of the control system 26 . The lamp-control parameter data preferably includes an offset value for each of the temperature probes 24 .

However, even when adjustments are made according to a calibration method such as the Rs-49 calibration method described above, wafer temperature uniformity falls short of desirable levels. One reason for this is that Rs-49 calibration method does not adequately account for zone coupling. For example, referring back to FIG. 1 , heat energy (represented by arrows between wafer 20 and reflector plate 22 ) travels between the wafer 20 and the reflector plate 22 until it is eventually detected by the temperature probe T 2 . However, some of that heat energy continues to be reflected between the reflector plate 22 and the wafer 20 , and is detected again by the neighboring temperature probe T 1 . Thus, the total heat energy detected by temperature probe T 1 includes heat energy traveling from neighboring zones, resulting in a form of interference referred to herein as zone coupling.

In order to account for zone coupling, a multi-zone interference correction process is disclosed herein that includes steps in the flowchart shown in FIG. 4 . Generally, the multi-zone interference correction process includes step S 1000 , where baseline characteristic data is established. The baseline characteristic data includes information regarding baseline heating uniformity of the RTP system 10 . Step S 1000 is discussed in greater detail below in connection with FIGS. 5-8 . At step S 2000 , zone characteristic data for a plurality of heating zones within the heating chamber of the RTP system is collected based on controlled temperature sensor variations. Step S 2000 is discussed in greater detail below in connection with FIGS. 6 , 8 , and 9 . Finally, at step S 3000 , lamp-control parameters for temperature probes of the RTP system are determined based on the baseline characteristic data and the zone characteristic data. Step S 3000 is discussed in greater detail below in connection with FIG. 10 .

FIG. 5 shows a flowchart of a process for establishing baseline characteristic data (step S 1000 ). This process includes an optional step S 1100 of establishing a baseline set of offset values for the temperature probes of the RTP system. The baseline offset values preferably include a numerical value for each of the temperature probes 24 (T 1 -T 6 ) that can be used to offset temperature measurements made by the temperature probes 24 in order to adjust for errors in the temperature measurements. The baseline offset values can be selected to be system default values, null values, or values obtained during a prior system calibration. The baseline offset values can also be obtained by performing a system calibration of some kind, including known RTP system calibration methods. For example, step S 1100 can include performing the Rs-49 calibration method described above.

Next, at step S 1200 , the baseline offset values are programmed into the control system 26 and a wafer 20 is processed in the RTP system 10 according to a prescribed recipe. The processed wafer 20 is then used in step S 1300 to generate baseline wafer characteristic data. The baseline characteristic data provides information indicating how uniformly a wafer is heated by the RTP system 10 using the baseline offset values.

FIG. 6 shows a flowchart illustrating a process included in step S 1300 . This process includes taking a series of sheet-resistance measurements along a line (“line scan”) that extends across a diameter of the wafer. At step S 1310 , a first line scan is made along a line L 1 shown in FIG. 7 . The line scan includes measuring sheet resistance at points P l through P n along line L 1 , where n is an odd integer. Note that points P l thru P (n−l)/2 are distributed along one side of the wafer 20 , point P (n+l)/2 is at the center of the wafer 20 , and points P (n+3)/2 thru P n are distributed along the other side of the wafer 20 . The points of measurement preferably are somewhat evenly distributed along line L 1 . For example, in a case where the wafer 20 has a diameter of 200 mm, resistivity measurements can be made at 121 points (i.e., n=121) positioned approximately every 1.6 mm. In alternate embodiments, measurements can be taken along line L 1 at points P l -P n where n is an even integer, and where points P l thru P n/2 are to the right of the center of the wafer 20 , and points P (n+2)/2 thru P n are on to the left of the center of the wafer 20 .

Referring now to FIG. 8 , a scanning device 30 (e.g., KLA Tencor Rs-75) is used for making the sheet-resistance measurements in step S 1310 . In step S 1320 of FIG. 6 , the scanning device 30 provides the resistivity values as line scan data to a memory device 32 . The memory device 32 stores an array of resistance values R 1 l -R 1 n of points P l -P n , respectively, along line L 1 .

In a preferred embodiment, additional scans are performed along lines L 2 -L 4 shown in FIG. 7 , where lines L 2 -L 4 are angularly displaced from line L 1 by angles of 45°, 90°, and 135°, respectively. Accordingly, at step S 1330 a determination is made as to whether another line remains to be scanned. After scanning of line L 1 , the process continues to step S 1340 (“Y” at step S 1330 ) in order to perform a line scan along line L 2 , then back to step S 1320 where line scan data is stored in the memory device 32 in an array of resistance values R 2 l -R 2 n associated with L 2 . The process will continue the loop of steps S 1340 , S 1320 , and S 1330 until each of lines L 1 -L 4 has been scanned and resistance values for each of the line scans has been stored. Preferably, lines L 2 -L 4 are identical to line L 1 with respect to the number and distribution of the measurement points P along each of the lines L 2 -L 4 (e.g., number n of points P along each of lines L 1 -L 4 =121; points occurring approximately every 1.6 mm).

Once line scan data has been generated and stored for each of the lines L 1 -L 4 , the process continues to step S 1350 (“N” at step S 1330 ). At step S 1350 , an array AVE_B of average baseline resistance values RA l -RA n is calculated by an averaging device 34 . Thus, the array AVE_B is an average of the arrays L 1 -L 4 :

[ RA l = ( R ⁢ ⁢ 1 l + R ⁢ ⁢ 2 l + R ⁢ ⁢ 3 l + R ⁢ ⁢ 4 l ) / 4 ⋮ RA n = ( R ⁢ ⁢ 1 n + R ⁢ ⁢ 2 n + R ⁢ ⁢ 3 n + R ⁢ ⁢ 4 n ) / 4 ]

The array AVE_B having thus been generated constitutes the baseline characteristic data for step S 1300 of FIG. 5 . Note that the arrays AVE_T 1 , AVE_T 2 , and AVE_T 3 shown in FIG. 8 will be discussed below.

The multi-zone interference correction process shown in FIG. 4 continues to step S 2000 , which is preferably performed according to the flowchart shown in FIG. 9 . In general, the process shown in FIG. 9 includes running a series of wafers 20 in the RTP system 10 , where one of the temperature probes 24 is offset (e.g., +3° C.) during each run, then comparing the effects of each run in order to refine the baseline offset values (established in step S 1100 of FIG. 5 ) for reduction of the zone-coupling effect.

Referring again to FIG. 1 , during a first cycle (i.e., steps S 2200 -S 2600 ) of the process of FIG. 9 the control system 26 offsets temperature measurements received from temperature probe T 1 by a predetermined amount, for example 3° C., causing the lamps associated with T 1 to heat to a temperature that is different than the lamps associated with T 2 -T 6 . For example, for an RTP processing recipe that requires heating to 925° C., the lamps T 1 will be actually heating to 928° C. while the remaining lamps heat to 925° C. Thus, the wafer 20 is intentionally heated unevenly due to the temperature offset introduced to data from temperature probe T 1 . This cycle is then repeated for each of the remaining temperature probes T 2 -T 6 . Characteristics of the unevenly-heated wafers 20 resulting from each of these cycles can then be measured and used to refine the baseline offset values (established in step S 1100 of FIG. 5 ) for reduction of the zone-coupling effect as described further below.

Referring back to FIG. 9 , steps for accomplishing this process will now be described in greater detail. At step S 2100 , a counter “j” is initialized to “j=1”. The counter j is used for tracking which of the temperature probes T 1 -T 6 is the temperature probe being offset during the current cycle.

At step S 2200 , for j=1 the control system 26 offsets for temperature probe T 1 according to a prescribed temperature offset, for example +3° C. Then, at step S 2300 a wafer 20 is processed according to a prescribed RTP processing recipe. As mentioned above, since the control of the lamps associated with probe T 1 are influenced by the temperature offset, the wafer 20 experiences uneven heating, particularly in the vicinity of the lamps T 1 .

Next, at step S 2400 the wafer 20 that has undergone the uneven heating in step S 2300 is used to generate wafer characteristic data. This step is preferably performed according to the process shown in FIG. 6 and discussed above, so description thereof is not repeated here for the sake of brevity. An array of average resistance values associated with the probe T 1 being offset is designated AVE_T 1 in FIG. 8 .

At step S 2500 , a determination is made as to whether another probe remains to be offset. If so, the process continues to step S 2600 where the counter j is incremented. The process then returns to step S 2200 . Thus, steps S 2200 through S 2500 are repeated for each of the probes T 2 -T 6 , and respective arrays AVE_T 2 through AVE_T 6 are generated at step S 2400 . These arrays of resistance values constitute the zone characteristic data referenced in step S 2000 of FIG. 4 .

Referring back to FIG. 4 , once the zone characteristic data has been generated, the process continues to step S 3000 for generating refined lamp-control parameters. In a preferred embodiment, step S 3000 includes the steps shown in the flowchart of FIG. 10 . This process can be performed by the parameter-processing device 36 shown in FIG. 8 . This process generally includes reducing the baseline and offset data arrays, normalizing the offset data arrays based on the baseline data array, and then using the normalized offset data to calculate (or adjust) lamp-control parameters used by the control system 26 to control the lamps 14 based on information from the temperature probes 24 .

The process shown in FIG. 10 begins at step S 3100 , which includes data reduction by folding the baseline resistance array AVE_B and each of the offset resistance arrays AVE_T 1 through AVE_T 6 . In a preferred embodiment, a folding function for folding each array of average resistances RA l thru RA n can be expressed as:

RF i =( RA i +RA n−i+l )/2

where i is an integer ranging from 1 to (n−l)/2, or one less than half the number n of elements in each of the resistance arrays. This function generates an array where the first array element RF 1 is an average of the first and last resistance values RA l and RA n , the second array element RF 2 is an average of the second and second to last resistance values RA 2 and RA n−l , and so on. This way, resistance values corresponding to equal distances from the wafer center (or equal radii) are averaged to produce a single value representative of each measurement position P between the wafer center and the wafer edge. This reduction is desirable given the generally symmetrical nature of the wafer 20 about the center thereof when processed in the RTP system 10 . The folding operation is performed on the baseline array AVE_B to generate a baseline folded array FAVE_B, and is performed on the offset arrays AVE_T 1 through AVE_T 6 to generate respective offset folded arrays FAVE_T 1 through FAVE_T 6 .

Next, at step S 3200 , the offset folded arrays FAVE_T 1 through FAVE_T 6 are normalized based on the baseline folded array FAVE_B to generate normalized offset arrays NAVE_T 1 , NAVE_T 2 , NAVE_T 3 , NAVE_T 4 , NAVE_T 6 , and NAVE_T 7 , where:

FIGS. 11A-11F show exemplary graphs of the normalized offset arrays NAVE_T 1 through NAVE_T 6 , respectively, where the abscissa represents the distance (mm) from the center of the wafer 20 , and the ordinate represents normalized resistance values (i.e., the values of respective elements of the normalized offset arrays). These graphs illustrate examples of change characteristics associated with the respective temperature offsets from step S 2000 . Recall that the first data element of each array corresponds to the outermost measurement point near the edge of the wafer 20 , while the last data element of each array corresponds to the centermost measurement point of the wafer 20 . Thus, in FIGS. 11A-11F , each data element (except for the data element corresponding to the center) of the arrays has been plotted twice in order to illustrate the effect of the respective offsets across the entire wafer 20 rather than just across half of the wafer 20 .

Finally, at step S 3300 , lamp control parameters (e.g., revised offset values for the temperature probes 24 ) are determined based on the normalized offset arrays. In the present embodiment, this is accomplished by the parameter-processing device 36 ( FIG. 8 ) as follows. A wafer 20 is run in an RTP system 10 according to a prescribed recipe (e.g., 925° C. for 20 sec). After the wafer 20 is processed in the RTP system 10 , an array of raw data RAW (e.g., array of sheet resistances) for the processed wafer 20 is generated (e.g., according to steps S 1310 and S 1320 described above). The raw data array is then used to determine adjustment amounts (referred to hereinafter as “delta offsets”) for the baseline offset values determined at step S 1100 ( FIG. 5 ) as follows.

Recall that for each of the temperature probes T 1 -T 6 , a respective baseline offset value BO 1 -BO 6 was determined at step S 1100 ( FIG. 5 ). Now, a delta offset ΔO 1 -ΔO 6 will be calculated for each of the baseline offset value BO 1 -BO 6 . The delta offset values ΔO 1 -ΔO 6 are variables in a series of weighted error WE functions, where a weighted error WE is calculated for each of the corresponding elements of the normalized folded arrays according to the following expression:

WE k = { [ ( ( NAVE_T1 k ) ⁢ ( Δ ⁢ ⁢ O ⁢ ⁢ 1 ) + ⁢ ( NAVE_T2 k ) ⁢ ( Δ ⁢ ⁢ O ⁢ ⁢ 2 ) + ( NAVE_T3 k ) ⁢ ( Δ ⁢ ⁢ O ⁢ ⁢ 3 ) + ( NAVE_T4 k ) ⁢ ( Δ ⁢ ⁢ O ⁢ ⁢ 4 ) + ⁢ ( NAVE_T6 k ) ⁢ ( Δ ⁢ ⁢ O ⁢ ⁢ 6 ) + ( NAVE_T7 k ) ⁢ ( Δ ⁢ ⁢ O ⁢ ⁢ 7 ) ) + Δ ⁢ ⁢ RAW k ] 2 }

where k ranges from 1 to (n−l)/2, and ΔRAW k is the difference between the raw-data sheet-resistance value RAW k and an average of the raw-data sheet resistances according to the following expression:

where AVE(RAW) represents the average of first k resistance values in the RAW array. The delta offsets ΔO 1 -ΔO 6 are determined by selecting values for the delta offsets ΔO 1 -ΔO 6 such that a sum total of the weighted errors WE is minimized to achieve a least total error LTE. The least total error LTE can be expressed as follows:

LTE = min ⁢ ⁢ ( ∑ k = 1 ( n - 1 ) / 2 ⁢ ⁢ WE k )

The delta offset values ΔO 1 -ΔO 6 can be determined by the parameter-processing device 36 using processing software (e.g., where the parameter-processing device 36 is a computer), such as Excel Solver (developed and distributed by Microsoft Inc.), to determine what values of ΔO 1 -ΔO 6 will achieve a least total error LTE according to the above expressions.

Once the delta offsets ΔO 1 -ΔO 6 have been determined, new revised temperature offset values RO 1 -RO 6 for the temperature probes T 1 -T 6 , respectively, can be calculated that will now account for zone coupling and provide for a multi-zone interference correction. The revised temperature offset values RO 1 -RO 6 equal a sum of a respective one of the delta offsets ΔO 1 -ΔO 6 and a respective one of the baseline offset values BO 1 -BO 6 (i.e., RO 1 =BO 1 +ΔO 1 , RO 2 =BO 2 +ΔO 2 , etc.).

While various embodiments in accordance with the principles disclosed herein have been described above, it should be understood that they have been presented by way of example only, and are not limiting. Thus, the breadth and scope of the invention(s) should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the claims and their equivalents issuing from this disclosure. Furthermore, the above advantages and features are provided in described embodiments, but shall not limit the application of such issued claims to processes and structures accomplishing any or all of the above advantages.

Additionally, the section headings herein are provided for consistency with the suggestions under 37 CFR 1.77 or otherwise to provide organizational cues. These headings shall not limit or characterize the invention(s) set out in any claims that can issue from this disclosure. Specifically and by way of example, although the headings refer to a “Technical Field,” such claims should not be limited by the language chosen under this heading to describe the so-called technical field. Further, a description of a technology in the “Background” is not to be construed as an admission that technology is prior art to any invention(s) in this disclosure. Neither is the “Brief Summary” to be considered as a characterization of the invention(s) set forth in issued claims. Furthermore, any reference in this disclosure to “invention” in the singular should not be used to argue that there is only a single point of novelty in this disclosure. Multiple inventions can be set forth according to the limitations of the multiple claims issuing from this disclosure, and such claims accordingly define the invention(s), and their equivalents, that are protected thereby. In all instances, the scope of such claims shall be considered on their own merits in light of this disclosure, but should not be constrained by the headings set forth herein.