Single to dual non-overlapping converter

Embodiments of the present invention relate to signal generation in electronic circuits.

Electronic circuits use signals to perform functions. Some circuits use a single signal for a function. Some other circuits use two signals as a complementary signal pair for other functions in which one of the two signals is an inverted version of the other signal.

An inverter is usually used to generate an inverted signal (inverted version) of an input signal. The inverter has a time delay. Thus, the inverted signal generated by the inverter has a delay relative to the original input signal. In some cases, the delay caused by the inverter is negligible for some function. Hence, in some cases, the inverted signal generated by the inverter and the original input signal are used together as the complementary signal pair. However, in cases where synchronization between the original input signal and the inverted signal is needed, the inverted signal and the original input signal are unsuitable.

FIG. 1 shows a converter according to embodiments of the invention.

FIG. 2 is an exemplary timing diagram showing a signal relationship between an input signal and output signals of FIG. 1 .

FIG. 3 shows a converter having differential amplifiers according to embodiments of the invention.

FIG. 4A is an exemplary timing diagrams showing signal relationships between an input signal and each of the staged delay control signals of FIG. 3 .

FIG. 4B is an exemplary timing diagrams showing a signal relationship between an input signal and output signals of FIG. 3 .

FIG. 5 shows an integrated circuit according to embodiments of the invention.

FIG. 6 shows a system according to embodiments of the invention.

FIG. 7 is a flowchart of a method of generating signals according to embodiments of the invention.

The following description and the drawings illustrate specific embodiments of the invention sufficiently to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other changes. In the drawings, like features or like numerals describe substantially similar components throughout the several views. Examples merely typify possible variations. Portions and features of some embodiments may be included in or substituted for those of others. The scope of the invention encompasses the claims and all available equivalents.

FIG. 1 shows a converter according to embodiments of the invention. Converter 100 includes an input circuit 110 , and output circuits 140 and 150 . Input circuit 110 receives an input signal IN and generates a number of staged delay control signals CTL 1 , CTL 2 , CTL 3 , and CTL 4 . The IN signal is a single-ended signal. The CTL 1 , CTL 2 , CTL 3 , and CTL 4 signals are staged delay staged control signals such that each of the CTL 1 , CTL 2 , CTL 3 , and CTL 4 signals has a different amount of delay relative to the IN signal. In other terms, the amount of delay of the CTL 1 , CTL 2 , CTL 3 , and CTL 4 signals is different from one another with respect to the IN signal.

Output circuit 140 responds to the CTL 1 , CTL 2 , CTL 3 , and CTL 4 signals and generates an output signal OUT. Output circuit 150 responds to the CTL 1 , CTL 2 , CTL 3 , and CTL 4 signals and generates an output signal OUT*. The OUT* signal is a delayed copy of the IN signal. The OUT signal is an inverted copy of the OUT* signal. The OUT and OUT* signals form a complementary signal pair in which the OUT and OUT* signals are complimentary to each other. For example, when the OUT signal has a high signal level, the OUT* signal has a low signal level and when the OUT signal has a low signal level, the OUT* signal has a high signal level.

The CTL 1 , CTL 2 , CTL 3 , and CTL 4 signals are grouped into two different groups. A first groups includes copies of the IN signal. A second group includes inverted copies of the IN signal. For example, the CTL 1 and CTL 3 may be in the first group while the CTL 2 and CTL 4 may be in the second group. Since each of the CTL 1 , CTL 2 , CTL 3 , and CTL 4 signals has a delay relative to the IN signal, the signals in the first group are also delayed copies of the IN signal and the signals in the second group are also inverted and delayed copies of the IN signal. Thus, in the example above, the CTL 2 and CTL 4 signals are delayed copies of the IN signals; the CTL 1 and CTL 3 are inverted and delayed copies of the IN signal.

In some embodiments, each of the output circuits 140 and 150 includes a differential amplifier in which the differential amplifier includes an input stage with a first input side and a second input side. Each of the first and second input sides includes multiple input nodes. In these embodiments, input circuit 110 loads the first group of the staged delay control signals (e.g., CTL 1 and CTL 3 ) to the first input side of the differential amplifier of each of the output circuits 140 and 150 for an equal amount of time. Also in these embodiments, input circuit 110 loads the second group of the staged delay control signals (e.g., CTL 2 and CTL 4 ) to the second input side of the differential amplifier of each of the output circuits 140 and 150 for an equal amount of time. Based on the CTL 1 , CTL 2 , CTL 3 , and CTL 4 signals, the differential amplifiers of generate the OUT and OUT* signals.

When input circuit 110 loads a signal to the differential amplifier, input circuit 110 holds a signal level of the signal for an amount of time. For example, when input circuit 110 loads the CTL 1 signal to the first input side of the first and second differential amplifiers, input circuit 110 holds the CTL 1 signal at a signal level (e.g., high) for an amount of time. Input circuit 110 stops loading the CTL 1 when input circuit 110 switches the CTL 1 signal to a different signal level (e.g., low). In some embodiment, input circuit 110 switches the CTL 1 signal between different signals based on the frequency of the IN signal.

FIG. 2 is an exemplary timing diagram showing a signal relationship between the input signal and the output signals of FIG. 1 . In FIG. 2 , V 1 and V 2 are signal levels. In some embodiments, V 1 and V 2 correspond to voltage. FIG. 2 shows that the IN signal is a single-ended signal and has signal levels of V 1 and V 2 . Thus, the signal swing of the IN signal is V 1 and V 2 . The OUT* signal is a delayed copy of the IN signal. Label DL indicates the amount of delay between the IN and OUT* signal. The OUT signal is an inverted version or inverted copy of the OUT* signal.

Both of the OUT and OUT* signals also have signal levels at V 1 and V 2 . Thus, both of the OUT and OUT* signal have the same signal swing as that of the IN signal. In some embodiments, V 1 and V 2 correspond to rail-to-rail voltage levels such as Vcc and ground where Vcc is the supply voltage of converter 100 of FIG. 1 . Therefore, in some embodiments, the IN signal and both of the OUT and OUT* signals have a rail-to-rail signal swing.

As shown in FIG. 2 , the OUT and OUT* signals form a complementary signal pair such that the OUT and OUT* signals have opposing signal levels. A gap 201 exists between the high signal levels of the OUT and OUT* signals and a gap 202 exists between the low signal levels of OUT and OUT* signals. Gaps 201 and 202 indicate that the OUT and OUT* signals are non-overlapping signals. Since the OUT and OUT* signal are complementary to each other and are non-overlapping, the OUT and OUT* are non-overlapping complementary signal pair.

FIG. 3 shows a converter having differential amplifiers according to embodiments of the invention. Converter 300 includes an input circuit 310 and output circuits 340 and 350 . Input circuit 310 receives an input signal on an input node 311 and generates staged delay control signals CTL 1 , CTL 2 , CTL 3 , and CTL 4 at control nodes 321 – 324 ( 321 , 322 , 323 and 324 ). For simplicity, the CTL 1 , CTL 2 , CTL 3 , and CTL 4 signals are occasionally referred together as the CTL signals. Output circuit 340 responds to the CTL signals and generates an output signal OUT at an output node 371 . Output circuit 350 responds to the CTL signals and generates an output signal OUT* at an output node 381 . The IN signal is a single-ended signal. The OUT and OUT* are non-overlapping complementary signal pair.

Input circuit 310 includes a number of inverters 301 – 305 ( 301 , 302 , 303 , 304 , and 305 ) connected in series with input node 311 and control nodes 321 – 324 . Input circuit 310 propagates the IN signal through inverters 301 – 305 to generate the CTL signals. The CTL signals include different groups of staged delay control signals. The CTL 1 and CTL 3 signals form a first group of staged delay control signals. The CTL 2 and CTL 4 signals form a second group of staged delay control signals.

Each of the first and second groups has a signal on both side of a center node 333 at the center of inverters 302 – 305 . The CLT signals are staged such that within each group, a signal from one side of center node 333 has a delayed copy on the other side of center node 333 . For example, the CTL 4 signal is a delayed copy of the CTL 2 signal. The CTL 3 signal is a delayed copy of the CTL 1 signal.

As show in FIG. 3 , the CTL 2 and CTL 4 signals are delayed copies of the IN signal. The CTL 1 and CTL 3 signals are delayed and inverted copies of the IN signal. The CTL signals are staged around center node 333 such that on each side of center node 333 , a staged delay control signal from one group is an inverted version of a signal from the other group. For example, the CTL 2 signal is the inverted version of the CTL 1 signal. The CTL 3 signal is the inverted version of the CTL 4 signal.

Since the staged delay control signals CTL are generated from the IN signal, each of the CTL signals has a delay (relative delay) relative to the IN signal. The relative delay of each of the CTL signals is a multiple of an inverter delay. The inverter delay is a delay of one of the inverters 301 – 305 . For example, the CTL 1 signal has one inverter delay relative to the IN signal. The CTL 2 signal has two inverter delay relative to the IN signal. Thus, each of the CTL signals have a different delay relative to the IN signal. In other terms, the amount of delay of the CTL signals is different from one another with respect to the IN signal.

The differences in the delays of the CTL signals relative to the IN signal in allow input circuit 310 to control the signal levels and the timing of the OUT and OUT* signals of output circuits 340 and 350 .

Output circuit 340 includes switching units 341 and 342 , and a current source 343 . Current source 343 includes transistors 348 and 349 forming a current mirror with a first leg connected to switching unit 341 and a second leg connected to switching unit 342 . Switching unit 341 includes a pair of transistors 345 and 347 connected in parallel between current source 343 and a supply node 362 . Switching unit 342 includes a pair of transistors 344 and 346 connected in parallel between current source 343 and supply node 362 .

Switching units 341 and 342 , and current source 343 form a differential amplifier with output node 371 being the output node of the differential amplifier to provide the OUT signal. Switching unit 341 forms a first input side of the differential amplifier. Switching unit 342 forms a second input side of the differential amplifier. The combination of switching units 341 and 342 forms an input stage of the differential amplifier to receive the CTL signals to produce the OUT signal.

Output circuit 350 includes switching units 351 and 352 , and a current source 353 . Current source 353 includes transistors 358 and 359 , forming a current mirror with a first leg connected to switching unit 351 and a second leg connected to switching unit 352 . Switching unit 351 includes a pair of transistors 355 and 357 connected in parallel between current source 353 and supply node 362 . Switching unit 352 includes a pair of transistors 354 and 356 connected in parallel between current source 353 and supply node 362 .

Switching units 351 and 352 , and current source 353 form a differential amplifier with output node 381 being the output node of the differential amplifier to provide the OUT* signal. Switching unit 351 forms a first input side of the differential amplifier. Switching unit 352 forms a second input side of the differential amplifier. The combination of switching units 351 and 352 forms an input stage of the differential amplifier to receive the CTL signals to produce the OUT* signal.

During operation, output circuit 340 switches the OUT signal between different signal levels in response to the CTL signals. Output circuit 350 switches the OUT* signal between different signals levels but in an opposite direction from that of the OUT signal. For example, output circuit 340 switches the OUT signal from low to high while output circuit 350 switches the OUT* signal from high to low.

Output circuits 340 and 350 simultaneously receive the CTL signals to control the signal levels of the OUT and OUT* signal such that the OUT and OUT* signals form a complementary signal pair and the OUT and OUT* signals are non-overlapping. In some embodiments, the OUT and OUT* signals are non-overlapping such that the high signal level of the OUT signal does not overlap the high signal level of the OUT* signal. In other terms, the OUT and OUT* signals do not simultaneously have a high signal level.

The signal level of the OUT signal depends on the current in current paths A and B of output circuit 340 . The signal level of the OUT* signal depends on the current in current paths C and D of output circuit 350 .

Output circuit 340 controls the current in current paths A and B by controlling the gates of transistors in 345 and 347 with the CTL 1 and CTL 3 signals and by controlling the gate of transistors 344 and 346 with the CTL 2 and CTL 4 signals. Similarly, output circuit 350 controls the current in current paths C and D by controlling the gates of transistors in 355 and 357 with the CTL 1 and CTL 3 signals and by controlling the gate of transistors 354 and 356 with the CTL 2 and CTL 4 signals.

Input circuit 310 loads the gates of the transistors of output circuits 340 and 350 in a sequential manner to enable output circuits 340 and 350 to control the current in current paths A, B, C, and D such that OUT and OUT* signals are non-overlapping and form a complementary signal pair.

At a first time interval, input circuit 310 simultaneously loads the CTL 1 signal to the gates of transistor 345 and 355 for an equal amount of time or an equal loading time. At a second time interval, input circuit 310 simultaneously loads the CTL 2 signal to the gates of transistor 344 and 354 for an equal amount of time or an equal loading time. At a third time interval, input circuit 310 simultaneously loads the CTL 4 signal to the gates of transistor 346 and 356 for an equal amount of time or an equal loading time. At a fourth time interval, input circuit 310 simultaneously loads the CTL 3 to the gates of transistor 347 and 357 for an equal amount of time or an equal loading time.

In FIG. 3 , the operating principle is configuring input circuit 310 such that the original version IN signal (at node 311 ) and the inverted version of the IN signal (the signal at node 321 ) load the input nodes of output circuits 340 and 350 simultaneously for an equal amount of time. Equal loading of the original and inverted versions of the IN signal to the input nodes of output circuits 340 and 350 allows output circuits 340 and 350 to generate the OUT and OUT* signals in which the OUT and OUT* signals are non-overlapping and complementary to each other.

Input circuit 310 is configured with a series of inverters to interpolate the delay introduced by the inversion of the IN signal (delay introduced by inverter 301 ) on four inverter delay ( 302 , 303 , 304 , and 305 ) to produce the CTL signals. The CTL signals allow equal loading of the output circuits 340 and 350 . As described above, selected signal of the CTL signals (CTL 1 , CTL 2 , CTL 3 , and CTL 4 ) is simultaneously loaded to output circuits 340 and 350 such that output circuits 340 and 350 experience equal loading from each of the CTL signals. As a result, from the output circuits 340 and 350 point of view, the CTL signals are simultaneously loaded the input nodes of output circuits 340 and 350 with respect to center node 333 .

Since the CTL signals are resulted from the interpolation of the delay introduced to the IN signal by inverter 301 , loading the CTL signals for an equal amount of time to output circuits 340 and 350 is equivalent to loading the original version of IN signal and the inverted version of the IN signal to output circuits 340 and 350 for an equal amount of time. Thus, using input circuit 310 to interpolate the delay introduced to the single-ended input signal IN allows equal loading of output circuits 340 and 350 with the original and inverted versions of the IN signal; as a result, output circuits 340 and 350 is able to generate dual non-overlapping and complimentary output signals OUT and OUT* based on the single-ended input signal IN.

The interpolating technique described above allows converter 300 of FIG. 3 to perform a conversion of a single-ended input signal to dual non-overlapping and complementary output signals at high speed. In some embodiments, converter 300 produces the OUT and OUT* signals at a speed between five and ten gigahertz (5 GHz to 10 Ghz). Thus, in some embodiments, the IN signal has a frequency between 5 GHz to 10 Ghz and the OUT and OUT* signals also have a frequency between 5 GHz to 10 Ghz.

Converter 300 of FIG. 3 may be formed with an equivalent circuit to serve the same purpose. For example, converter 300 may be formed with the following changes: the transistors in switching units 341 , 342 , 351 , and 352 may be formed with p-type (p-channel) transistors instead of n-type (n-channel); node 362 may be connected to a supply voltage (e.g., Vcc) instead of ground; the transistors of current sources 343 and 353 may be formed with n-type transistors instead of p-type transistors; and node 361 may be connected to ground.

FIG. 4A is an exemplary timing diagrams showing signal relationships between the input signal and each of the staged delay control signals of FIG. 3 . In FIG. 4A , T 0 through T 4 represent times; V 1 and V 2 are signal levels. The IN signal and the CTL signals have the same signal swing between V 1 and V 2 . In some embodiments, V 1 and V 2 correspond to voltage levels. In some embodiments, V 1 and V 2 correspond to rail-to-rail voltage levels such as Vcc and ground, where Vcc is a supply voltage of converter 300 of FIG. 3 . Therefore, in some embodiments, the IN signal and the CTL signals have a rail-to-rail signal swing.

Each of the labels D 1 , D 2 , D 3 , D 4 , D 5 in FIG. 4A represents a fixed delay (time delay). The delays D 1 , D 2 , D 3 , D 4 , and D 5 in FIG. 4A correspond to the delays of inverters 301 – 305 , respectively, of FIG. 3 . As shown in FIG. 4 , each of the CTL signals has a delay relative to the IN signal. Since each of the D 1 , D 2 , D 3 , D 4 , and D 5 is the delay of an inverter such as each of the inverters 301 – 305 , each of the CTL signals has a delay equal to a multiple of the delay of an inverter relative to the IN signal. For example, the CTL 1 signal has a delay equal to one-inverter delay (D 1 ) relative to the IN signal; the CTL 2 signal has a delay equal to two-inverter delay (D 1 and D 2 ) relative to the IN signal. FIG. 4A shows that the delay between the CTL 2 and CTL 4 signal is two-inverter delay (D 3 and D 4 ) and the delay between the CTL 1 and CTL 3 signals is four-inverter delay (D 2 , D 3 , D 4 , and D 5 ). Thus, the delay between the CTL 2 and CTL 4 signals is less than the delay between the CTL 1 and CTL 3 signals.

The combination of different (unequal) delay of the staged delay control signals CTL relative to the IN signal allows output circuits 340 and 350 to generate a non-overlapping and complementary OUT and OUT* signals.

FIG. 4B is an exemplary timing diagrams showing a signal relationship between an input signal and the output signals of FIG. 3 . In FIG. 4B , V 1 and V 2 are signal levels. In some embodiments, V 1 and V 2 correspond to voltage levels. FIG. 4B shows that the IN signal is a single-ended signal and has signal levels of V 1 and V 2 . Thus, the signal swing of the IN signal is V 1 and V 2 . FIG. 4B shows that the OUT* signal is a delayed copy of the IN signal and the OUT signal is an inverted version or inverted copy of the OUT* signal. Label DL in FIG. 4B indicates the amount of delay between the IN and OUT* signals.

FIG. 4B also shows that both of the OUT and OUT* signals also have signal levels at V 1 and V 2 . Thus, both of the OUT and OUT* signal have the same signal swing as that of the IN signal. In some embodiments, V 1 and V 2 correspond to rail-to-rail voltage levels such as Vcc and ground, where Vcc is a supply voltage of converter 300 of FIG. 3 . Therefore, in some embodiments, the IN signal and both of the OUT and OUT* signals have a rail-to-rail signal swing.

FIG. 4B shows that OUT and OUT* signals form a complementary signal pair such that the OUT and OUT* signals have opposing signal levels. A gap 401 exists between the high signal levels of the OUT and OUT* signals and a gap 402 exists between the low signal levels of OUT and OUT* signals. Gaps 401 and 402 indicate that the OUT and OUT* signals are non-overlapping signals. Since the OUT and OUT* signal are complementary to each other and are non-overlapping, the OUT and OUT* are non-overlapping complementary signal pair.

In FIG. 4 , the IN signal and the OUT and OUT* signal may have a duty cycle different from 50 percent duty cycle.

FIG. 5 shows an integrated circuit according to embodiments of the invention. Integrated circuit 500 includes a converter 510 , a signal source 520 , data sources 531 and 532 , a latch circuit 540 , a select circuit 550 , and an internal circuit 560 . Converter 510 includes embodiments of converter 100 of FIG. 1 and converter 300 of FIG. 3 .

In FIG. 5 , converter 510 receives an input signal IN from signal source 520 and provides output signals OUT and OUT* to latch circuit 540 and select circuit 550 . The OUT and OUT* signals in FIG. 5 are non-overlapping complimentary signal pair similar to the OUT and OUT* signals described in FIG. 1 through FIG. 4 .

In FIG. 5 , latch circuit 540 uses the OUT and OUT* signal to pass a signal D 1 from data source 531 to internal circuit 560 . Latch circuit 540 includes latches 541 and 542 . In some embodiments, latches 541 and 542 form a master and slave network to sequentially pass the D 1 signal from data source to internal circuit 560 . For example, latch circuit 540 passes the D 1 signal to latch 541 when the OUT signal is high and the OUT* signal is low. Subsequently, latch circuit 540 passes the D 1 signal from latch 541 to internal circuit 560 via latch 542 when the OUT signal is low and the OUT* signal is high.

Select circuit 550 uses the OUT and OUT* signal to select either the D 2 and D 3 signal from data source 532 and passes the selected signal to internal circuit 560 . D 4 at the output of select circuit 550 represents the selected signal, which is either the D 1 or D 2 signal. Select circuit 550 includes switches 551 and 552 . In some embodiments, each of the switches 551 and 552 includes a pass gate having control nodes controlled by the OUT and OUT* signals to pass either the D 2 or D 3 signal to internal circuit 560 . For example, when the OUT signal is high and the OUT* signal is low, select circuit 550 selects the D 2 signal and passes the D 2 signal to internal circuit 560 via switch 551 . As another example, when the OUT signal is low and the OUT* signal is high, select circuit 550 selects the D 3 signal and passes the D 3 signal to internal circuit 560 via switch 552 . Internal circuit 560 receives the D 1 and D 4 signal for further processing. In some embodiments, signal source 520 includes a clock generator such that the IN signal is a clock signal.

In FIG. 5 , latch circuit 540 and select circuit 550 receive the OUT and OUT* signals from the same converter 510 . In some embodiments, each of the latch circuit 540 and select circuit 550 receives the OUT and OUT* signals from a separate converter.

FIG. 6 shows a system according to embodiments of the invention. System 600 includes processing unit or processor 610 , a memory device 620 , a memory controller 630 , a graphic controller 640 , an input and output (I/O) controller 650 , a display 652 , a keyboard 654 , a pointing device 656 , and a peripheral device 658 . A bus 660 connects all of these devices together. A clock circuit 670 provides an external clock signal to at least one of the devices of system 600 . In some embodiments, system 600 may omit one or more devices shown in FIG. 6 . In some embodiments, two or more devices shown in system 600 may be formed in a single chip.

Bus 660 may be conducting traces on a circuit board or may be one or more cables. Bus 660 may also connect the devices of system 600 by wireless means such as electromagnetic radiation (e.g., radio waves). Peripheral device 658 may be a printer, an optical device (e.g., a compact disc read only memory (CD-ROM) device or a digital video disc (DVD) device), a magnetic device (e.g., floppy disk driver), or an audio device (e.g., a microphone). Memory device 620 may comprise a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or a combination thereof.

At least one of the devices shown in system 600 includes embodiments of FIG. 1 through FIG. 5 . Thus, at least one of the devices shown in system 600 includes embodiments of a converter such as converter 100 or converter 300 described in FIG. 1 through FIG. 5 in which the converter generates a non-overlapping complementary signal pair based on a single-ended input signal. Further, at least one of the devices shown in system 600 includes embodiments of an integrated circuit such as integrated circuit 500 of FIG. 5 in which the integrated circuit uses a non-overlapping complementary signal pair to control a transfer of data among different circuits of the integrated circuit.

System 600 of FIG. 6 may take the form of computers (e.g., desktops, laptops, hand-helds, servers, Web appliances, routers, etc.), wireless communication devices (e.g., cellular phones, cordless phones, pagers, personal digital assistants, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, camcorders, digital cameras, MP3 (Motion Picture Experts Group, Audio Layer 4) players, video games, watches, etc.), and the like.

FIG. 7 is a flowchart of a method of generating signals according to embodiments of the invention. Method 700 generates non-overlapping and complementary signal pair based on a single-ended input signal.

Box 710 receives an input signal. In some embodiments, the input signal is single-ended clock signal.

Box 720 generates a number of staged delay control signals based on the input signal. Each of the staged delay control signals has a fixed timing relationship with the input signal. For example, each of the staged delay control signals has a fixed delay relative to the input signal. The staged delay control signals are groups into a first group of staged delay control signals and a second group of staged delay control signals. The first group of staged delay control signals includes inverted copies of the input signal, in which the amount of delay of the inverted copies is different from one another relative to the input signal. The second group of staged delay control signals includes delayed copies of the input signal, in which the amount of delay of the delayed copies is different from one another relative to the input signal. In some embodiments, box 720 propagates the input signal through an odd number of inverters connected in series to generate the staged delay control signals such that the fixed relative delay of each staged delay control signal is a multiple of an inverter delay.

In embodiments where the odd number of series-connected inverter are used, the first group of staged delay control signals includes a signal at the output of the first inverter in the series and a signal at the output of the last inverter in the series. Also in these embodiments, the second group of staged delay control signals includes signals at the output of the inverters located between the first and last inverters in the series.

The input signal and the staged delay control signals are similar to the IN and CTL signals described in FIG. 1 through FIG. 6 . In some embodiments, box 720 uses an input circuit such as input circuit 110 of FIG. 1 or input circuit 310 of FIG. 3 to receive the input signal and to generate the staged delay control signals.

Box 730 generates a first output signal. In some embodiments, the first output signal and the input signal have an equal signal swing. For example, both of the input signal and the first output signal have a low signal level of V 1 and a high signal level of V 2 , where V 1 and V 2 are voltage levels. In some embodiments, V 1 and V 2 are rail-to-rail voltage levels such as supply voltage level (e.g., Vcc) and ground.

In some embodiments, box 730 loads a first input side of an input stage of a first differential amplifier with the first group of staged delay control signals (e.g., the CTL 1 and CTL 3 signals) to control a first pair of parallel transistors in a first current path of the first differential amplifier. Box 730 also loads a second side of the input stage of the first differential amplifier with the second group of staged delay control signals (e.g., the CTL 2 and CTL 4 signals) to control a second pair of parallel transistors in a second current path of the first differential amplifier. The current in the first and second current paths of the first differential amplifier controls the signal level of the first output signal. In some embodiments, box 730 uses a different amplifier such as the differential amplifier of output circuit 340 of FIG. 3 to generate the first output signal.

Box 740 generates a second output signal. In some embodiments, the second and the input signal have an equal signal swing. In some embodiments, V 1 and V 2 are rail-to-rail voltage levels such supply voltage level (e.g., Vcc) and ground. In some embodiments, box 740 loads a first input side of an input stage of a second differential amplifier with the first group of staged delay control signals to control a first pair of parallel transistors in a first current path of the second differential amplifier. Box 730 also loads a second side of the input stage of the second differential amplifier with the second group of staged delay control signals to control a second pair of parallel transistors in a second current path of the second differential amplifier. The current in the first and second current paths of the second differential amplifier controls the signal level of the second output signal. In some embodiments, box 740 uses a different amplifier such as the differential amplifier of output circuit 350 of FIG. 3 to generate the second output signal.

In box 730 and box 740 , the first group of staged delay control signals is simultaneously loaded to the first input side of the input stages of the first and second differential amplifiers. The first group of staged delay control signals is loaded such that the first group of staged delay control signals controls the first input side of the input stages of the first and second differential amplifiers for an equal amount of time.

Similarly, in box 730 and box 740 , the second group of staged delay control signals is simultaneously loaded to the second side of the input stages of the first and second differential amplifiers. The second group of staged delay control signals is loaded such that the second group of staged delay control signals controls the second side of the input stages of the first and second differential amplifiers for an equal amount of time.

The first and second output signals generated in boxes 730 and 740 form a non-overlapping complementary signal pair such as the OUT and OUT* signal described in FIG. 1 through FIG. 6 .

In the description of FIG. 1 through FIG. 7 , portions and features of the converter or the devices in some embodiments may be included in or substituted for those of other embodiments.

It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.