Multiplexer with low parasitic capacitance effects

This application is a Continuation-in-part of application Ser. No. 10/893,999, Filed: Jul. 20, 2004 now U.S. Pat. No. 6,888,483, Titled: HIGH SPEED ANALOG TO DIGITAL CONVERTER, which is a Continuation of application Ser. No. 10/688,921, Filed: Oct. 21, 2003 now U.S. Pat. No. 6,788,238, Titled: HIGH SPEED ANALOG TO DIGITAL CONVERTER, which is a Continuation of application Ser. No. 10/349,073, Filed: Jan. 23, 2003 now U.S. Pat. No. 6,674,388, Titled: HIGH SPEED ANALOG TO DIGITAL CONVERTER, which is a Continuation of application Ser. No. 10/158,595, Filed: May 31, 2002 now U.S. Pat. No. 6,573,853, Titled: HIGH SPEED ANALOG TO DIGITAL CONVERTER, all of which are incorporated by reference herein.

1. Field of the Invention

The present invention relates to multiplexers, and, more particularly, to multiplexers with low cross-talk between signals.

2. Related Art

A subranging analog to digital converter (ADC) architecture is suitable for implementing high-performance ADC's (i.e. high speed, low power, low area, high resolution). FIG. 1 shows a generic two-step subranging architecture, comprising a reference ladder 104 , a coarse ADC 102 , a switching matrix 103 , a fine ADC 105 , coarse comparators 107 , fine comparators 108 and an encoder 106 . In most cases, a track-and-hold 101 is used in front of the ADC. In this architecture, an input voltage is first quantized by the coarse ADC 102 . The coarse ADC 102 compares the input voltage against all the reference voltages, or against a subset of the reference voltages that is uniformly distributed across the whole range of reference voltages. Based on a coarse quantization, the switching matrix 103 connects the fine ADC 105 to a subset of the reference voltages (called a “subrange”) that is centered around the input signal voltage.

Modem flash, folding and subranging analog to digital converters (ADC's) often use averaging techniques for reducing offset and noise of amplifiers used in the ADC. One aspect of averaging is the topology that is used to accomplish averaging, i.e., which amplifier outputs in which arrays of amplifiers are averaged together.

In general, flash, folding and subranging ADC's use cascades of distributed amplifiers to amplify the residue signals before they are applied to the comparators. These residue signals are obtained by subtracting different DC reference voltages from an input signal V in . The DC reference voltages are generated by the resistive ladder (reference ladder) 104 biased at a certain DC current.

High-resolution ADC's often use auto-zero techniques, also called offset compensation techniques, to suppress amplifier offset voltages. In general, autozeroing requires two clock phases (φ 1 and φ 2 ). During the auto-zero phase, the amplifier offset is stored on one or more capacitors, and during the amplify phase, the amplifier is used for the actual signal amplification.

Two different auto-zero techniques can be distinguished, which are illustrated in FIGS. 2 and 3 . The technique shown in FIG. 2 connects an amplifier 201 in a unity feedback mode during the auto-zero clock phase φ 1 . As a result, a large part of the amplifier 201 input offset voltage is stored on input capacitors C 1 a , C 1 b . The remaining offset is stored on output capacitors C 2 a , C 2 b if available.

The second technique, shown in FIG. 3 , shorts the amplifier 201 inputs during the auto-zero phase φ 1 and connects them to a DC bias voltage V res . Here, the amplifier 201 output offset voltage is stored on the output capacitors C 2 a , C 2 b . Many ADC architectures use a cascade of several (auto-zero) amplifiers to amplify the input signal prior to applying to the comparators 107 , 108 . In general, flash, folding and subranging ADC's use arrays of cascaded amplifiers, and averaging and interpolation techniques are used to improve performance.

Unfortunately, the performance of cascaded arrays of amplifiers degrades significantly at high clock and input signal frequencies. The cause of this degradation is illustrated in FIG. 4 when the reset technique shown in FIG. 3 is used, and where R SW is shown as a circuit element, and the current flow I C is explicitly shown.

When the amplifier 201 is in the auto-zero phase φ 1 , the input capacitors C 1 a , C 1 b are charged to the voltage V sample that is provided by the track-and-hold amplifier 101 . As a result, a current I C will flow through the input capacitors C 1 a , C 1 b and an input switch (not shown). Due to the finite on-resistance R SW of the input switch (see FIG. 4 ), an input voltage is generated, which will settle exponentially towards zero. This input voltage is amplified by the amplifier 201 and results in an output voltage that also slowly settles towards zero (assuming the amplifier 201 has zero offset).

Essentially, the auto-zero amplifier 201 is in a “reset” mode one-half the time, and in an “amplify” mode the other one-half the time. When in reset mode, the capacitors C 1 a , C 1 b are charged to the track-and-hold 101 voltage, and the current I C flows through the capacitors C 1 a , C 1 b and the reset switches, so as to charge the capacitors C 1 a , C 1 b.

When the ADC has to run at high sampling rates, there is not enough time for the amplifier 201 output voltage to settle completely to zero during the reset phase. As a result, an error voltage is sampled at the output capacitors C 2 a , C 2 b that is dependent on the voltage V sample . This translates into non-linearity of the ADC, and often causes inter-symbol interference (ISI).

The problem of ISI occurs in most, if not all, ADC architectures and various approaches exist for attacking the problem. The most straightforward approach is to decrease the settling time constants. However, the resulting increase in power consumption is a major disadvantage.

Another approach is to increase the time allowed for settling, by using interleaved ADC architectures. However, this increases required layout area. Furthermore, mismatches between the interleaved channels cause spurious tones. The ISI errors can also be decreased by resetting all cascaded amplifiers during the same clock phase. Unfortunately, this is not optimal for high speed operation either.

FIG. 9 illustrates a simple conventional multiplexer. As shown in FIG. 9 , two inputs, V 1 and V 2 are fed into two transistors, or switches, 902 A, 902 B, respectively. Depending on which of the switches 902 A, 902 B is on or off, the output voltage Vout is switched between V 1 and V 2 . Note that each of the transistors 902 A, 902 B has parasitic capacitance Cp. For clarity, only one of the transistors is shown with the parasitic capacitance, but it will be appreciated that all such transistors have some parasitic capacitance. The parasitic capacitance Cp causes signal feedthrough (also known as “leakage,” or “crosstalk”) of V 2 to V OUT when the transistor 902 B is supposed to be off. Similarly, when transistor 902 A is off, its parasitic capacitance causes signal feedthrough to Vout. This effect is undesirable in multiplexers.

FIG. 10 illustrates a conventional approach to decreasing signal feedthrough. This approach relies on the addition of two switches (transistors) to ground, 906 A and 906 B, and additional switches 904 A, 904 B, connected as shown in FIG. 10 . The switches 906 A, 906 B help reduce the signal feedthrough. However, this approach has two problems. It requires twice as many transistors for the same on-resistance Ron. Also, there is four times as much total gate capacitance in the overall circuit, which is important if the switches are clocked.

The present invention is directed to a multiplexer with low parasitic capacitance effects that substantially obviates one or more of the problems and disadvantages of the related art.

In one aspect of the invention there is provided a differential multiplexer including a plurality of multiplexing circuits. Each multiplexing circuit inputs a corresponding differential input signal including a positive input signal and a negative input signal, and outputs positive and negative output signals. Each multiplexing circuit includes first, second, third and fourth transistors. The first and second transistors input the positive input signal. The third and fourth transistors input the negative input signal. Outputs of the first and third transistors are connected to the positive output signal. Outputs of the second and fourth transistors are connected to the negative output signal. The positive and negative output signals are controlled using gate voltages on the first and fourth transistors. The second and third transistors are turned off when the differential multiplexer is in use.

In another aspect of the invention, there is provided a differential multiplexer including a plurality of multiplexing circuits. Each multiplexing circuit inputs a corresponding differential input signal including a positive input signal and a negative input signal, and outputs positive and negative output signals. Each multiplexing circuit includes a plurality of transistors cross-coupled to make leakage between the positive and negative input signals common mode in the positive and negative output signals.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE FIGS.

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 illustrates a conventional averaging topology.

FIGS. 2 and 3 illustrate conventional amplifier topologies with reset switches.

FIG. 4 illustrates a conventional amplifier topology and the source of the inter-symbol interference problem.

FIG. 5 illustrates a source of inter-symbol interference in greater detail.

FIG. 6 illustrates one embodiment of the present invention.

FIG. 7 illustrates another embodiment of the present invention.

FIG. 8 illustrates a reduction in inter-symbol interference using the present invention.

FIG. 9 illustrates a conventional multiplexer.

FIG. 10 illustrates a conventional approach to decreasing signal feedthrough.

FIG. 11 illustrates how the circuit of FIG. 6 can be used as a differential multiplexer.

FIG. 12 illustrates how the circuit FIG. 11 can be adapted to a 4:1 multiplexer.

Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

Recently, a technique to address the nonlinearity was published by Miyazaki et al., “A 16 mW 30 M Sample/s pipelined A/D converter using a pseudo-differential architecture,” ISSCC Digest of Tech. Papers, pp. 174–175 (2002), see particularly FIG. 10.5.2 therein. The technique applies only to amplifiers that use the auto-zero technique of FIG. 2 .

In Miyazaki, four extra switches and two extra capacitors are required. The resulting circuit topology has a common-mode transfer function of “1” and a differential-mode transfer function of “0” during the reset clock phase.

However, an important disadvantage of the circuit shown in Miyazaki is that it requires twice the amount of capacitance. This has a serious impact on the ADC layout area. Furthermore, the capacitive loading of the track-and-hold 101 doubles, which significantly slows down the charging of the capacitors C 1 a , C 1 b (roughly by a factor of two).

FIG. 5 shows the rationale for the present invention. In FIG. 5 , the track-and-hold amplifier 101 outputs a step function to the sampling capacitors C 1 a , C 1 b . Due to the finite resistance RSW, the pulse becomes a spike (i.e., it is effectively high-pass filtered) by the time it gets to the amplifier 201 , which is the first amplifier in a cascade. The next set of capacitors C 2 a , C 2 b sees a “smeared-out” pulse, which, by the time it is amplified by the next amplifier in a cascade (amplifier 202 ), and charges the next stage capacitors C 3 a and C 3 b , becomes further “smeared-out”. The spike being transferred throughout the cascaded amplifiers causes inter-symbol interference.

The problem of ISI can be solved in a very elegant way by complementing the reset switches shown in FIG. 3 with some additional switches before the fine amplifiers of the fine ADC 105 . The resulting circuit is shown in FIG. 6 . The extra switches are contained in the dashed box 510 (a transfer matrix or transfer circuit). FIG. 7 shows a modification of the new circuit that works in a similar way.

The transfer circuit shown in the dashed box 510 has a transfer function of “1” for common-mode signals at all times, so that the common mode transfer function is H CM (φ 1 )=1, H CM (φ 2 )=1. However, the transfer function varies for differential signals depending on the clock phase (φ 1 or φ 2 ). More specifically, the transfer function for differential signals is H DM (φ 1 )=0, and H DM (φ 2 )=1. Hence, a differential voltage created across nodes 1 and 2 (due to the charging of the input capacitors C 1 a , C 1 b ) is not transferred to input nodes 3 and 4 of the amplifier 201 during φ 1 . Therefore, the output voltage of the amplifier 201 is not affected by V sample in any way, reducing the occurrence of ISI. The input capacitors C 1 a , C 1 b subtract track-and-hold amplifier 101 voltage from a reference ladder 104 voltage.

The technique presented herein can find application in various types of ADC architectures that use auto-zero techniques for combating amplifier offsets.

FIG. 6 shows one embodiment of the present invention. φ 1 and φ 2 represent two phases of a clock, preferably non-overlapping phases. As shown in FIG. 6 , the sampling voltage V sample is differentially connected to two sampling capacitors C 1 a , and C 1 b , which are in turn connected to three switch transistors Ma, Mb and Mc. Gates of the switch transistors Ma, Mb, Mc are connected to φ 1 , a drain of the transistor Ma is connected to V res , and a source of the transistor Mc is connected to the reset voltage V res . Between the amplifier 201 and the switch transistors Ma, Mb, Mc, the transfer matrix 510 comprises four transistors M 1 , M 2 , M 3 and M 4 . Gates of the transistors M 2 and M 3 are connected to φ 1 . Gates of the transistors M 1 and M 4 are connected to V dd , the supply voltage. Sources of the transistors M 1 and M 2 are tied together and to the node 1 , which is also connected to the sampling capacitor C 1 a . Sources of the transistors M 3 and M 4 are tied together and also connected to a node 2 , which is also connected to the sampling capacitor C 1 b . Drains of the transistors M 3 and M 1 are tied together and to node 3 , which is the “+” input of the amplifier 201 . Drains of the transistors M 2 and M 4 are tied together and to node 4 , which is also connected to the “−” input of the amplifier 201 .

Thus, the circuit within the dashed box 510 may be referred to as a transfer matrix that has a property such that its differential mode transfer function H(φ 1 )=0, H(φ 2 )=1. This is different from a conventional approach, where the transfer function may be thought of as being H=1 for both φ 1 and φ 2 .

It will be appreciated that while the overall transfer function of the transfer matrix 510 is H DM (φ 1 )=0, H DM (φ 2 )=1, H CM (φ 1 )=1, H CM (φ 2 )=1, this is primarily due to the switches M 1 –M 4 , which essentially pass the differential voltage of nodes 1 and 2 through to nodes 3 and 4 respectively, on φ 2 . However, the gain factor need not be exactly 1, but may be some other value. The important thing is that it be substantially 0 on φ 2 .

FIG. 7 represents another embodiment of the present invention. The elements of FIG. 7 correspond to the same-numbered elements of FIG. 6 , however, the position of the transfer matrix 510 is before the three transistors Ma, Mb and Mc, rather than after. This results in lower noise operation, compared to the embodiment shown in FIG. 6 . The embodiment shown in FIG. 6 , however, generally allows for higher frequency operation, compared to the embodiment of FIG. 7 .

Note that either PMOS or NMOS transistors may be used as switches in the present invention. Note further that given the use of the FET transistors as switches (rather than the amplifiers), the drain and the source function equivalently.

FIG. 8 illustrates the improvement in the signal due to the transfer matrix 510 . Note that the transistors Ma, Mb, Mc and the transistors of the transfer matrix M 1 –M 4 , are PMOS transistors, with the negative supply Vss used instead of the positive supply V dd . As may be seen from FIG. 8 , the amount of spike seen by the amplifier 201 after a step function outputted from the track-and-hold 101 is dramatically decreased due to the transfer function of the transfer matrix 510 . φ 1e in FIG. 8 refers to an “early” phase φ 1 of the two-phase clock. The small spike seen in FIG. 8 is due to a mis-match of the transistors M 1 –M 4 , and disappears entirely if the transistors are made bigger. In the event there is no spike (i.e., the transistors M 1 –M 4 are perfectly matched), an approximately 50% improvement in speed is expected.

Note further that in the event of using a plurality of cascaded amplifier stages for a pipeline architecture (designated A, B, C, D), if the A and B stage switches are driven by the phase φ 1 , and the C and D stages are driven by φ 2 , the transfer matrix 510 is only needed for the A stage and the C stage. On the other hand, if the switches of the stages A, B, C and D are driven by alternating clock phases (i.e., φ 1 , φ 2 , φ 1 , φ 2 ), each stage will need its own transfer matrix 510 .

Although the above discussion is primarily in terms of analog to digital converters, and the application of the circuit 510 shown in FIG. 6 is directed to analog to digital converters, it will also be appreciated that the circuit 510 can be used as a multiplexer, in applications other than analog to digital converters. This is because the signal feedthrough in a circuit such as 510 is substantially less than in conventional multiplexers.

FIG. 11 illustrates how the circuit discussed previously, here labeled 510 A and 510 B, can be used as a differential multiplexer. As shown in FIG. 11 , the differential multiplexer includes two circuits 510 A, 510 B, each of which is identical and includes four transistors, M 1 A, M 2 A, M 3 A, and M 4 A in circuit 510 A, and corresponding transistors in the circuit 510 B. The circuit 510 A inputs the positive differential signal V 1 (V 1,POS , V 1,NEG ) and the circuit 510 B inputs the differential signal V 2 (V 2,POS , V 2,NEG ). The output of the two circuits 510 A, 510 B is thus the differential output (V O,POS , V O,NEG ). Thus, for each circuit 510 , for each group of four transistors, the middle two transistors (e.g., M 2 A, M 3 A) are always off; their purpose is that feedthrough from V 2 pos now goes to both V O,POS and V O,NEG . In other words, the middle switches, M 2 A, M 3 A, M 2 B, M 3 B are used for isolation. The purpose of the middle switches, M 2 A, M 3 A, M 2 B, M 3 B, is to provide effectively a “mirror parasitic capacitance” for the outer switches M 1 A, M 4 A, M 1 B, M 4 B, etc.

Therefore, the feedthrough, or leakage is common mode, and does not appear in the differential output voltage (V O,POS , V O,NEG ). Thus, for the circuit 510 A, both the common mode and the differential mode transfer function are one. For the circuit 510 B, both transfers functions are zero.

This circuit has the advantage that there is no need to have switches in series, therefore the on-resistance Ron is not higher than in the conventional circuit shown in FIG. 9 . Also, if the switches are clocked, the gate capacitance is lower than in the conventional circuit of FIG. 10 .

FIG. 12 illustrates how the multiplexer circuit 510 described above can be adapted to not just a 2:1 multiplexer, but to, for example, a 4:1 multiplexer. This figure illustrates how the multiplexing concept shown in FIG. 11 can be generalized to any N:1 multiplexer. Four multiplexing circuits 510 A– 510 D are arranged as shown, with the differential inputs V 1 –V 4 fed into the four circuits 510 A– 510 D. A single differential output (V O,POS , V O,NEG ) is generated, with minimal feedthrough from any of the non-selected inputs to the output.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.