LexDanaLexDanabeta
Inventor

Jan Mulder

Inventor
Houten, NL

Overview

54→
Patents
1994–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 54 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Mprimary
H03MCoding34%
H03KPulse technique24%
H03FAmplifiers9%
H03HImpedance networks, e.g. resonant circuits8%
H04LTransmission of digital information, e.g. telegraphic communication8%
H04BTransmission6%
G01RMeasuring electric variables2%
H02HEmergency protective circuit arrangements2%
B65DContainers for storage or transport of articles or materials, e.g. bags, barrels, bottles, boxes, cans, cartons, crates, drums, jars, tanks, hoppers, forwarding containers1%
G11BInformation storage based on relative movement between record carrier and transducer1%
PatentTitleYear
10,903,641Fast overvoltage protection circuit with digital control202110,250,338Transmitter drive with improved transmitter performance and reliability201910,084,626Wireless transmitter using a widebrand digital-to-analog converter for processing multiple channels in a digital radio-frequency signal201810,014,877Multi-segmented all logic DAC20189,806,924'Wireless transmitter using a wideband digital-to-analog converter for processing multiple channels in a digital radio-frequency signal'20179,543,752'Overvoltage protection circuit with digital control'20179,413,385'Efficient decoder for current-steering digital-to-analog converter'20169,362,940'Parallel sample-and-hold circuit for a pipelined ADC'20169,325,336'Gain calibration of ADC residue amplifiers'20168,598,906'Low-power ethernet transmitter'20138,410,820'High speed latch comparators'20138,401,502'Method and system for a control scheme on power and common-mode voltage reduction for a transmitter'20138,253,470'Offset calibration for amplifiers'20127,906,992'High speed latch comparators'20117,800,449'Single-ended-to-differential converter with common-mode voltage control'20107,710,184'ISI reduction technique'20107,616,144'Resistor ladder interpolation for PGA and DAC'20097,589,655'Method and system for a control scheme on power and common-mode voltage reduction for a transmitter'20097,587,181'Method and system for a control scheme on power and common-mode voltage reduction for a transmitter'20097,482,891'Interpolating programmable gain attenuator'20097,423,569'Method and system for a control scheme on power and common-mode voltage reduction for a transmitter'20087,352,215'High speed latch comparators'20087,324,038'Subranging analog to digital converter with multi-phase clock timing'20087,271,755'Resistor ladder interpolation for PGA and DAC'20077,262,639'High-speed comparator'20077,256,725'Resistor ladder interpolation for subranging ADC'20077,242,267'Interpolating programmable gain attenuator'20077,208,980'Comparator with offset compensation'20077,190,298'Resistor ladder interpolation for subranging ADC'20077,170,701'Amplifier with a strong output current'20077,135,942'Interpolating programmable gain attenuator'20067,129,865'High speed, low power comparator'20067,019,679'Multiplexer with low parasitic capacitance effects'20066,888,483'High speed analog to digital converter'20056,876,318'Method for increasing rate at which a comparator in a metastable condition transitions to a steady state'20056,873,210'Single-ended-to-differential converter with common-mode voltage control'20056,867,621'Class AB digital to analog converter/line driver'20056,831,585'Distributed averaging analog to digital converter topology'20046,788,238'High speed analog to digital converter'20046,784,818'Analog to digital converter with interpolation of reference ladder'20046,771,127'Single-ended-to-differential converter with common-mode voltage control'20046,727,756'Single-ended-to-differential converter with common-mode voltage control'20046,727,839'High speed, low power comparator'20046,720,798'Class AB digital to analog converter/line driver'20046,697,005'Analog to digital converter with interpolation of reference ladder'20046,674,388'High speed analog to digital converter'20046,664,910'Distributed averaging analog to digital converter topology'20036,653,966'Subranging analog to digital converter with multi-phase clock timing'20036,642,794'Noise and input impedance matched amplifier'20036,639,430'High speed latch comparators'20036,628,224'Distributed averaging analog to digital converter topology'20036,583,747'Subranging analog to digital converter with multi-phase clock timing'20036,573,853'High speed analog to digital converter'20035,337,914'Lined container'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994Based in Auckland, NZ· patent location history
2003–2017Patents assigned to BROADCOM CORP (45)· patent assignee history
2003–2007Patents assigned to KONINKL PHILIPS ELECTRONICS NV (2)· patent assignee history
2003–2018Based in Houten, NL· patent location history
2010–2021Based in Bunnik, NL· patent location history
2012–2013Patents assigned to MULDER JAN (4)· patent assignee history
2017–2021Patents assigned to AVAGO TECHNOLOGIES GENERAL IP (5)· patent assignee history
2019–2021Patents assigned to AVAGO TECH INT SALES PTE LID (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
BROADCOM CORP452003–2017
AVAGO TECHNOLOGIES GENERAL IP52017–2021
MULDER JANself42012–2013
AVAGO TECH INT SALES PTE LID22019–2021
KONINKL PHILIPS ELECTRONICS NV22003–2007
Locations
LocationPatentsSpan
Houten, NL502003–2018
Bunnik, NL32010–2021
Auckland, NZ11994