Magnetic memory device and method of reading information

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2004-035402, filed Feb. 12, 2004, the entire contents of which are incorporated herein by reference.

1. Field of the Invention

The present invention relates to a magnetic memory device and a method of reading information, and in particular, to, for example, the circuit configuration of memory cell through read bit lines through in a magnetic memory device and a method of reading information from a magnetic memory device.

2. Description of the Related Art

Each cell in a magnetic random access memory (MRAM) using a tunneling magneto resistive (TMR) effect is composed of an magnetic tunnel junction (MTJ) element and a selection transistor having one end connected to the MTJ element and the other end connected to a ground potential line.

Information can be read from a magnetic memory device at a low voltage utilizing a good MR ratio. However, a sense amplifier is composed of a conventional n-type Metal Oxide Semiconductor (MOS) transistor or CMOS transistor, so that as the power voltage decreases and the bit line voltage correspondingly approaches its threshold, information may not be read at high speed or read operations are disabled. Thus, a mechanism is required which increases the amplitude of the sense amplifier with respect to the magnitude of a read signal, that is, the amplitude of bit lines. Such an overdrive technique for the sense amplifier is described in “A 0.9V Sense-Amplifier Driver for High-Speed Gb-Scale DRAMs”, K. Gotoh et al., Symposium On VLSI cir., June, 1996, and “Low Voltage High Speed Circuit Designs for Giga-bit DRAMs”, K-C Lee et al., Symposium On VLSI Cir. June, 1996. These techniques enable the read margin to be increased. However, these techniques relate to dynamic RAMs (DRAMs). Accordingly, if they are applied directly to an MRAM, the problem described below may occur. When these techniques are applied to an MRAM, a voltage amplified by overdriving read bit lines is applied to the MTJ element. As a result, the insulating film in the MTJ element may be degraded or damaged. This problem has come more marked particularly because MRAMs have been miniaturized to reduce the thickness of the insulating film in the MTJ element and thus the insulating withstand voltage (for example, 10 [MV/cm]).

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a memory cell having an MTJ element, one end of the memory cell selectively electrically connected to a ground potential line; a first bit line electrically connected to another end of the memory cell; a sense amplifier which amplifies a difference in potential between the first bit line and a second bit line complementary to the first bit line so that the difference is equal to or larger than a difference between an internal power potential and a ground potential; and a connection circuit which disconnects the MTJ element from an electric connection between the ground potential line and the sense amplifier.

According to a second aspect of the present invention, there is provided a semiconductor device comprising: a memory cell having an MTJ element; a first bit line electrically connected to the memory cell; a sense amplifier which amplifies a difference in potential between the first bit line and a second bit line complementary to the first bit line so that the difference is equal to or larger than a difference between an internal power potential and a ground potential; and a connection circuit which selectively electrically connects the sense amplifier and the MTJ element.

According to a third aspect of the present invention, there is provided a semiconductor device comprising: a memory cell having an MTJ element and a switching element which selectively electrically connects one end of the MTJ element to a ground potential line; a first bit line electrically connected to the memory cell; a sense amplifier which amplifies a difference in potential between the first bit line and a second bit line complementary to the first bit line so that the difference is equal to or larger than a difference between an internal power potential and a ground potential; and a control circuit which disconnects the switching element to float the memory cell before the sense amplifier amplifies the potential difference.

According to a fourth aspect of the present invention, there is provided a method of reading information comprising: reading out potential according to information contained in an MTJ element to a first bit line by electrically connecting the MTJ element to a ground potential line and the first bit line; disconnecting the MTJ element from electric connection between the ground potential line and a sense amplifier; and after the disconnection, amplifying a difference in potential between the first bit line and a second bit line complementary to the first bit line so that the difference is equal to or larger than a difference between an internal power potential and a ground potential.

FIG. 1 is a block diagram showing a magnetic memory device according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram of essential parts of magnetic memory devices according to the first embodiment of the present invention;

FIG. 3 is a circuit diagram showing a current mirror current source circuit;

FIG. 4 is a timing chart showing the potentials of essential parts of the magnetic memory device according to the first embodiment of the present invention;

FIG. 5 is a diagram showing the circuit configuration of essential parts of the magnetic memory device according to a second embodiment of the present invention;

FIG. 6 is a timing chart showing the potentials of essential parts of the magnetic memory device according to the second embodiment of the present invention;

FIG. 7 is a diagram showing the circuit configuration of essential parts of a magnetic memory device according to a third embodiment of the present invention;

FIG. 8 is a timing chart showing the potentials of essential parts of the magnetic memory device according to the third embodiment of the present invention;

FIG. 9 is a diagram showing the circuit configuration of essential parts of a magnetic memory device according to a fourth embodiment of the present invention;

FIG. 10 is a timing chart showing the potentials of essential parts of the magnetic memory device according to the fourth embodiment of the present invention; and

FIG. 11 is a diagram showing a variation of the first and second embodiments.

Embodiments of the present invention will be described below with reference to the drawings. In the description below, components having the same functions and configurations are denoted by the same reference numerals. Duplicate descriptions will be given only when required.

(First Embodiment)

FIG. 1 is a block diagram showing a magnetic memory device according to a first embodiment of the present invention. As shown in FIG. 1 , a memory cell array MCA is provided which has memory cells MC arranged, for example, in a matrix. Each memory cell MC is composed of an MTJ element and a selection transistor (neither of which are shown). The MTJ element has a stacked structure including two ferromagnetic films and an insulating film sandwiched between the ferromagnetic films. The MTJ element records information utilizing a variation in magnetic resistance based on a spin polarization tunnel effect.

A bit line BL and a write word line WWL are provided so as to sandwich the two ferromagnetic layers between the lines with the MTJ element located at an intersection and with a space between each line and the layers. A read word line WL is connected to the gate of the selection transistor to select the memory cell MC. The potentials on the read word line WL and write word line are controlled by a row decoder RD.

Information is written to the MTJ element by the bit line BL and the write word line WWL by using a synthetic magnetic field to change a relative direction between the spins in the two ferromagnetic films. Information is read from the MTJ element by applying a voltage between the two ferromagnetic films in the selected cell and reading a resistance value from a current flowing through the ferromagnetic films. Alternatively, it is possible to allow a constant current to flow through the MTJ element in the selected cell and then to read the voltage between the two ferromagnetic films.

Each memory cell MC is connected to the bit line BL. A memory cell connection control circuit 1 is provided on the bit lines BL between the memory cell array MCA and the sense amplifier SA. The memory cell connection control circuit 1 provides such control as connection or disconnection of each of paths in accordance with control by a control circuit 2 . The sense amplifier is provided for each pair of bit lines. A column decoder CD controls the potentials of the bit lines so that only predetermined bit lines (bit line pairs) are operated in accordance with an externally supplied address signal.

In short, a read operation is performed as described below. First, the row decoder RD selects the world line WL connected to a target memory cell MC. Then, a read voltage is applied to the target memory cell MC. The column decoder CD operates so as to activate the sense amplifier SA connected to the bit line connected to this memory cell MC. Then, the sense amplifier SA amplifies the potential on the bit line BL to read data from the bit line BL.

FIG. 2 shows the circuit configuration of essential parts of the magnetic memory device in FIG. 1 . As shown in FIG. 2 , the bit line BL and a bit line /BL (the symbol / denotes negative logic; this applies to the description below) complementary to the bit line BL are provided. A precharge circuit 3 is connected between the bit lines BL and /BL and fixes the bit lines BL and /BL at a predetermined potential, for example, an intermediate value Vd/2 between an internal power potential Vd and the ground potential Vss in a standby state. Lowering the power potential Vcc may generate the internal power potential Vd. The precharge circuit 3 is composed of, for example, two n-type MOS transistors QN 1 and QN 2 connected in series. The connection node between the transistors QN 1 and QN 2 is connected to a potential generating circuit 4 a that supplies the potential Vd/2. A signal line PC is connected to gates of the transistors QN 1 and QN 2 . A signal (potential) on the signal line PC is controlled by the control circuit 2 .

The memory cell MC is connected to each of the bit lines BL and /BL. The memory cell MC is composed of an MTJ element MTJ and a selection transistor Q connected in series. The read word line (hereinafter simply referred to as a word line) WL is connected to a gate of the selection transistor Q. An end of the MTJ element MTJ which is opposite the connection node between the MTJ element MTJ and the selection transistor Q is connected to the bit line BL (bit line /BL). An end of the selection transistor which is opposite the connection node between the selection transistor and the MTJ element is grounded.

A read potential supplying circuit 5 is connected between the bit lines BL and /BL. The read potential supplying circuit 5 applies a read potential (internal power potential Vd−ground potential Vss) to the memory cell MC and setting the potentials on the bit lines BL and /BL at a reference potential (for example, the potential Vd/2). The read potential supplying circuit 5 is composed of, for example, four p-type MOS transistors QP 1 to QP 4 connected in series. A signal line SI is connected to gates of the transistors QP 1 and QP 4 . A signal on the signal line SI is controlled by the control circuit 2 . The connection node between the transistors QP 2 and QP 3 is connected to a potential generating circuit 4 b that supplies the internal power potential Vd. A current Iload supplied by a current mirror current source is supplied to the transistors QP 2 and QP 3 .

The memory cell connection control circuit 1 is inserted into the path of the bit lines BL and /BL. Specifically, the bit lines BL and /BL are separated into a memory cell side of the memory cell connection control circuit 1 (bit lines BL and /BL) and a sense amplifier side of the memory cell connection control circuit 1 (signal lines SN and /SN). The memory cell connection control circuit 1 controls the connection between the bit line BL and the signal line SN and the connection between the bit line /BL and the signal line /SL in accordance with a signal on a signal line ISO. The signal on the signal line ISO is controlled by the control circuit 2 . The memory cell connection control circuit 1 is typically composed of n-type MOS transistors QN 3 and QN 4 provided on the bit lines BL and /BL, respectively. The signal line ISO is connected to gates of the transistors QN 3 and QN 4 .

The sense amplifier SA is connected between the signal lines BL and /BL. The sense amplifier SA has an overdrive function of amplifying the difference in potential between the bit lines BL and /BL so that the difference is equal to or larger than the difference between the internal power potential Vd and the ground potential Vss. Specifically, a potential generating circuit 4 c supplies a sense amplifier supply potential Vup (=Vd +Δ) to the sense amplifier SA. The sense amplifier SA thus sets the potential of one of the bit lines BL and /BL at Vss and amplifies the potential of the other to Vup. The potential Vup can be generated by boosting the internal power potential Vd. Alternatively, the power potential Vcc may be directly used.

The sense amplifier SA is composed of, for example, two n-type MOS transistors QN 5 and QN 6 connected in series and two p-type MOS transistors QP 5 and QP 6 connected in series. The transistors QN 5 and QN 6 are connected between the signal lines SN and /SN. Likewise, the transistors QP 5 and QP 6 are also connected between the signal lines SN and /SN. Gates of the transistors QN 5 and QP 5 are connected to the signal line /SN. Gates of the transistors QN 6 and QP 6 are connected to the signal line SN.

The connection node between the transistors QP 5 and QP 6 is connected to one end of each of the p-type transistors QP 7 and QP 8 . A potential generating circuit 4 a supplies the potential Vd/2 to the other end of the transistor QP 7 . A potential generating circuit 4 c supplies the potential Vup to the other end of the transistor QP 8 . Gates of the transistors QP 7 and QP 8 are connected to signals SC 1 and SC 2 , respectively. Signals on the signal lines SC 1 and SC 2 are controlled by the control circuit 2 .

The connection node between the transistors QN 5 and QN 6 is connected to one end of each of the n-type transistors QN 7 and QN 8 . The potential generating circuit 4 a supplies the potential Vd/2 to the other end of the transistor QN 7 . The other end of the transistor QN 8 is grounded. Gates of the transistors QN 7 and QN 8 are connected to signals SC 3 and SC 4 , respectively. Signals on the signal lines SC 3 and SC 4 are controlled by the control circuit 2 .

The other ends of the signal lines SN and /SN are connected to the respective data lines (not shown) via transistors QN 9 and QN 10 . A signal line CSL from the control circuit 2 is connected to gates of the transistors QN 9 and QN 10 .

FIG. 3 is a circuit diagram showing the current mirror current source circuit. An output from the current mirror current source circuit in FIG. 3 generates the current Iload supplied to the read potential supplying circuit 5 in FIG. 2 . As shown in FIG. 3 , one end of a p-type MOS transistor QP 9 connects to an end of the current mirror current source circuit which is connected to the potential generating circuit 4 b , which generates the potential Vd. The other end of the transistor QP 9 constitutes an output end and is grounded via a constant current source I. The other end of the transistor QP 9 is also connected to the gate of the transistor QP 9 .

Now, the operation of the magnetic memory device in FIG. 2 will be described with reference to FIG. 4 . FIG. 4 is a timing chart showing the potentials of essential parts of the magnetic memory device in FIG. 2 . An example will be described in which the two MTJ elements MTJ store respective pieces of information complementary to each other and in which two memory cells store one bit of information. Specifically, “0” information means the case in which the memory cell MC connected to the bit line BL stores “0” information, whereas the memory cell connected to the bit line /BL stores “1” information. The opposite case corresponds to “1” information. Accordingly, it is assumed that before the read operation described below, the complementary pieces of information are already stored in the two memory cells MC.

As shown in FIG. 4 , during standby, the potential on the signal line PC (hereinafter simply referred to the signal line PC; this applies to the description below) is at a high level (potential Vd), so that the precharge circuit 3 is on. The bit lines BL and /BL have the potential Vd/2. The signal SI is at the high level, so that the read potential supplying circuit 5 is off. The word line WL is at a low level (potential Vss). The signal ISO is at the high level. Thus, the bit line BL and the signal line SN are connected together, and the bit line /BL and the signal line /SN are connected together. As a result, the potentials on the bit lines BL and /BL is the same as those of the signals SN and /SN, respectively.

Furthermore, the signals SC 1 and SC 4 have the potential Vss. The signal SC 2 has the potential Vup. The signal SC 3 has the potential Vd. Accordingly, the potential (sense amplifier supply potential) SAN of the connection node between the transistors QN 5 and QN 6 and the potential (sense amplifier supply potential) SAP of the connection node between the transistors QP 5 and QP 6 each have a value of Vd/2.

When information is read, at a time T 1 , the signal PC is set the low level, the potential of the word line WL connected to the selected cell is set at the high level, and the signal SI is set at the low level. As a result, a read potential is supplied to the memory cells MC. The potentials on the bit lines BL and /BL increase or decrease depending on resistance values that in turn depend on the information in the MTJ elements connected to the bit lines BL and /BL, respectively. In this case, both sense amplifier supply potentials SAP and SAN have a value of Vd/2, so that the sense amplifier does not start operation.

Then, the time passes which is required to adequately change the potentials on bit lines BL and /BL. At a time T 2 , the signal ISO changes to the low level. Thus, the memory cells MC and the sense amplifier SA are disconnected from each other.

Then, at a time T 3 , the signals SC 2 and SC 3 lower to the potential Vss, the signal SC 1 rises to the potential Vup, and the signal SC 4 rises to the potential Vd. Accordingly, the sense amplifier supply potential SAP rises to the potential Vup. The sense amplifier supply potential SAN lowers to the potential Vss. As a result, the sense amplifier SA starts operation. One of the signals SN and /SN rises to the potential Vup, while the other lowers to the potential Vss. Then, the transistors QN 9 and QN 10 are turned on (not shown) to load the signals SN and /SN onto the corresponding data lines.

Then, at a time T 4 , signals SC 1 and SC 4 lower to the potential Vss, the signal SC 2 rises to the potential Vup, and the signal SC 3 rises to the potential Vd. Thus, the sense amplifier supply potentials SAP and SAN change to Vd2. Consequently, the sense amplifier SA stops operation. Furthermore, the signals SN and /SN change to the potential Vd/2.

Then, at a time T 5 , the signal PC changes to the high level, the signal SI changes to the high level, and the word line WL changes to the low level. Thus, the bit lines BL and /BL are precharged to the potential Vd/2.

Subsequently, at a time T 6 , the signal ISO changes to the high level. The bit lines BL and /BL and the signal lines SN and /SN are connected together to shift the device to a standby state. The operations between the times T 1 and T 6 define one cycle of read operations. That is, owing to the use of nondestructive reads, the MRAM does not require any rewrite operations, which are required for DRAMs.

According to the magnetic memory device according to the first embodiment of the present invention, after information from the memory cell MCs is loaded onto the bit lines BL and /BL, the memory cells MC and the sense amplifier SA are disconnected from each other. Then, sense amplification is carried out using an overdrive technique. Thus, even if the overdrive changes the potentials on the signal lines SN and /SN to values equal to or larger than Vd, these potentials are not transmitted to the MTJ element MTJ. This avoids applying a high voltage to the opposite ends of the MTJ element MTJ. It is thus possible to enable a read operation with a high margin using the overdrive technique, which is required to activate the sense amplifier in a low voltage operation, while preventing the degradation or destruction of the MTJ element MTJ attributed to the application of a high voltage to the MTJ element MTJ.

(Second Embodiment)

A second embodiment has a circuit configuration similar to that of the first embodiment, and the sense amplifier supply potentials SAP and SAN in the second embodiment are different from those in the first embodiment.

FIG. 5 is a diagram showing the circuit configuration of essential parts of a magnetic memory device according to the second embodiment of the present invention. The circuit in FIG. 5 is similar to that in FIG. 2 . Accordingly, only the differences from FIG. 2 will be described below. As shown in FIG. 5 , the potential Vd from the potential generating circuit 4 b is supplied to the other end of the transistor QP 8 , which is partly responsible for the control of the sense amplifier supply potential SAP. The potential Vdown (=Vss−Δ) from the potential generating circuit 4 d is supplied to the other end of the transistor QN 8 , which is partly responsible for the control of the sense amplifier supply potential SAN.

Now, the operation of the magnetic memory device in FIG. 5 will be described with reference to FIG. 6 . FIG. 6 is a timing chart showing the potentials of essential parts of the magnetic memory device in FIG. 5 . The operations shown in FIG. 6 are similar to those shown in FIG. 4 . Accordingly, only the differences will be described. During standby, the signal SC 1 has the potential Vss. The signal SC 2 has the potential Vd. The signal SC 3 has the potential Vd. The signal SC 4 has the potential Vdown.

Upon a read, at a time T 2 , the signal ISO changes to the low level. Then, at time T 3 , the signal lines SC 1 and SC 4 rise to the potential Vd, the signal SC 2 lowers to the potential Vss, the signal SC 3 lower to the potential Vdown. As a result, the sense amplifier SA starts operation. One of the signals SN and /SN rises to the potential Vd, while the other lowers to the potential Vdown. Then, the transistors QN 9 and QN 10 in FIG. 5 are turned on (not shown). Thus, the signals SN and /SN are loaded onto the corresponding data lines. Subsequently, at a time T 4 , the signal SC 1 lowers to the potential Vss, The signal SC 2 rises to the potential Vd, yhe signal SC 3 rises to the potential Vd, the signal SC 4 lowers to the potential Vdown. Then, as in the case of the first embodiment, after a time T 5 , at a time T 6 , the device shifts to the standby state.

With the semiconductor memory device according to the second embodiment of the present invention, the sense amplifier SA uses the potential Vd and the overdriven potential Vdown to amplify the potentials on the signal lines SN and /SN. Thus, after amplification, the difference in potential between the signal lines SN and /SN is larger than the internal power potential Vd−ground potential Vss like in the first embodiment. Furthermore, as with the first embodiment, amplification is carried out after the memory cell MCs and the sense amplifier SA have been disconnected from each other. Thus, as in the case of the first embodiment, it is possible to enable a read operation with a high margin, while preventing the degradation or destruction of the MTJ element MTJ.

(Third Embodiment)

In a third embodiment, the memory cell connection control circuit 1 is not provided. However, the third embodiment is instead characterized by the manner of controlling the potential on the word line WL, in order to prevent a high voltage from being applied to the MTJ element MTJ.

FIG. 7 is a diagram showing the circuit configuration of a magnetic memory device according to the third embodiment of the present invention. As shown in FIG. 7 , the memory cell connection control circuit 1 is not provided on the bit lines BL and /BL between the sense amplifier SA and the memory cells MC. The sense amplifier SA and the memory cell MCs are connected all the time.

Now, the operation of the magnetic memory device in FIG. 7 will be described with reference to FIG. 8 . FIG. 8 is a timing chart showing the potentials of essential parts of the magnetic memory device in FIG. 7 . As shown in FIG. 8 , the state during standby is the same as that in the first embodiment. Upon a read, at a time T 1 , the signal PC changes to the low level, the potential on the word line WL connected to the selected cell changes to the high level, the signal SI changes to the low level. As a result, a read voltage is applied to the memory cells MC. The potentials on the bit lines BL and /BL increase or decrease depending on resistance values that in turn depend on the information in the MTJ elements connected to the bit lines BL and /BL. The sense amplifier does not start operation at that point.

After the time passes which is required to adequately change the potentials on the bit lines BL and /BL, the signal SI changes to the high level at a time T 3 . The word line WL changes to the low level. As a result, the selection transistor Q is turned off to float the memory cell MC. That is, no voltages are applied to the opposite ends of the MTJ element regardless of the changes in the potentials on the bit lines BL and /BL.

Then, at a time T 3 , the signals SC 2 and SC 3 lower to the potential Vss, the signal SC 1 rises to the potential Vup, and the signal SC 4 rises to the potential Vd. Thus, the sense amplifier SA starts operation. Accordingly, one of the bit lines BL and /BL rises to the potential Vup, while the other lowers to the potential Vss. Then, the potentials on the bit lines BL and /BL are loaded onto the corresponding data lines.

Then, at a time T 4 , signals SC 1 and SC 4 lower to the potential Vss, the signal SC 2 rises to the potential Vup, and The signal SC 3 rises to the potential Vd. As a result, the sense amplifier SA stops operation, and the signals SN and /SN change to the potential Vd/2.

Then, at a time T 5 , the signal PC changes to the high level. Thus, the bit lines BL and /BL are precharged to the potential Vd/2 to shift the device to the standby state.

With the magnetic memory device according to the third embodiment of the present invention, after information from the memory cell has been loaded onto the bit lines BL and /BL, the memory cell MC is floated. Then, sense amplification is carried out using the overdrive technique. Thus, even if the overdrive changes the potentials on the bit lines to values equal to or larger than Vd, it is possible to avoid applying a voltage to the opposite ends of the MTJ element MTJ. This makes it possible to enable a read operation with a high margin using the overdrive technique, while preventing the degradation or destruction of the MTJ element MTJ attributed to the application of a high voltage to the MTJ element MTJ.

(Fourth Embodiment)

According to a fourth embodiment, the sense amplifier supply potentials SAP and SAN vary as in the case of the second embodiment in the circuit configuration of the third embodiment.

FIG. 9 is a diagram showing the circuit configuration of essential parts of a magnetic memory device according to the fourth embodiment of the present invention. The circuit in FIG. 9 is similar to that in FIG. 7 . Accordingly, only the differences from FIG. 7 will be described below. As shown in FIG. 9 , the potential Vd from the potential generating circuit 4 b is supplied to the other end of the transistor QP 8 . The potential Vdown from the potential generating circuit 4 d is supplied to the other end of the transistor QN 8 .

Now, the operation of the magnetic memory device in FIG. 9 will be described with reference to FIG. 10 . FIG. 10 is a timing chart showing the potentials of essential parts of the magnetic memory device in FIG. 9 . The operations shown in FIG. 10 are similar to those shown in FIG. 8 . Accordingly, only the differences will be described. During standby, the signal SC 1 has the potential Vss. The signal SC 2 has the potential Vd. The signal SC 3 has the potential Vd. The signal SC 4 has the potential Vdown. Upon a read, at a time T 3 , the signal SI changes to the high level and the word line WL changes to the low level. Consequently, the memory cell MC is floated.

At a time T 3 , the signal lines SC 1 and SC 4 rise to the potential Vd, the signal SC 2 lowers to the potential Vss, and the signal SC 3 lower to the potential Vdown. Thus, the sense amplifier SA starts operation. Consequently, one of the bit lines BL and /BL rises to the potential Vd, while the other lowers to the potential Vdown. The potentials on the bit lines BL and /BL are loaded onto the corresponding data lines. Subsequently, at a time T 4 , the signal SC 1 lowers to the potential Vss, the signal SC 2 rises to the potential Vd, the signal SC 3 rises to the potential Vd, and the signal SC 4 lowers to the potential Vdown. Then, at a time T 5 , the device shifts to the standby state.

With the semiconductor memory device according to the fourth embodiment of the present invention, the sense amplifier SA uses the potential Vd and the overdriven potential Vdown to amplify the potentials on the bit lines BL and /BL. Thus, after amplification, the difference in potential between the bit lines BL and /BL is larger than the internal power potential Vd−ground potential Vss as in the case of the third embodiment. Furthermore, as with the third embodiment, amplification is carried out after the memory cell MC and the sense amplifier SA have been disconnected from each other. Thus, as in the case of the third embodiment, it is possible to enable a read operation with a high margin, while preventing the degradation or destruction of the MTJ element MTJ.

The first to fourth embodiments have been described with reference to the circuit configuration of the single bit line pair. However, as described in FIG. 1 , a plurality of memory cells MC are provided, and actually a large number of bit line pairs are provided in line along a word lines direction. In this case, for example, in accordance with an address signal, only the bit line pair connected to the target memory cell MC is precharged to Vd/2, with the remaining bit line pairs set at the potential Vss. Such control enables the operation of only the sense amplifier SA between the bit lines of the pair connected to the target memory cell MC.

FIG. 11 shows a circuit configuration with a plurality of bit line pairs provided. As shown in FIG. 11 , an arrangement similar to that shown in FIG. 2 is provided in each of two bit line pairs. The sense amplifier supply voltages SAP and SAN are supplied to all the bit lines. The connection node between the transistors QN 5 and QN 6 is connected to one end of an n-type MOS transistor QN 8 a and to one end of an n-type MOS transistor QN 8 b , respectively. The other end of the transistor QN 8 a is grounded, while the potential Vdown is supplied to the other end of the transistor QN 8 b . In this figure, the control section 2 and the potential generating circuits 4 a to 4 d are omitted. This circuit configuration corresponds to the first or second embodiment but may be similarly implemented in the third or fourth embodiment.

Moreover, in each embodiment, the sense amplifier SA overdrives either the potential Vd or the potential Vss for amplification. However, both potentials may be overdriven.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.