Double data rate synchronous dynamic random access memory semiconductor device

This application claims foreign priority under 35 U.S.C. § 119 to Korean Patent Application No. 2003-13423, filed on 4 Mar. 2003, in the Korean Intellectual Property Office.

1. Field of the Invention

The present invention relates to semiconductor memory devices, and more particularly, to semiconductor memory devices that prevent conflicts between data read from and data written to the devices.

2. Description of the Related Art

In general, a DDR SDRAM semiconductor device is connected to a DRAM controller. The DRAM controller writes data to and reads data from the DDR SDRAM semiconductor device. The DDR SDRAM semiconductor device includes a memory bank that stores data, a delay locked loop (“DLL”) circuit that generates a clock signal, an output buffer that buffers data stored in the memory bank and outputs the buffered data in synchronization with the clock signal, and an output controller that controls the operation of the output buffer.

FIG. 1 shows a timing diagram, indicated generally by the reference numeral 100 , describing a malfunction of a conventional DDR SDRAM semiconductor device when the DRAM controller writes data to the DDR SDRAM semiconductor device. Hereinafter, the reason for the malfunction will be described with reference to FIG. 1 .

Once the DRAM controller applies a read command RD to the DDR SDRAM semiconductor device and a CAS latency elapses, the output buffer outputs data DQR. At this time, the data DQR is output from the output buffer in synchronization with a clock signal CLK_DLL output from the DLL circuit.

The output controller receives the clock signal CLK_DLL and the read command RD. While receiving the clock signal CLK_DLL, the output controller activates the output buffer when the read command RD is active and deactivates the output buffer when the read command RD is inactive. This operation prevents unnecessary power consumption by the output buffer.

Once a precharge command PR is applied to the memory bank after the output buffer has output data DQR, the clock signal CLK_DLL is not output to the output controller any more. This state is maintained while the DLL circuit is reset and completes a locking operation on a signal input to the DLL circuit, i.e., during a period tD. At this time, the output controller should deactivate the output buffer because the read command RD is inactive. However, since the clock signal CLK_DLL has not been input to the output controller, the output controller may erroneously apply an active read command RD latched therein to the output buffer to activate the output buffer. Then, if data DQR generated in the DDR SDRAM semiconductor device is input to the output buffer, the output buffer outputs data DQR to the DRAM controller without receiving the read command RD.

Thereafter, when a write command WR becomes active, and thus, the DRAM controller writes data DQW to the DDR SDRAM semiconductor device, a conflict occurs between data DQW written to the DDR SDRAM semiconductor device and data DQR output from the DDR SDRAM semiconductor device. Such a conflict causes malfunction of the DDR SDRAM semiconductor device.

These and other drawbacks and disadvantages of the prior art are addressed by a semiconductor memory device that prevents a conflict between data read from the device and data written to the device.

A semiconductor memory device includes a delay locked loop (“DLL”) circuit for receiving an input clock signal and generating a deskewed output clock signal, an output unit for buffering data stored within the semiconductor memory device and outputting the data, and an output control unit in signal communication with the DLL circuit and the output unit for deactivating the output unit when the DLL circuit performs a locking operation on the input clock signal.

These and other aspects, features and advantages of the present disclosure will become apparent from the following description of exemplary embodiments, which is to be read in connection with the accompanying drawings.

The above and other aspects and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

FIG. 1 is a timing diagram describing a malfunction of a conventional DDR SDRAM semiconductor device when data is written to the DDR SDRAM semiconductor device;

FIG. 2 is a block diagram illustrating a DDR SDRAM semiconductor device according to an embodiment of the present invention;

FIG. 3 is a circuit diagram illustrating an output control unit of FIG. 2 ; and

FIG. 4 is a timing diagram for signals of FIG. 2 .

The present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. In the drawings, the same reference numerals have been used, where possible, to designate the same elements.

FIG. 2 shows a block diagram illustrating a double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) semiconductor device according to the present invention. Referring to FIG. 2 , a DDR SDRAM semiconductor device 201 includes a delay locked loop (“DLL”) circuit 211 , a clock signal control unit 221 , an output control unit 241 , and an output unit 231 .

The DLL circuit 211 compensates for skew of an input clock signal ECLK and generates an output clock signal DCLK. The clock signal control unit 221 includes a first logic unit 223 and a second logic unit 225 .

The first logic unit 223 receives a read signal RD and a DLL locking signal PDLLON. When either the read signal RD or the DLL locking signal PDLLON is active, the first logic unit 223 activates its output signal. When both the read signal RD and the DLL locking signal PDLLON are inactive, the first logic unit 223 deactivates its output signal. The read signal RD becomes active when data stored in the DDR SDRAM semiconductor device 201 is read out. The DLL locking signal PDLLON becomes active when the DLL circuit 211 is reset and performs a locking operation on the input clock signal ECLK. The first logic unit 223 may be an OR gate.

The second logic unit 225 receives the output signal of the first logic unit 223 and the output clock signal DLCK of the DLL circuit 211 . When the output signal of the first logic unit 223 is active, the second logic unit 225 outputs a clock signal CLK_DLL. When the output signal of the first logic unit 223 is inactive, the second logic unit 225 does not output the clock signal CLK_DLL. The second logic unit 225 may be an AND gate.

The output control unit 241 receives the read signal RD and the clock signal CLK_DLL output from the second logic unit 225 and outputs the read signal RD as a control signal P 1 to the output unit 231 in synchronization with the received clock signal CLK_DLL. The output control unit 241 will be further discussed with reference to FIG. 3 .

The output unit 231 receives data DQi stored in the DDR SDRAM semiconductor device, the clock signal CLK_DLL output from the second logic unit 225 , and the control signal P 1 output from the output control unit 241 . The output unit 231 is activated when the control signal P 1 becomes active. When the control signal P 1 becomes inactive, the output unit 231 is deactivated. Thus, when the control signal P 1 is active, the output unit 231 buffers and outputs data DQi stored in the DDR SDRAM semiconductor device 201 as data DQ, in synchronization with the clock signal CLK_DLL output from the second logic unit 225 . When the control signal P 1 is inactive, the output unit 231 does not output data DQ.

When signals DCLK, CLK_DLL, RD, and PDLLON are active, they are logic high, and when they are inactive, they are logic low. However, in an alternative embodiment, the relationship between the signals and their logic states may be reversed.

FIG. 3 shows a circuit diagram illustrating the output control unit 241 of FIG. 2 . Referring to FIG. 3 , the output control unit 241 includes a plurality of latch circuits 311 , 312 , 313 and 314 , and a plurality of transmission gates 321 , 322 , 323 and 324 .

The transmission gates 321 , 322 , 323 and 324 receive the clock signal CLK_DLL output from the second logic unit 225 of FIG. 2 . When the clock signal CLK_DLL is logic high, the transmission gates 321 , 322 , 323 and 324 are activated and output the received read signal RD. When the clock signal CLK_DLL is logic low, the transmission gates 321 , 322 , 323 , and 324 are deactivated and do not output the received read signal RD.

The latch circuits 311 , 312 , 313 and 314 latch and output the received read signal RD. During the input of the clock signal CLK_DLL, the received read signal RD passes through the latch circuits 311 , 312 , 313 and 314 , and is output as the control signal P 1 . As will be recognized by those of ordinary skill in the pertinent art, the number of latch circuits and transmission gates is subject to change with the configuration of the output control unit 241 .

FIG. 4 shows a timing diagram, indicated generally by the reference numeral 400 , for signals DCLK, CLK_DLL, RD and PDLLON, all of FIG. 2 . Hereinafter, the DDR SDRAM semiconductor device 201 of FIG. 2 will be described with reference to FIG. 4 .

When data DQi stored in the DDR SDRAM semiconductor device 201 is read out, the read signal RD input to the first logic unit 223 and the output control unit 241 , is activated, and the output clock signal DLCK is output from the DLL circuit 211 . Then, the clock signal CLK_DLL is output from the second logic unit 225 and applied to the output unit 231 and the output control unit 241 . When the control signal P 1 output from the output control unit 241 becomes active, the output unit 231 is activated and outputs data DQ to the outside of the DDR SDRAM semiconductor device 201 .

Once a data read operation has been completed, the read signal RD becomes inactive and is input to the DLL circuit 211 . Then, the DLL circuit 211 is reset and performs the locking operation on the input clock signal ECLK. During the locking operation, the DLL locking signal PDLLON becomes active, i.e., logic high. As a result, the first logic unit 223 outputs a high signal to the second logic unit 225 and the second logic unit 225 outputs the clock signal CLK_DLL. Then, the output control unit 241 outputs the inactive control signal P 1 in synchronization with the clock signal CLK_DLL output from the second logic unit 225 . Since the control signal P 1 output from the output control unit 241 is inactive, i.e., logic low, the output unit 231 is deactivated and does not output data DQ.

Here, since the DLL SDRAM semiconductor device 201 deactivates the output unit 231 while the DLL circuit 211 is reset and performs the locking operation, when data is written to the DR SDRAM semiconductor device 201 from outside, the output unit 231 cannot output any data. Therefore, when data is written to the DDR SDRAM semiconductor 201 , no conflict occurs between data read from and written to the DDR SDRAM semiconductor device 201 .

As described above, since no conflict occurs between the data read from and the data written to the DDR SDRAM semiconductor device according to the present invention, when data is written thereto, the DDR SDRAM semiconductor device does not exhibit the conventional malfunction during the data write operation.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the pertinent art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.