Inventor
Kyu-hyoun Kim
Inventor
Mount Kisco, NY, US
Overview
Patents· 174 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores36%
G06FElectric digital data processing25%
H03KPulse technique10%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
H03MCoding4%
H04LTransmission of digital information, e.g. telegraphic communication3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
H01LSemiconductor devices1%
H10DInorganic electric semiconductor devices1%
PatentTitleYear
10,838,851Multi-dimensional accesses in memory202010,671,497Efficient and selective sparing of bits in memory systems202010,606,713Using dual channel memory as single channel memory with command address recovery202010,606,692Error correction potency improvement via added burst beats in a dram access cycle202010,585,672Memory device command-address-control calibration202010,546,628Using dual channel memory as single channel memory with spares202010,468,088Redundant voltage regulator for memory devices201910,353,455Power management in multi-channel 3D stacked DRAM201910,338,815Multi-channel nonvolatile memory power loss management201910,281,974Power management in multi-channel 3D stacked DRAM201910,255,986Assessing in-field reliability of computer memories201910,168,922Volatile and non-volatile memory in a TSV module201910,168,905Multi-channel nonvolatile memory power loss management201910,168,923Coherency management for volatile and non-volatile memory in a through-silicon via (TSV) module201910,102,884Distributed serialized data buffer and a memory module for a cascadable and extended memory subsystem201810,067,702Memory system with switchable operating bands201810,063,263Extended error correction coding data storage201810,042,726Data buffer spare architectures for dual channel serial interface memories201810,032,505Dynamic random access memory with pseudo differential sensing201810,027,349Extended error correction coding data storage201810,025,508Concurrent upgrade and backup of non-volatile memory201810,019,312Error monitoring of a memory device containing embedded error correction20189,965,017System and method for conserving energy in non-volatile dual inline memory modules20189,940,457Detecting a cryogenic attack on a memory device with embedded error correction20189,917,601'Adaptive error correction in a memory system'20189,912,324'Open-loop quadrature clock corrector and generator'20189,904,611'Data buffer spare architectures for dual channel serial interface memories'20189,898,218'Memory system with switchable operating bands'20189,886,200'Concurrent upgrade and backup of non-volatile memory'20189,880,896'Error feedback and logging with memory on-chip error checking and correcting (ECC)'20189,875,036Concurrent upgrade and backup of non-volatile memory20189,760,504'Nonvolatile memory data security'20179,747,148'Error monitoring of a memory device containing embedded error correction'20179,733,870'Error vector readout from a memory device'20179,734,008'Error vector readout from a memory device'20179,734,095'Nonvolatile memory data security'20179,690,649'Memory device error history bit'20179,684,555'Selective memory error reporting'20179,626,242'Memory device error history bit'20179,606,851'Error monitoring of a memory device containing embedded error correction'20179,552,869'Random access memory with pseudo-differential sensing'20179,529,543'Concurrent upgrade and backup of non-volatile memory'20169,495,242'Adaptive error correction in a memory system'20169,471,423'Selective memory error reporting'20169,471,422'Adaptive error correction in a memory system'20169,459,672'Capacitance management'20169,454,422'Error feedback and logging with memory on-chip error checking and correcting (ECC)'20169,442,512'Interface clock frequency switching using a computed insertion delay'20169,436,563'Memory system for mirroring data'20169,430,344'Memory system for mirroring data'20169,418,722'Prioritizing refreshes in a memory device'20169,389,974'Data retrieval from stacked computer memory'20169,389,972'Data retrieval from stacked computer memory'20169,349,432'Reference voltage modification in a memory device'20169,298,395'Memory system connector'20169,250,815'DRAM controller for variable refresh operation timing'20169,251,894'Accessing a resistive memory storage device'20169,245,604'Prioritizing refreshes in a memory device'20169,245,619'Memory device with memory buffer for premature read protection'20169,224,450'Reference voltage modification in a memory device'20159,196,347'DRAM controller for variable refresh operation timing'20159,189,327'Error-correcting code distribution for memory systems'20159,159,410'Accessing a resistive memory storage device'20159,146,883'Securing the contents of a memory device'20159,146,882'Securing the contents of a memory device'20159,087,612'DRAM error detection, evaluation, and correction'20159,076,770'Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same'20159,064,602'Implementing memory device with sub-bank architecture'20159,058,896'DRAM refresh'20159,053,811'Memory device refresh'20159,037,930'Managing errors in a DRAM by weak cell encoding'20159,001,609'Hybrid latch and fuse scheme for memory repair'20158,995,217'Hybrid latch and fuse scheme for memory repair'20158,909,878'Implementing timing alignment and synchronized memory activities of multiple memory devices accessed in parallel'20148,898,544'DRAM error detection, evaluation, and correction'20148,890,316'Implementing decoupling devices inside a TSV DRAM stack'20148,887,014'Managing errors in a DRAM by weak cell encoding'20148,856,579'Memory interface having extended strobe burst for read timing calibration'20148,848,471'Method for optimizing refresh rate for DRAM'20148,824,573'Digital phase detector with zero phase offset'20148,823,162'Integrated circuit die stacks with translationally compatible vias'20148,816,490'Integrated circuit die stacks with rotationally symmetric VIAS'20148,799,566'Memory system with a programmable refresh cycle'20148,797,823'Implementing SDRAM having no RAS to CAS delay in write operation'20148,780,578'Integrated circuit die stacks having initially identical dies personalized with switches'20148,756,475'Method of detecting error in a semiconductor memory device'20148,718,216'Digital phase detector with zero phase offset'20148,697,567'Implementing decoupling devices inside a TSV DRAM stack'20148,659,959'Advanced memory device having improved performance, reduced power and increased reliability'20148,644,085'Duty cycle distortion correction'20148,639,874'Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device'20148,635,487'Memory interface having extended strobe burst for write timing calibration'20148,543,753'Multi-use physical architecture'20138,516,409'Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device'20138,493,801'Strobe offset in bidirectional memory strobe configurations'20138,452,919'Advanced memory device having improved performance, reduced power and increased reliability'20138,432,027'Integrated circuit die stacks with rotationally symmetric vias'20138,379,459'Memory system with delay locked loop (DLL) bypass control'20138,359,521'Providing a memory device having a shared error feedback pin'20138,343,804'Implementing multiple different types of dies for memory stacking'20138,315,068'Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same'20128,310,841'Integrated circuit die stacks having initially identical dies personalized with switches and methods of making the same'20128,307,270'Advanced memory device having improved performance, reduced power and increased reliability'20128,289,798'Voltage regulator bypass in memory device'20128,284,621'Strobe offset in bidirectional memory strobe configurations'20128,258,619'Integrated circuit die stacks with translationally compatible vias'20128,253,478'Internal voltage generating circuit for semiconductor device'20128,255,783'Apparatus, system and method for providing error protection for data-masking bits'20128,093,075'Semiconductor integrated circuit including a power supply, semiconductor system including a semiconductor integrated circuit, and method of forming a semiconductor integrated circuit'20128,055,976'System and method for providing error correction and detection in a memory system'20118,023,358'System and method for providing a non-power-of-two burst length in a memory system'20118,004,335'Phase interpolator system and associated methods'20117,952,944'System for providing on-die termination of a control signal bus'20117,948,817'Advanced memory device having reduced power and improved performance'20117,948,272'Input buffer for detecting an input signal'20117,882,417'Semiconductor memory device and memory system including the same'20117,778,042'Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices'20107,683,725'System for generating a multiple phase clock'20107,675,158'Semiconductor integrated circuit including a power supply, and semiconductor system including a semiconductor integrated circuit'20107,636,262'Synchronous memory having shared CRC and strobe pin'20097,626,422'Output driver and method thereof'20097,612,621'System for providing open-loop quadrature clock generation'20097,598,762'Semiconductor driver circuit with signal swing balance and enhanced testing'20097,593,288'System for providing read clock sharing between memory devices'20097,573,932'Spread spectrum clock generator'20097,567,106'Duty cycle correction circuit, clock generation circuits, semiconductor devices using the same, and method for generating clock signal'20097,528,668'Differential amplifier, differential amplifying method, and phase locked loop and delay locked loop using the same'20097,522,440'Data input and data output control device and method'20097,518,539'Concurrent correlated double sampling and analog-to-digital conversion'20097,439,772'Level shifting circuit and method reducing leakage current'20087,420,870'Phase locked loop circuit and method of locking a phase'20087,417,902'Input circuit for a memory device, and a memory device and memory system employing the input circuit'20087,405,949'Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices'20087,375,564'Time delay compensation circuit comprising delay cells having various unit time delays'20087,336,554'Semiconductor memory device having a reduced number of pins'20087,269,078'Buffer circuit and memory system for selectively outputting data strobe signal according to number of data bits'20077,212,052'Jitter suppressing delay locked loop circuits and related methods'20077,199,630'Delay locked loops and methods using ring oscillators'20077,199,634'Duty cycle correction circuits suitable for use in delay-locked loops and methods of correcting duty cycles of periodic signals'20077,190,206'Interface circuit and signal clamping circuit using level-down shifter'20077,184,509'Delay locked loop circuit for internally correcting duty cycle and duty cycle correction method thereof'20077,135,935'Hyper-ring oscillator'20067,133,318'Output driver capable of controlling slew rate of output signal according to operating frequency information or CAS latency information'20067,123,520'Buffer circuit and memory system for selectively outputting data strobe signal according to number of data bits'20067,091,741'Input buffer capable of reducing input capacitance seen by input signal'20067,085,336'Signal transmission circuit and method for equalizing disparate delay times dynamically, and data latch circuit of semiconductor device implementing the same'20067,057,433'Delay-Locked Loop (DLL) capable of directly receiving external clock signals'20067,038,972'Double data rate synchronous dynamic random access memory semiconductor device'20067,035,148'Output driver capable of controlling slew rate of output signal according to operating frequency information or CAS latency information'20067,015,739'Integrated circuit devices having duty cycle correction circuits that receive control signals over first and second separate paths and methods of operating the same'20066,999,375'Synchronous semiconductor device and method of preventing coupling between data buses'20066,980,036'Semiconductor device comprising frequency multiplier of external clock and output buffer of test data and semiconductor test method'20056,954,094'Semiconductor memory device having partially controlled delay locked loop'20056,934,215'Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device'20056,870,776'Data output circuit in combined SDR/DDR semiconductor memory device'20056,853,317'Circuit and method for generating mode register set code'20056,847,559'Input buffer circuit of a synchronous semiconductor memory device'20056,812,765'Pulsed signal transition delay adjusting circuit'20046,734,707'Data input circuit for reducing loading difference between fetch signal and multiple data in semiconductor device'20046,704,228'Semiconductor memory device post-repair circuit and method'20046,693,842'Semiconductor device having a plurality of output signals'20046,639,868'SDRAM having data latch circuit for outputting input data in synchronization with a plurality of control signals'20036,590,421'Semiconductor device and method of outputting data therein'20036,590,434'Delay time controlling circuit and method for controlling delay time'20036,535,051'Charge pump circuit'20036,486,719'Flip-flop circuits having digital-to-time conversion latches therein'20026,466,071'Methods and circuits for correcting a duty-cycle of a signal'20026,459,314'Delay locked loop circuit having duty cycle correction function and delay locking method'20026,452,432'Signal processing circuits having a pair of delay locked loop (DLL) circuits for adjusting a duty-cycle of a periodic digital signal and methods of operating same'20026,414,517'Input buffer circuits with input signal boost capability and methods of operation thereof'20026,388,485'Delay-locked loop circuit having master-slave structure'20026,366,148'Delay locked loop circuit and method for generating internal clock signal'20026,359,481'Data synchronization circuit'20026,327,190'Complementary differential input buffer for a semiconductor memory device'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2014Patents assigned to SAMSUNG ELECTRONICS CO LTD (57)· patent assignee history
2002–2014Based in Suwon-si, KR· patent location history
2002–2007Based in Kyungki-do, KR· patent location history
2006–2011Based in Gyeonggi-do, KR· patent location history
2009–2020Patents assigned to IBM (112)· patent assignee history
2009–2018Based in Mount Kisco, NY, US· patent location history
2012–2015Patents assigned to KIM KYU-HYOUN (33)· patent assignee history
2012–2015Patents assigned to COTEUS PAUL W (9)· patent assignee history
2012–2014Patents assigned to GOWER KEVIN C (9)· patent assignee history
2016–2020Based in Chappaqua, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 112 | 2009–2020 |
| SAMSUNG ELECTRONICS CO LTD | 57 | 2001–2014 |
| KIM KYU-HYOUNself | 33 | 2012–2015 |
| COTEUS PAUL W | 9 | 2012–2015 |
| GOWER KEVIN C | 9 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Mount Kisco, New York, US | 64 | 2009–2018 |
| Chappaqua, New York, US | 44 | 2016–2020 |
| Suwon-si, KR | 36 | 2002–2014 |
| Kyungki-do, KR | 12 | 2002–2007 |
| Gyeonggi-do, KR | 10 | 2006–2011 |