Circuit to linearize gain of a voltage controlled oscillator over wide frequency range

The present application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/447,569, which was filed on Feb. 14, 2003, of common inventorship. owner-ship and title, and is hereby incorporated by reference.

1. Field of the Invention

The present invention relates to voltage controlled oscillators (VCO's), and more particularly to linearizing gain (frequency out/voltage) of VCO's over a wide frequency range.

2. Background Information

VCO's are commonly used in many applications, especially in communication and control applications. Virtually all phase-locked-loop (PLL) circuits employ a VCO in the control loop. FIG. 1 is a block diagram of such a phase-locked-loop circuit. A phase and frequency detector 2 compares an input reference or clock signal 4 to a feedback signal 6 that is a frequency divided VCO output signal 8 . The phase-frequency detector 2 provides an UP or DOWN error signal into a charge pump 10 that together with a Loop filter 12 generates a control voltage Vcnt 14 . A Loop Buffer 16 and a VCO 18 complete the loop to the VCO output signal 8 . The feedback signal 6 is derived from signal 8 , typically (but not necessarily) by dividing the signal as shown. As is well known in such systems the feed back loop operates to reduce the differences between the clock signal 4 and the divided signal 6 . Not shown, but often found in such circuits, are analog to digital converters that may form parts of the PLL loop. In such cases the operations described in any one block of FIG. 1 are carried out digitally as is well known in the art.

Most VCO's used in a PLL and elsewhere strive to operate over a wide frequency range. One primary aspect determining that frequency range is the linearity of the VCO's gain. Non-linearities tend to increase phase offsets between the input and looped back signal and change the loop gain which may lead to “overshooting” and other stability issues. This in turn leads to compromising the loop filter parameters, which leads to limiting the operating frequency range of the PLL. Other negative effects of non-linearities may include increased noise, increased acquisition times, and/or frequency jitter.

FIG. 2 is a common delay string of five pulse delay elements, t 1 –t 5 , that wraps around to create an oscillator circuit. A control signal, Vcnt, is fed to each delay element to change the delay of each element and thus the frequency of the circuit. This type of oscillator is found in the prior art and may be used in a preferred embodiment of the present invention. FIG. 3 diagrams a five stage oscillator where the output of the last delay circuit, t 5 , loops back to the input of the first delay circuit, t 1 . A phase reversal is incorporated into the loop to cause oscillations. In such a circuit the delay, T, of each circuit is added to get the period P of the oscillator, and inverting the period yields the frequency. If each circuit delay is equal, the resulting frequency is an inverse function of one circuit delay, or Fosc=K 1 (1/T). The power on reset, POR, allows the oscillation to start.

FIG. 4 shows the optimal relationship for a VCO where the frequency out is a straight line function of a control voltage in with a slope of K 2 . The relationship as applied to a VCO with an input control voltage, Vcnt, is:

Fosc=K 2 ( Vcnt ) plus some offset  Eq. 1

The following discussion drops the offset and considers the relationship to pass through the origin for simplicity. However, as will be understood by those skilled in the art, there is no loss in the general applicability of the following discussion.

The effort to linearly extend this line has been an ongoing objective in the art and is an objective of the present invention.

It is well known in the art to use a current source to charge a capacitor to create a delay circuit suitable for use in a delay type oscillator described above. The well known relation ship of a current I charging a capacitor C is:

I=C ( dv/dt )  Eq. 2.

The delay, T, of one delay circuit, will be a function of the time it takes the voltage on the charging capacitance to reach some circuit determined threshold level, V 1 . V 1 is considered for this discussion to start from a complete discharge or zero volts. Again there will be some small residual voltage, that will not affect the general applicability of the present invention as understood by those skilled in the art. So the dv/dt can be written as V 1 /T, and Eq. 2 becomes

I=C ( V 1 / T ). Rearranging yields:

1 /T= ( I/CV 1 )  Eq. 3, and

T= ( CV 1 / I )

So, the delay of one circuit is CV 1 , and the frequency of the delay circuit will be a constant equal to the number of delay circuit stages times 1/T, or

Fosc=K 1 (1 /T )= K 1 ( I/CV 1 ).

As discussed below the current, I, of Eq. 3 is shown to be a function of the square of Vcnt (Vcnt^2) for a specific design, and so, as discussed above, the frequency of the sequential delay circuit oscillator will be:

Fosc= ( K 3 / CV 1 ) Vcnt^ 2  Eq. 4

As discussed below, V 1 is a function of Vcnt, and C is a constant along with K 3 , resulting in:

Fosc= ( K 3 / C )( Vcnt ^2 /Vcnt )  Eq. 5, or

Fosc=K 2 ( Vcnt ),  Eq. 6,

which is a relationship oF interest as discussed below.

FIG. 5 is a copy of item 22 from U.S. Pat. No. 5,748,048 to Moyal (Moyal), and assigned to Cypress Semiconductor Corp. Moyal and FIG. 6 completes a partial schematic showing a single delay stage of charging of the capacitor C that illustrates the square law relationship. In FIG. 5 , P 3 and N 2 are operated as FET diode clamps. A FET diode clamp is a FET that operates in the saturation region where the drain current is approximately related to the square of the gate to source voltage. Here the current I 1 is proportional to the square of the Vcnt (less threshold voltages). Current I 1 ′ mirrors I 1 , and, following FIG. 6 , I 1 ″ mirrors I 1 ′ (although with current mirrors there may be a factor due to channel size involved). The delay of I 1 ″ charging capacitor C is inversely related to I 1 ,″ as is well known. As applied to the analysis above, from FIG. 5 and Eq. 4, Vcnt will be related to the root of I 1 and therefor to maintain the linearity of FIG. 4 . The V 1 of Eq. 4 will also be related to the square root of I, therefore canceling each other out of Eq. 4 as shown above in Eq. 5.

It is clear that linear frequency range shown in FIG. 4 depends on the square law relationship discussed above. Moreover, to extend the linear relationship of FIG. 4 , the square law relationship, Vcnt to I 1 , of FIG. 5 and Eq. 4, must be correspondingly extended.

In the circuit of FIG. 5 , since P 3 and N 2 are FETS built simultaneously with N 1 , P 1 and the other FETS, process variations from chip to chip or batch to batch will correlate among the FETs. For example the temperature coefficients, TC's (usually positive) will track and at higher temperature larger FET threshold voltages, Vt's, will act to restrict the operating range of the circuit. In this case “threshold” refers to the gate voltage necessary to drive a given drain current, not the threshold that begins to turn on an FET. Moreover, if the fabricating process produces slow FET's, all will be slow and may affect the high frequency range of the VCO. Also, as the Vcnt goes low, the threshold of the FET's become a factor and the square law relationship may not hold. In such a case the linearity of the VCO will deteriorate causing problems discussed above.

The present invention addresses these limitations.

In view of the foregoing background discussion, the present invention provides a voltage controlled oscillator (VCO) with an extended linear range and improved temperature and processing compensation.

Ideally the input control signal for a VCO changes the frequency of the VCO in a linear manner over as wide a range as possible, and that frequency remains stable for changes in temperature and processing. In the present invention the control voltage is input to the gate of a first FET, preferably an N type MOSFET, that outputs current. The source of the first FET connects to a resistor in parallel with a diode connected bipolar transistor. The use of bipolar devices acts to compensate for temperature and for processing effects, and provide an exponential response as described below. The drain of the first FET is connected to the drain of a second FET, preferably to a diode connected P type MOSFET, that carries the drain current from the first FET. The current through this second FET controls the output signal frequency. However, until the input control signal FET overcomes its threshold voltage, there will be no current through the first FET, and so none through the second FET. In such an instance the VCO would not function. The present invention provides a diode connected third FET, preferably an N type MOSFET, that draws current through the drain of the second FET and therefore current is drawn through the second FET even when there is no current through the first FET. This extends the operating range of the VCO. Moreover, the current drawn by the third FET follows the same relationship as the current that would have been provided by the first FET if the threshold voltage were not present. This has the beneficial result of extending the linear range of the VCO.

In preferred embodiment, a diode connected bipolar PNP is placed parallel to the bipolar diode connected NPN. A fourth diode connected FET is placed in series with the third diode connected FET, and another P type FET is connected to mirror the current through the first P type FET. The current through the first P type FET and the mirror current, in a preferred embodiment are used in tandem to control the delay feedback of a preferred VCO circuit.

It will be appreciated by those skilled in the art that although the following Detailed Description will proceed with reference being made to illustrative embodiments, the drawings, and methods of use, the present invention is not intended to be limited to these embodiments and methods of use. Rather, the present invention is of broad scope and is intended to be defined as only set forth in the accompanying claims.

The invention description below refers to the accompanying drawings, of which:

FIG. 1 is a block diagram of a phase locked loop;

FIG. 2 is a block diagram of a delay looped back oscillator;

FIG. 3 is. Is a timing diagram of the delay loop of FIG. 2 ;

FIG. 4 is a graph of frequency versus a control voltage;

FIG. 5 is a copy of a circuit from a prior art patent(Moyal);

FIG. 6 is a partial circuit diagram showing the charing of a capacitor;

FIG. 7 ios a block/circuit diagram of a phase locked loop including an embodiment of the present invention,

FIG. 8 is a circuit diagram of a differential single delay circuit using charging of a capacitor;

FIG. 9 is a circuit diagram of an embodiment of the present invention,

FIGS. 10 and 11 are graphs of current versus control inputs.

FIG. 7 shows a VCO in a PLL implementing a preferred embodiment of the present invention. The block circuit diagram is a version of FIG. 1 and but implements a loop buffer that distinguishes and improves upon prior art. The VCO 20 is a five stage ring delay oscillator with the control voltages Vp and Vn being fed to each stage in parallel in a manner similar (albeit a single input) to Vcnt of FIG. 2 .

One such delay stage, a differential delay circuit, is shown in FIG. 8 . Vp is fed to the gates of P 21 and P 22 which are current mirrors of the drain current I 10 of N 10 ( FIG. 7 ). P 20 and P 23 are FET diode clamps. The FET diode connection N 13 of FIG. 7 drain, Vn, connects to the gate of N 23 of FIG. 8 . Here the current through N 13 , I 10 ,′ is mirrored as I 10 ″ in N 23 . The current I 10 ″ will split between N 20 and N 21 depending on the difference between the voltage INP and INM, respectively. Current from the common drain connections 80 and 81 , minus the split currents due to I 10 ″, charge the delay capacitors C 1 and C 2 , respectively. Design and operation of the differential delay circuit of FIG. 8 , from the schematic of FIG. 8 , is within the capability of those practiced in the art. The delayed outputs OUTP and OUTM are fed to succeeding stages (shown as blocks, 82 , 83 , respectively) and from the last stage the corresponding out signals are connected with the needed inversion to the first stage inputs thereby completing the delay loop. The delayed OUTP is connected to INP input and the delay OUTM to the INM input. As well known, the feed back loop is arranged so that the loop feed back is out of phase with enough gain to create an oscillation. The frequency of oscillation is a function of the delay which is a function of the currents charging the capacitors. Implementing such circuits is well within the skill of ordinary practitioners in the field. Lastly, with respect to FIG. 8 , the power on reset, POR, allows the operation of the VCO to start.

FIG. 9 isolates the loop buffer of FIG. 7 . The source of N 10 is fed to a resistor R 1 and to R 2 and R 3 that each lead to bipolar transistors T 1 and T 2 connected as base-emitter diodes. As is well known, diodes use of emitter resistors produce a diode current-voltage curve that demonstrates a close approximation to the desired square law relationship (similar to the FET diode). An advantage as compared to Moyal, however, is that the base emitter diodes exhibit a negative temperature coefficient as compared to the FET connected diodes. Another advantage is that the bipolar transistors will not track the FET's if the process happens to be producing slow FETs.

When Vcnt drops towards the voltage threshold of N 10 plus the base emitter drops of T 1 or T 2 , the operation of the square law current will diminish as N 10 nears a turning off threshold. Referring to the graph of FIG. 4 location L, the linearity of the frequency vs. Vcnt will diminish. At this point, as the voltage at Vp rises, the square law diode connected FET's N 11 and N 12 will draw current I 20 through P 10 and maintain the square law relationship with respect to Vp into the L region of FIG. 4 . Alternatively as Vcnt rises the currents from N 11 and N 12 will be reduce as the voltage across N 11 and N 12 are reduced.

FIG. 10 shows the currents of FIG. 9 without N 11 and N 12 , and FIG. 11 , shows the currents with N 11 and N 12 . In FIG. 10 the current through P 10 (IP 10 on graph) is equal to I 10 through N 10 . Also, note that when Vcnt lowers to VT, there is no current through P 10 . The current through R 1 contributs some linear current when the VT of N 10 is reached, but the voltages of the source of N 10 must rise above the base-emitter thresholds before current is drawing through T 1 and T 2 . This represents the L area of FIG. 4 . But, in FIG. 11 , N 11 and N 12 provide current through P 10 allowing for a linear extension of the relationship of FIG. 4 into the L area. From FIG. 11 , note the IP 10 current flows 100 below when Vcnt reaches Vt. This shows the extension of operation in the L area of FIG. 4 .

For large currents used at high frequency operation, the bipolar devices create a greater than square-law current. That is the bipolar current is exponentially related to the applied voltage, although in a preferred embodiment the use of emitter resistors tend to linearize this relationship. This acts to linearize the VCO circuit gain once current to voltage relationship moves from exponential to linear, as shown in FIGS. 10 and 11 .

It should be understood that above-described embodiments are being presented herein as examples and that many variations and alternatives thereof are possible. Accordingly, the present invention should be viewed broadly as being defined only as set forth in the hereinafter appended claims.