Inventor
Ronald B. Hulfachor
Inventor
Nashua, NH, US
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Lprimary
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses23%
H10DInorganic electric semiconductor devices23%
H03KPulse technique15%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems8%
G01RMeasuring electric variables4%
G05FSystems for regulating electric or magnetic variables4%
G06FElectric digital data processing4%
H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements which operate in a non-switching manner4%
H03MCoding4%
H04LTransmission of digital information, e.g. telegraphic communication4%
PatentTitleYear
10,770,983Circuits and methods for secondary-side rectified voltage sensing in isolated switched-mode power converters20208,558,524'Master/slave power supply switch driver circuitry'20138,476,939'Switching power supply gate driver'20138,412,923'Multi-mode pin usage in a power supply control integrated circuit'20137,443,250'Programmable phase-locked loop responsive to a selected bandwidth and a selected reference clock signal frequency to adjust circuit characteristics'20087,405,628'Technique for switching between input clocks in a phase-locked loop'20087,348,818'Tunable high-speed frequency divider'20087,079,369'Active power/ground ESD trigger'20067,030,669'Circuit to linearize gain of a voltage controlled oscillator over wide frequency range'20066,940,356'Circuitry to reduce PLL lock acquisition time'20056,927,460'Method and structure for BiCMOS isolated NMOS transistor'20056,894,553'Capacitively coupled current boost circuitry for integrated voltage regulator'20056,855,964'Triggering of an ESD NMOS through the use of an N-type buried layer'20056,794,945'PLL for clock recovery with initialization sequence'20046,261,932'Method of fabricating Schottky diode and related structure'20016,117,717'Method for after gate implant of threshold adjust with low impact on gate oxide integrity'20006,100,125'LDD structure for ESD protection and method of fabrication'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2006Patents assigned to FAIRCHILD SEMICONDUCTOR (9)· patent assignee history
2000–2001Based in Standish, ME, US· patent location history
2004–2020Based in Nashua, NH, US· patent location history
2005Based in Cape Elizabeth, ME, US· patent location history
2008Patents assigned to SILICON LAB INC (3)· patent assignee history
2013Patents assigned to INT RECTIFIER CORP (3)· patent assignee history
2013Patents assigned to CARROLL ROBERT T (2)· patent assignee history
2013Patents assigned to HULFACHOR RONALD B (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FAIRCHILD SEMICONDUCTOR | 9 | 2000–2006 |
| INT RECTIFIER CORP | 3 | 2013 |
| SILICON LAB INC | 3 | 2008 |
| CARROLL ROBERT T | 2 | 2013 |
| HULFACHOR RONALD Bself | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Nashua, NH, US | 11 | 2004–2020 |
| Cape Elizabeth, ME, US | 3 | 2005 |
| Standish, ME, US | 3 | 2000–2001 |