Semiconductor device having ECC circuit

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-308839, filed Sep. 1, 2003, the entire contents of which are incorporated herein by reference.

1. Field of the Invention

This invention relates to a semiconductor device and more particularly to a semiconductor device having an ECC circuit which corrects an error in output data from a memory.

2. Description of the Related Art

The operation speed of semiconductor devices is enhanced more and more and the integration density of elements of the devices is also extremely enhanced with the development of the semiconductor device technology. As a result, an influence by not only the degradation-fault but also the delay-fault as the fault mode of the device increases and a serious problem occurs. Therefore, the actual speed test, that is, at-speed test in the initial stage of the device manufacturing process becomes important. Particularly, a memory in the chip acts as a critical path of the whole chip in many cases, and therefore, a self-test circuit called a BIST (Built-In-Self Test) circuit is mounted on the chip and the at-speed test for the memory is made in the wafer stage.

The capacity of storage nodes of cells configuring the memory is reduced with shrinkage of elements, and therefore, a soft error of the memory develops into a major problem. As a measure to prevent occurrence of the soft error, an ECC (Error Correcting Code) circuit is mounted on the memory in the chip in many cases. The memory having the ECC circuit mounted thereon stores code bits for testing in addition to normal data bits. The ECC circuit detects the presence or absence of an error in the data bits based on the value of the code bits, detects one of the bits in which the error occurs, corrects the error and outputs the corrected bits to the exterior. The number of error bits in the same word which can be corrected is determined according to a code used by the ECC circuit. Generally, a one-bit error correction code or a SEC-DED code which is capable of performing a single error correction and two or more error detection is often used.

The block configuration of a conventional memory device used when the memory having the ECC circuit mounted thereon is tested by use of a BIST circuit is shown in FIG. 10 . In FIG. 10 , a BIST circuit 91 checks data output via an ECC circuit 92 and determines whether or not an error is present in output data of a memory array 93 . However, in the memory device having the ECC circuit 92 mounted thereon, a larger number of operation processes are performed in a case wherein an error has occurred than in a case wherein no error has occurred. Therefore, a critical path of the memory operation often occurs when an error correction is made.

However, since the frequency of occurrence of soft errors is extremely low, the critical path hardly appears at the time of at-speed test. Therefore, in this case, the critical path is not dealt with as an object of the at-speed test.

For example, in Jap. Pat. Appln. KOKAI Publication Disclosure No. 2003-36697, a test circuit for a semiconductor memory is disclosed. The test circuit has a pseudo error signal generating circuit between a memory circuit and a BIST circuit, converts output data from the memory circuit according to a set signal and generates a pseudo error signal necessary for checking the operation of the BIST circuit.

However, since no ECC circuit is provided in the test circuit of the semiconductor memory disclosed in this Jap. Pat. Appln. KOKAI Publication Disclosure No. 2003-36697, no measure to cope with a soft error of the memory is taken.

A semiconductor device according to an aspect of the present invention comprises a memory which stores data, an ECC circuit which corrects a bit error of data read out from the memory and generates correction data, a BIST circuit which tests the correction data output from the ECC circuit, and a pseudo error generating circuit which generates a pseudo error for at least one bit configuring the data read out from the memory and supplies the pseudo error to the ECC circuit in a test mode.

FIG. 1 is a block diagram showing the configuration of a first embodiment of this invention.

FIG. 2 is a block diagram showing a concrete circuit of a PRPG circuit of FIG. 1 .

FIG. 3 is a block diagram showing the configuration of a second embodiment of this invention.

FIG. 4 is a block diagram showing the configuration of a third embodiment of this invention.

FIG. 5 is a block diagram showing the configuration of a fourth embodiment of this invention.

FIG. 6 is a block diagram showing the configuration of a fifth embodiment of this invention.

FIG. 7 is a block diagram showing the configuration of a sixth embodiment of this invention.

FIG. 8 is a block diagram showing the configuration of a seventh embodiment of this invention.

FIG. 9 is a flowchart for illustrating the operation of the seventh embodiment.

FIG. 10 is a block diagram showing the configuration of a conventional test circuit.

There will now be described embodiments of this invention in detail with reference to the accompanying drawings.

First, a first embodiment of this invention is explained with reference to FIG. 1 . In FIG. 1 , a memory array 11 is configured by an SRAM, for example. The memory array 11 stores the total number of bits including a preset number of data bits configuring data and a preset number of error bits of an error correction code as one word unit in each address position. Row and column address decoders which designate address positions of the memory array 11 are attached to the memory array 11 , but they are omitted here to make the explanation simple. Further, an input port In 1 and output port Out 1 which are used to input/output data and a clock input port C 11 which receives a clock CLK are provided in the memory array 11 .

The data input port In 1 of the memory array 11 is connected to a first output port Out 2 of an ECC circuit 12 via a data path and the data output port Out 1 is connected to a first input port In 2 via another data path. The same clock CLK as that supplied to the memory array 11 is supplied to a clock input port C 12 . The ECC circuit 12 further includes a data input port In 3 and data output port Out 3 and is connected to a BIST circuit 13 via the above ports. The BIST circuit 13 includes a clock input port C 13 and is supplied with the same clock CLK as that supplied to the memory 11 and ECC circuit 12 . A test output indicating the test result of the BIST circuit 13 is output via a Pass/Fail terminal.

The BIST circuit 13 further includes an EN signal input terminal EN and is configured to be supplied with a test enable signal TESTEN and activated.

Further, a pseudo error generator circuit 14 is connected to the data path connected between the data output port Out 1 of the memory array 11 and the data input port In 2 of the ECC circuit 12 . The pseudo error generator circuit 14 includes a pseudo random pulse generator circuit (which is hereinafter referred to as a PRPG circuit) 14 A which receives a test enable signal TESTEN and clock CLK, a decoder 14 B which decodes n-bit random pulse data output from the PRPG circuit 14 A and generates 2 n decode outputs, an AND circuit 14 C to which an output of the decoder 14 B and the test enable signal TESTEN are input, and an EXOR circuit 14 D which is supplied with an output of the AND circuit 14 C at one input terminal. The EXOR circuit 14 D further receives a data bit from the output port Out 1 of the memory array 11 at the other input terminal.

Next, one example of the concrete circuit of the PRPG circuit 14 A is explained with reference to FIG. 2 . In FIG. 2 , the PRPG circuit 14 A is a linear feedback shift register (LFSR) circuit of 8-bit configuration, for example. The PRPG circuit 14 A includes eight series-connected shift registers SR 1 to SR 8 and EXOR circuits EX 1 , EX 2 , EX 3 which are respectively connected between the shift registers SR 1 and SR 2 , between the shift registers SR 5 and SR 6 , and between the shift registers SR 6 and SR 7 . Outputs S 0 to S 7 from the shift registers SR 1 to SR 8 are respectively supplied to the next-stage circuits and are also supplied as 8-bit output data (n=8) to the decoder 14 B of FIG. 1 . Further, the bit output S 7 of the final-stage shift register SR 8 is supplied to the EXOR circuits EX 3 , EX 2 , EX 1 via a feedback circuit or feedback line FL and fed back to the input terminal of the first-stage shift register SR 1 .

In the circuit of FIG. 2 , when the TESTEN signal of “L” level is supplied to the reset input terminals R of the shift registers SR 1 to SR 8 , output signals of the shift registers SR 1 to SR 8 are initialized and set to a value other than S 7 to S 0 =00000000.

In this state, when the TESTEN signal is set to an “H” level, output signals are output at a given timing corresponding to the clock CLK. At this time, the output S 7 of the final-stage shift register SR 8 is fed back to the first-stage shift register SR 1 via the feedback line FL and is also fed back to the intermediate shift registers SR 2 , SR 6 , SR 7 via the three EXOR circuits EX 1 , EX 2 , EX 3 . Therefore, outputs S 0 to S 7 of eight bits from the shift registers SR 1 to SR 8 represent a pseudo random number data.

The outputs S 6 to S 0 (n=7) of seven bits except the final-stage output S 7 , for example, among the pseudo random pulses of eight bits are supplied to the decoder 14 B and a selected one of 2 7 1-bit decode outputs is supplied to one input terminal of the AND circuit 14 C, while the test enable signal TESTEN is supplied to the other input terminal of the AND circuit 14 C.

The AND circuit 14 C supplies an “H” level signal to the EXOR circuit 14 D only when the test enable signal TESTEN is “H” and the 1-bit decode output from the decoder 14 B is “H”. Therefore, an output from the EXOR circuit 14 D is set to “H” or “L” when a data bit from the output port Out 1 of the memory array 11 is “L” or “H”, respectively. Thus, an inverted data bit or code bit is supplied as a pseudo soft error to the ECC circuit 12 from the EXOR circuit 14 D.

The ECC circuit 12 detects the pseudo soft error and is activated to generate and supply correction data to the BIST circuit 13 . As a result, the at-speed test for the memory array 11 and ECC circuit 12 is made by the BIST circuit 13 , thereby making it possible to perform the screening for the critical path of the memory array 11 .

In the embodiment of FIG. 1 , a storage area which stores the code bits for the ECC circuit 12 is contained in the memory array 11 . Therefore, all of the data bits and code bits are output from the output port Out 1 and all of the bits are subjected to error correction by the ECC circuit 12 .

However, when it is sufficient if the test for the data bits is made, it is satisfactory to perform the error correction process for the data bits. In this case, only the data bits may be supplied to the ECC circuit 12 via the pseudo error generator circuit 14 .

FIG. 3 is a block diagram showing the configuration of another embodiment of this invention which is configured based on the above idea. In FIG. 3 , portions which correspond to those of FIG. 1 are denoted by the same or similar reference symbols and the detail explanation thereof is omitted.

In the embodiment of FIG. 3 , a memory array 11 A which stores data bits and a memory array 11 B which stores code bits are separately provided. In the memory array 11 A, an input port In 1 and output port Out 1 are provided together with a clock terminal C 11 . The ports In 1 and Out 1 are respectively connected to an output port Out 2 and input port In 2 of an ECC circuit 12 A. Like the embodiment of FIG. 1 , the ECC circuit 12 A includes an input port In 4 and output port Out 4 together with a clock terminal C 12 in addition to an input port In 3 and output port Out 3 connected to a BIST circuit 13 . The input port In 4 and output port Out 4 are respectively connected to an output port Out 5 and input port In 5 of the memory array 11 B. Further, a clock terminal C 14 is provided in the memory array 11 B and is supplied with the same clock CLK as that supplied to the memory array 11 A.

In the embodiment of FIG. 3 , only data bits stored in the memory array 11 A including a data bit formed as a pseudo error bit in the pseudo error generator circuit 14 are supplied to the ECC circuit 12 A. On the other hand, code bits stored in the memory array 11 B are directly supplied to the ECC circuit 12 A. Data bits which are subjected to an error correction process by the ECC circuit 12 A and code bits which are not processed are combined as a word in the ECC circuit 12 A and supplied to the BIST circuit 13 for test. Then, a test output having the contents of Pass/Fail is acquired.

In the embodiment of FIG. 3 , the data bits and code bits are stored in the different memory arrays. However, the same operation can be attained by making a configuration as follows. That is, like the case of FIG. 1 , the data bits and code bits are stored in the same memory array, only the data bits are supplied to the ECC circuit 12 A via a first data path (not shown) including a bit path via the pseudo error generator circuit 14 at the time of readout from the memory array 11 A and the code bits are directly supplied to the ECC circuit 12 A via a second data path (not shown).

In the embodiment of FIG. 1 , there is a possibility that a 1-bit error occurs in the data bits in the same word which is different from the pseudo error bit generated from the pseudo error generator circuit 14 . In this case, a total of two bits of errors are included in the same word. If the ECC circuit 12 shown in FIG. 1 is of 1-bit correction type, it cannot correct errors of two bits and, therefore, the test output becomes a “fail” as the test result of the BIST circuit 13 .

However, in a normal test circuit which does not use the pseudo error generator circuit 14 , only the 1-bit error is supplied to an ECC circuit. Therefore, the 1-bit error can be corrected by the ECC circuit 12 and a “pass” output can be attained as the test output. In a case where the probability that a 1-bit error occurs in one word is extremely small, it is preferable to determine that the chip of a to-be-tested semiconductor device is a “pass” when taking it into consideration that the soft error test can be made.

An embodiment of FIG. 4 is configured based on the above idea and a circuit using a code capable of correcting a 1-bit error and also capable of detecting a 2-bit error is used in an ECC circuit 12 B.

In the embodiment of FIG. 4 , portions which correspond to those of FIG. 1 are denoted by the same or similar reference symbols and the repetitive explanation thereof is omitted. In FIG. 4 , the ECC circuit 12 B has a terminal DED through which a signal indicating detection of a 2-bit error is output when the 2-bit error is detected. For example, an “H” level detection signal appears on the terminal DED when a 2-bit error is detected.

A BIST circuit 13 A includes a BIST circuit section 13 A- 1 which receives an error correction output from the ECC circuit 12 B, an OR circuit 13 A- 2 which receives a Pass/Fail output of “H” or “L” level of the BIST circuit section 13 A- 1 at one input terminal, and a latch circuit 13 A- 3 which latches an output of the OR circuit 13 A- 2 . A detection signal of “H” or “L” level indicating the 2-bit error detection output from the terminal DED is supplied to the other input terminal of the OR circuit 13 A- 2 .

In FIG. 4 , if a bit error occurs in neither the data bit nor the code bit read out from the memory array 11 , only one bit supplied from the pseudo error generator circuit 14 to the ECC circuit 12 B becomes an error for one word. As a result, the ECC circuit 12 B is activated and an error correction output is supplied to the BIST circuit 13 A. In this case, a “pass” output (“H” level) is output from the BIST circuit section 13 A- 1 and an “L” level detection signal is obtained from the terminal DED of the ECC circuit 12 B. Therefore, an output of the OR circuit 13 A- 2 is set to an “H” level and latched in the latch circuit 13 A- 3 and an “H” level test output is obtained as a final “pass” output.

Further, in FIG. 4 , in a case where a bit error occurs in a data bit or code bit read out from the memory array 11 , a total of two bits of errors containing an error of one bit supplied from the pseudo error generator circuit 14 to the ECC circuit 12 B are provided for one word. Therefore, error correction becomes impossible and an error correction output from the activated ECC circuit 12 B is not correctly corrected data. Therefore, when the error correction output from the ECC circuit 12 B is supplied to the BIST circuit 13 A, a “fail” output (“L” level) is obtained from the BIST circuit section 13 A- 1 . Since a detection signal of “H” level indicating 2-bit error detection is obtained from the terminal DED of the ECC circuit 12 B, the “H” level signal is supplied as an input to the OR circuit 13 A- 2 and an “H” level output is obtained from the OR circuit 13 A- 2 . The “H” level output is latched in the latch circuit 13 A- 3 and a test output is obtained as a final “pass” output.

In the embodiment of FIG. 4 , like the embodiment of FIG. 1 , a storage area which stores code bits used for the ECC circuit 12 B is contained in the memory array 11 . Therefore, all of the data bits and code bits are output to the output port Out 1 and all of the bits are subjected to error correction by the ECC circuit 12 B.

However, when it is sufficient if the test for the data bits is made, it is satisfactory to perform the error correction process for the data bits. In this case, only the data bits including a data bit via the pseudo error generator circuit 14 may be supplied to the ECC circuit 12 B.

FIG. 5 is a block diagram showing the configuration of another embodiment of this invention configured based on the above idea. In FIG. 5 , portions which correspond to those of FIG. 4 are denoted by the same or similar reference symbols and the detailed explanation thereof is omitted.

In the embodiment of FIG. 5 , a memory array 11 A which stores data bits and a memory array 11 B which stores code bits are separately provided. In the memory array 11 A, an input port In 1 and output port Out 1 are provided together with a clock terminal C 11 . The ports In 1 and Out 1 are respectively connected to an output port Out 2 and input port In 2 of an ECC circuit 12 B. Like the embodiment of FIG. 4 , the ECC circuit 12 B includes an input port In 4 and output port Out 4 together with a clock terminal C 12 in addition to an input port In 3 and output port Out 3 connected to a BIST circuit 13 A. The input port In 4 and output port Out 4 are respectively connected to an output port Out 5 and input port In 5 of the memory array 11 B. Further, a clock terminal C 14 is provided in the memory array 11 B and is supplied with the same clock CLK as that supplied to the memory array 11 A. Further, a 2-bit error detection terminal DED is provided.

In the embodiment of FIG. 5 , of the data bits stored in the memory array 11 A only a data bit is supplied as a pseudo error bit to the ECC circuit 12 B via a pseudo error generator circuit 14 . On the other hand, code bits stored in the memory array 11 B are directly supplied as it is to the input port In 4 of the ECC circuit 12 B. Data bits which are subjected to an error correction process by the ECC circuit 12 B and code bits which are not processed are combined as a word in the ECC circuit 12 B and supplied to the BIST circuit 13 A for test. Then, a final test output having the contents of Pass/Fail can be acquired.

In the embodiment of FIG. 5 , the data bits and code bits are stored in the different memory arrays 11 A, 11 B. However, like the case of FIG. 4 , the same operation can be attained by making a configuration as follows. That is, the data bits and code bits are stored in the same memory array, only the data bits are supplied to the ECC circuit 12 B via a first data path (not shown) including the pseudo error generator circuit 14 at the time of readout from the memory array and the code bits are directly supplied to the ECC circuit 12 B via a second data path (not shown).

In the embodiments of FIGS. 1 , 3 to 5 , a case wherein the pseudo error generator circuit 14 is configured by use of the pseudo random pulse generator circuit (PRPG circuit) 14 A with the configuration shown in FIG. 2 is explained. However, a circuit of another configuration can be used as the pseudo error generator circuit. FIG. 6 shows still another embodiment using one example of the pseudo error generator circuit 14 A.

In FIG. 6 , the pseudo error generator circuit 14 A includes eight series-connected shift registers SR 1 to SR 8 and eight EXOR circuits EX 11 to EX 18 . The EXOR circuits EX 11 to EX 18 are connected to respectively receive output bits of the shift registers SR 1 to SR 8 at one input terminal and respectively receive eight output bits of the memory array 11 at the other input terminal. Further, outputs Out< 0 > to Out< 7 > from the output terminals of the EXOR circuits are supplied to the ECC circuit 12 .

Outputs S 0 to S 7 from the shift registers SR 1 to SR 7 are respectively supplied to the next-stage circuits and are supplied to the final-stage shift register SR 8 of the EXOR circuit. In this case, the output S 7 of the final-stage shift register SR 8 is supplied to the EXOR circuit EX 18 and fed back to the input terminal of the first-stage shift register SR 1 . via a feedback circuit FL. Further, a test enable signal TESTEN is supplied to the reset terminals of the shift registers SR 1 to SR 8 and a clock CLK is supplied to the clock terminals thereof.

In the circuit of FIG. 6 , if the TESTEN signal of “L” level is supplied to the reset input terminals R of the shift registers SR 1 to SR 8 , output signals S 0 to S 7 of the shift registers SR 1 to SR 8 are initialized and only one of the output signals S 0 to S 7 is initialized to be set to the “H” level “1”. For example, only the output S 0 of the first-stage shift register SR 1 is set to the “H” level.

After this, if the clock CLK is supplied while the test enable signal TESTEN is kept in the “H” state, for example, the output signal S 1 of the shift register SR 2 is set to the “H” level at the timing of a rise of the “H” level of the clock CLK. Then, the output signal S 1 is supplied to the EXOR circuit EX 12 . At this time, if a data bit which is read out from the memory array 11 and supplied to the EXOR circuit EX 12 is set at the “L” level, the output Out< 1 > of the EXOR circuit EX 12 is inverted to “H” and supplied to the ECC circuit 12 as a pseudo error bit. On the contrary, if the data bit is “H”, it is inverted to “L” and also supplied to the ECC circuit 12 as a pseudo error bit.

The outputs of the shift registers SR 3 , SR 4 , . . . are sequentially set to “H” each time the clock CLK is supplied while the signal TESTEN is kept in the “H state. Then, a pseudo soft error of 1-bit/word is sequentially supplied from a corresponding one of the EXOR circuits EX 12 , EX 13 , . . . in response to the output of the memory array 11 .

The ECC circuit 12 detects a pseudo soft error and is activated to generate and supply correction data to the BIST circuit. As a result, the at-speed test for the memory array 11 and ECC circuit 12 is made by the BIST circuit of the following stage, thereby making it possible to perform the screening process for the critical path of the memory array 11 . In the explanation for FIG. 6 , data bits are read out from the memory array 11 and a pseudo soft error is supplied. However, if code bits for error correction are stored in the memory array 11 , the code bits may also be read out in succession to the data bits, for example, and then a pseudo soft error may be supplied in the same manner as described above, for example.

In each of the first to fifth embodiments described above, a pseudo soft error is generated for a given data bit. However, the same effect can be attained even if a bit which causes a pseudo error to be generated is fixed.

FIG. 7 shows a block configuration of an embodiment configured based on the above idea. A bit path P 1 connected to a specified output port OutF of a memory array 11 in which data bits and code bits are stored is connected to one input terminal of an EXOR circuit 14 EX. A test enable signal TESTEN is supplied to the other input terminal of the EXOR circuit 14 EX whose output is connected to a specified input port Inf of an ECC circuit 12 B. The ECC circuit 12 B is configured in the same manner as in the embodiment of FIG. 4 .

In the circuit of FIG. 7 , if a bit signal read out from the memory array 11 to the output port OutF is set at the “H” level, for example, it is inverted to the “L” level when the test enable signal TESTEN is set at the “H” level. Then, it is supplied as a pseudo soft error bit to the input port Inf of the ECC circuit 12 B. As a result, the ECC circuit 12 B is activated via the path P 1 connected to the input port Inf and an error correction operation is performed. The remaining data bits and code bits are supplied to the ECC circuit 12 B via the output port Out 1 . The entire operation of the embodiment of FIG. 7 is the same as that of the embodiment of FIG. 4 and no further detail explanation thereof is made. However, the pseudo error generator circuit includes only the EXOR circuit 14 EX and the circuit configuration is made extremely simple in comparison with that of the embodiment of FIG. 4 .

In each of the first to sixth embodiments, a pseudo soft error is generated by use of the EXOR circuit provided on the bit path from the memory array to the ECC circuit. Thus, the EXOR circuit provided on the bit path may cause the operation speed of the test circuit to be lowered in some cases.

FIG. 8 shows an embodiment configured to cope with the above case. In FIG. 8 , the whole configuration can be considered to be obtained by omitting the pseudo error generator circuit 14 in the embodiment of FIG. 5 . Portions of FIG. 8 which correspond to those of FIG. 5 are denoted by the same or similar reference symbols and the explanation thereof is omitted. As is clearly understood from FIG. 8 , this embodiment is configured to supply a data bit output from the output port Out 1 of the memory array 11 A directly to the input port In 2 of the ECC circuit 12 C without using the EXOR circuit connected to the pseudo error generator circuit.

The ECC circuit 12 C has a 2-bit error detection terminal DED and enable signal input terminal ECCEN. The ECCEN terminal receives a control output from a control circuit 13 B- 4 provided in a BIST circuit 13 B- 1 . A control output of the control circuit 13 B- 4 is supplied to the ECCEN terminal of the ECC circuit 12 C. The ECC circuit 12 C is selectively set into one of two operation modes according to a level of the control output of the control circuit 13 B- 4 of the BIST circuit 13 B- 1 .

First, when an ECCEN signal is at the “H” level, the ECC circuit 12 C is set in the normal mode. Therefore, when data bits are written into a memory array 11 A at the data write time, corresponding error correction code bits are written into a memory array 11 B.

When the ECCEN signal is at the “L” level, the ECC circuit 12 C is set in a non-operative mode and is thus set in a state in which it does not function as an ECC circuit. Therefore, when data bits are written into the memory array 11 A at the data write time, corresponding error correction code bits are not written into the memory array 11 B.

Like the embodiment of FIG. 5 , the DED terminal of the ECC circuit 12 C is connected to one input terminal of an OR circuit 13 B- 2 of a BIST circuit 13 B and a Pass/Fail output of the BIST circuit section 13 B- 1 is supplied to the other input terminal thereof. An output of the OR circuit 13 B- 2 is output as a final (Pass/Fail) output from a latch circuit 13 B- 3 .

Next, the operation of the embodiment of FIG. 8 containing the control circuit 13 B- 4 is explained with reference to the flowchart of FIG. 9 . In the embodiment of FIG. 8 , when a test mode is set in the step S 1 of FIG. 9 , a test enable signal TESTEN is first set to the “H” level. Then, the control circuit 13 B- 4 which has received the TESTEN signal supplies an “H” level signal to the terminal ECCEN of the ECC circuit 12 C. As a result, the ECC circuit 12 C is set into the normal operation mode and data bits are written into the memory array 11 A in a normal state in the step S 2 .

After this, the ECCEN signal is set to the “L” level in the step S 3 . Then, data bits including one inverted bit obtained by inverting one bit of data bits written into the same address of the memory array 11 A in the step S 2 is written into the memory array 11 A in the step S 4 . At this time, code bits corresponding to the data are not written into the memory array 11 B. Therefore, data containing a one-bit/word error is written as combined data of the data of the memory array 11 A and the code of the memory array 11 B.

In this state, a signal to the terminal ECCEN is set to the “H” level again in the step S 5 and the ECC circuit 12 C is set into the normal operation mode. Further, if a test to read out data stored in the memory arrays 11 A and 11 B is made in the step S 6 in this state, the ECC circuit 12 C detects the error and is activated to output an error correction output to the BIST circuit section 13 B. In the case of a 1-bit error, the BIST circuit 13 B- 1 outputs a “pass” signal of “H” level to the OR circuit 13 B- 2 . At this time, the DED signal is set at the “L” level, but an output of the OR circuit 13 B- 2 is set to the “H” level. Therefore, a final “pass” output is output via the latch circuit 13 B- 3 .

When a 2-bit error is detected by the ECC circuit 12 C, the DED signal is set to the “H” level. Further, an output of the BIST circuit 13 B- 1 becomes a “fail” of “L” level, but like the embodiment of FIG. 5 , a final “pass” output can be acquired from the latch circuit 13 B- 3 .

According to the embodiments of this invention, the semiconductor device having the memory, ECC circuit and BIST circuit is so configured that an error correction can be made without fail by the ECC circuit at the test time in a state in which the ECC circuit and BIST circuit are activated. Thus, the semiconductor device capable of performing the satisfactory screening process for critical paths of the ECC circuit and memory, for example, can be provided.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.