Method for fabricating semiconductor component with on board capacitor

This application is a division of Ser. No. 10/226,472, filed Aug. 23, 2002, U.S. Pat. No. 6,891,248 B2.

This application is related to Ser. No. 10/887,255, filed Jul. 7, 2004.

This invention relates generally to semiconductor manufacture and packaging. More particularly, this invention relates to a semiconductor component having an on board capacitor, to a method for fabricating the component, and to systems incorporating the component.

One type of semiconductor package includes several semiconductor components in a single package module. The semiconductor components can be in the form of semiconductor dice, semiconductor packages, or semiconductor wafers. This type of package is sometimes referred to as a multi chip module (MCM) package, or as a system in a package (SIP).

Typically, the MCM package is constructed to provide a system level of functionality, such as a control or memory function. As such, the MCM package can include different types of semiconductor components configured to perform different functions in the system. For example, a MCM package configured as a micro controller can include a microprocessor component, and one or more memory components, such as SRAMs, DRAMs, or flash memories.

MCM packages offer increased system performance, because the integrated circuits on the semiconductor components can be operated more efficiently. This is largely a result of decreasing the interconnection length between the components. In addition, system performance is improved because the input/output ports for the MCM package can be configured to access the whole system, which can be organized to reduce signal delays and access times. The power requirements are also reduced due to a reduction in the driver requirements.

One problem that occurs in the MCM packages results from parasitic inductance. For example, parasitic inductance can result from switching transients and cross coupling between the conductors (e.g., wires or traces) that electrically connect the different components in the MCM package. Parasitic inductance can cause transient voltages, spurious signals, and power supply noise, which degrade the operation of the semiconductor components, and adversely affect the performance of the system. Parasitic inductance can also make testing of the MCM packages more difficult because false readings are obtained, making electrical evaluation of the packages more difficult. Parasitic inductance is particularly a problem at clocking speeds of 500 mHz or more.

One technique for overcoming parasitic inductance is by filtering the transient voltages, spurious signals and power supply noise. For example, external de coupling capacitors can be surface mounted within the MCM packages or on a substrate, such as a circuit board or test board, containing the MCM packages. One problem with these external capacitors is that they are susceptible to shorting, and also to mechanical damage due to their surface mounting. In addition, the conductive paths between the capacitors and the components, or the integrated circuits on the components, can also produce parasitic inductance. As MCM packages, and other systems containing multiple semiconductor components, become more densely populated with components, problems associated with parasitic inductance are increased.

The present invention reduces the problems associated with parasitic inductance by incorporating an on board capacitor into the structure of a component. In addition, the on board capacitor is more durable than conventional surface mount capacitors, is protected by the structure of the component, and is closer to the integrated circuits contained on the component. The present invention is also directed to a novel method for fabricating components with on board capacitors, and to improved systems incorporating the components.

In accordance with the present invention, a semiconductor component, a method for fabricating the component, and systems incorporating the component are provided. In an illustrative embodiment, the component comprises a semiconductor package containing a single die. The die includes integrated circuits, and die contacts, such as bond pads, in electrical communication with the integrated circuits.

In addition to the die, the component includes an array terminal contacts, and an on board capacitor in electrical communication with selected terminal contacts and selected die contacts. The capacitor is configured to filter transient voltages, spurious signals, and power supply noise resulting from parasitic inductance. The capacitor includes a first electrode and a second electrode separated by a dielectric layer. In the illustrative embodiment, the first electrode is in electrical communication with a ground (Vss) die contact, and with a ground (Vss) terminal contact. The second electrode is in electrical communication with a power (Vcc) die contact, and with a power (Vcc) terminal contact.

The fabrication method is preferably performed on a wafer containing multiple semiconductor dice which are made into the components, and then singulated into the separate components. The fabrication method includes the steps of forming the first electrodes on the dice using a first metal layer in contact with the ground (Vss) die contacts, forming a dielectric layer on the first electrodes, and then forming second electrodes on the dice using a second metal layer in contact with the power (Vcc) die contacts. The first metal layer can comprise a portion of a first redistribution layer (RDL 1 ) formed on an electrically insulating layer such as a passivation layer. The dielectric layer can comprise a deposited and cured polymer, and the second metal layer can comprise a portion of a second redistribution layer (RDL 2 ).

The component can be used to construct systems such as MCM packages, and multi chip modules. In an alternate embodiment a wafer component comprises a semiconductor wafer containing multiple dice, with each die having an on board capacitor. The wafer component can be used to construct systems such as circuit boards and modules.

FIG. 1A is a plan view of a semiconductor component constructed in accordance with the invention;

FIG. 1B is a side elevation view of FIG. 1A ;

FIG. 1C is an enlarged, partially cut away portion of FIG. 1A ;

FIG. 1D is an enlarged schematic cross sectional view taken along section line 1 D— 1 D of FIG. 1C ;

FIG. 1E is an enlarged schematic cross sectional view taken along section line 1 E— 1 E of FIG. 1C ;

FIG. 2 is a schematic cross sectional view of a packaged system incorporating components constructed in accordance with the invention;

FIG. 3A is a plan view of a semiconductor multi chip module incorporating components constructed in accordance with the invention;

FIG. 3B is a schematic cross sectional view taken along section line 3 B— 3 B of FIG. 3A ;

FIG. 3C is an enlarged schematic cross sectional view taken along section line 3 C— 3 C of FIG. 3B ;

FIGS. 4A–4F are schematic cross sectional views illustrating steps in a method for fabricating the semiconductor component of FIGS. 1A–1E ;

FIG. 5A is view taken along line 5 A— 5 A of FIG. 4A ;

FIG. 5B is a cross sectional view taken along line 5 B— 5 B of FIG. 4B ;

FIG. 5C is a cross sectional view taken along line 5 C— 5 C of FIG. 4C ;

FIG. 5D is a cross sectional view taken along line 5 D— 5 D of FIG. 4D ;

FIG. 5E is a cross sectional view taken along line 5 E— 5 E of FIG. 4E ;

FIG. 5F is a cross sectional view taken along line 5 F— 5 F of FIG. 4F ;

FIG. 6A is a schematic plan view of an alternate embodiment wafer component constructed in accordance with the invention;

FIG. 6B is a cross section taken along line 6 B— 6 B of FIG. 6A illustrating a die on the wafer component; and

FIG. 6C is a schematic cross sectional view of an electronic assembly constructed with the wafer component.

As used herein, the term “semiconductor component” refers to an electronic element that includes a semiconductor die. Exemplary semiconductor components include semiconductor dice, semiconductor packages, semiconductor wafers, BGA devices, multi chip modules and circuit boards.

Referring to FIGS. 1A–1E , a semiconductor component 10 P constructed in accordance with the invention is illustrated. In this embodiment, the component 10 P comprises a semiconductor package, such as a chip scale package (CSP).

The component 10 P includes a semiconductor die 12 , and a plurality of terminal contacts 14 . The die 12 can comprise a conventional semiconductor die having a desired electrical configuration. For example, the die 12 can be a memory device, such as a DRAM, SRAM or flash memory. In the illustrative embodiment, the component 10 P and the die 12 are generally rectangular in shape, but other shapes such as square can be utilized. In addition, the component 10 P and the die 12 are substantially the same size, and have matching peripheral outlines.

The die 12 includes a pattern of die contacts 16 , such as bond pads embedded within an electrically insulating passivation layer 18 ( FIG. 1D ). The die contacts 16 and the die passivation layer 18 are located on a face 21 (circuit side) of the die 12 , with the die contacts 16 located below the surface of the passivation layer 18 . In the illustrative embodiment the die contacts 16 are located along a center line 20 of the die 12 , which is also the center line of the component 10 P. As shown in FIGS. 1D and 1E , the die 12 also includes internal conductors 22 in electrical communication with the die contacts 16 and with integrated circuits 24 contained on the die 12 .

The component 10 P also includes an outer protective layer 28 . As shown in FIGS. 1D and 1E , the terminal contacts 14 are located in openings 26 formed through the outer protective layer 28 . The outer protective layer 28 can comprise a dielectric material adapted to electrically insulate and protect the component 10 P.

The terminal contacts 14 can comprise solder bumps, or balls, bonded to under bump metallization layers 30 . The terminal contacts 14 provide electrical connection points from the outside world to the integrated circuits 24 and other electrical devices on the component 10 P. In the illustrative embodiment, the terminal contacts 14 are arranged in a ball grid array composed of six rows and sixteen columns. However, as is apparent, other dense area arrays, or patterning arrangements, can be used for locating the terminal contacts 14 . The terminal contacts 14 permit the component 10 P to be flip chip mounted circuit side down to mating electrodes on a supporting substrate, such as a circuit board. Accordingly the component 10 P can be referred to as a “flip chip” component.

The component 10 P also includes an on board capacitor 32 configured to filter transient voltages and spurious signals, such as those produced by parasitic inductance, and to reduce power supply noise. The capacitor 32 thus improves the performance of the component 10 P and improves test procedures, such as burn-in conducted on the component 10 P. The capacitor 32 is in electrical communication with a ground terminal contact 14 Vss, and in electrical communication with a power terminal contact 14 Vcc for the component 10 P.

As shown in FIGS. 1D and 1E , the capacitor 32 includes a first (lower) electrode 34 and a second (upper) electrode 36 separated by a dielectric layer 38 . The first (lower) electrode 34 is in electrical communication with the ground terminal contact 14 Vss and with a ground die contact 16 Vss. The second (upper) electrode 36 is in electrical communication with the power terminal contact 14 Vcc and with a power die contact 16 Vcc. As shown in FIG. 1D , a ground conductor 40 Vss electrically connects the ground terminal contact 14 Vss, the ground die contact 16 Vss and the first (lower) electrode 34 . As shown in FIG. 1E , a power conductor 42 Vcc electrically connects the power terminal contact 14 Vcc, the power die contact 16 Vcc and the second (upper) electrode 36 . In addition, as shown in FIG. 1C , generic conductors 44 electrically connect the remaining terminal contacts 14 to their corresponding die contacts 16 on the die 12 .

Referring to FIG. 2 , a MCM package 50 that includes semiconductor components 10 P- 1 , 10 P- 2 and 10 P- 3 constructed in accordance with the invention is illustrated. The MCM package 50 can be configured as a system in a package (SIP) adapted to perform a desired function such as micro processing. Each semiconductor component 10 P- 1 , 10 P- 2 , 10 P- 3 includes an on board capacitors 32 constructed substantially as previously described for semiconductor component 10 P ( FIG. 1A ). However, the components 10 P- 1 , 10 P- 2 , 10 P- 3 can be configured to perform different electrical functions in the MCM package 50 . For example, with the MCM package 50 configured as a micro controller, component 10 P- 1 can include an SRAM die, component 10 P- 2 can include a microprocessor die, and component 10 P- 3 can include a flash memory die.

The on board capacitors 32 contained on the components 10 P- 1 , 10 P- 2 , 10 P- 3 improve the performance of the MCM package 50 by filtering transient voltages, spurious signals and power supply noise. In addition, the on board capacitors 32 are located close to the integrated circuits 24 ( FIG. 1D ) on the components 10 P- 1 , 10 P- 2 , 10 P- 3 such that the function of the capacitors 32 is improved. Specifically, fewer transient voltages and spurious signals are produced in the electrical paths between the capacitors 32 , and the integrated circuits 24 than with prior art external capacitors.

The MCM package 50 also includes a substrate 52 wherein the components 10 P- 1 , 10 P- 2 , 10 P- 3 are mounted using flip chip technology. The substrate 52 includes electrodes and conductors which electrically connect the components 10 P- 1 , 10 P- 2 , 10 P- 3 in a required electrical configuration. The substrate 52 also includes external leads 54 in electrical communication with the components 10 P- 1 , 10 P- 2 , 10 P- 3 . The MCM package 50 also includes a package body 56 formed of a cured plastic or other suitable material, which encapsulates the substrate 52 and the components 10 P- 1 , 10 P- 2 , 10 P- 3 .

Referring to FIGS. 3A–3C , a multi chip module 58 that includes several semiconductor components 10 P constructed as previously described with on board capacitors 32 is illustrated. The multi chip module 58 can be configured as a system for performing a specific function such as memory storage. The multi chip module 58 includes a module substrate 60 having patterns of electrodes 64 for flip chip mounting the components 10 P to the module substrate 60 . As such, the terminal contacts 14 on the components 10 P can be bonded to the electrodes 64 on the module substrate 60 using a suitable bonding process, such as solder reflow or thermode bonding. The electrodes 64 are in electrical communication with conductors 62 formed on the module substrate 60 in a required circuit pattern. In addition, the conductors 62 are in electrical communication with an edge connector 66 which provides a connection point from the outside to the multi chip module 58 . The on board capacitors 32 contained on the components 10 P improve the performance of the multi chip module 58 by filtering transient voltages, spurious signals and power supply noise, substantially as previously described.

Referring to FIGS. 4A–4F and 5 A– 5 F, a method for fabricating the component 10 P is illustrated. Initially, as shown in FIG. 4A , the semiconductor die 12 is provided. For simplicity, only a portion of the die 12 is illustrated. Preferably, the die 12 is contained on a semiconductor wafer containing a plurality of identical dice, and the fabrication steps are performed on all of the dice on the wafer.

Following fabrication, the dice will be singulated into a plurality of separate components 10 P. The die 12 includes integrated circuits 24 formed in a semiconducting substrate using techniques that are known in the art. The die 12 also includes internal conductors 22 in electrical communication with the integrated circuits 24 . In addition, the die 12 includes the die contacts 16 in electrical communication with the integrated circuits 24 . The die contacts 16 can comprise a thin film aluminum layer, or another electrically conductive material. In addition, the die contacts 16 can have a conventional shape (e.g., square or rectangular), a conventional size (e.g., 25 to 200 μm on a side), and can be arranged in a conventional configuration. As shown in FIG. 5A , the die 12 includes a ground die contact 16 Vss and a power die contact 16 Vcc. The die 12 also includes the passivation layer 18 which can comprise an electrically insulating material such as BPSG or SiO 2 . As shown in FIG. 5A , the passivation layer 18 includes openings 68 aligned with the die contacts 16 .

Initially as shown in FIG. 4B , the first (lower) electrode 34 and the ground conductor 40 Vss, are formed on the passivation layer 18 in electrical communication with the ground die contact 16 Vss. The first (lower) electrode 34 and the ground conductor 40 Vss, can be formed using a deposition process such as CVD, PECVD, PVD, sputtering or evaporation, followed by photopatterning and etching. Suitable materials include aluminum, chromium, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum or alloys of these metals, such as TiSi 2 .

Preferably, the first (lower) electrode 34 and the ground conductor 40 Vss, are formed from a first redistribution layer RDL 1 . Specifically, the first (lower) electrode 34 and the ground conductor 40 Vss comprise portions of the first redistribution layer RDL 1 . Redistribution layers are typically used in semiconductor manufacture to “fan out” the signals from standard die contacts 16 , to contacts of a dense area array, such as a ball grid array (BGA). In an ideal situation, the die 12 would be designed to have the die contacts 16 in a pattern that does not require the redistribution layer RDL 1 to be added. For example, a semiconductor manufacturer can design the die 12 and the die contacts 16 such that the die contacts 16 are already in a grid array, for attaching solder balls of a ball grid array (BGA). However, as this ideal situation does not always exist, redistribution layers are widely used in semiconductor manufacture.

In addition to forming the first (lower) electrode 34 and the ground conductor 40 Vss, the redistribution layer RDL 1 can be used to form the conductors 44 ( FIG. 1C ) for the remaining die contacts 16 , and pads 70 ( FIG. 1C ) on the conductors 44 for bonding the terminal contacts 14 . As shown in FIG. 5B , the first (lower) electrode 34 and the ground conductor 40 Vss, are in electrical communication with the ground die contact 16 Vss. In addition, the ground conductor 40 Vss includes a pad 70 Vss for bonding the ground terminal contact 14 Vss.

Next, as shown in FIG. 4C , the dielectric layer 38 for the capacitor 32 can be formed on the first (lower) electrode 34 . The dielectric layer 38 is sized to separate the first (lower) electrode 34 from the second (upper) electrode 36 by a precise distance (d). The value of the capacitance (C) of the capacitor 32 is a function of the distance (d), the area (A) of the dielectric layer 38 , and the dielectric constant or permittivity (E). These parameters can be related by the well known formula C=E A/d. Depending on the application, the value of C can be selected from micro farads (μF) to pico farads (pF).

The dielectric layer 38 can comprise a thin film dielectric material having a desired dielectric constant (E). Suitable dielectric materials include polymers, oxides, nitrides, ceramics or other high dielectric materials. For example, polyimide, tantalum pentoxide (Ta 2 O 5 ) and polyvinylidenefluoride (PVDF) are suitable dielectric materials. Depending on the material a suitable process such as deposition through a nozzle, spatuling, screen printing, or stenciling can be used to form the dielectric layer 38 . Also depending on the material, a curing step, such as heating at a selected temperature for a selected time period, may also be required.

Next, as shown in FIG. 4D , the second (upper) electrode 36 and the power conductor 42 Vcc, are formed on the dielectric layer 38 in electrical communication with the power die contact 16 Vcc. The second (upper) electrode 36 and the power conductor 42 Vcc, can be formed using a deposition process such as CVD, PECVD, PVD, sputtering or evaporation, followed by photopatterning and etching. Suitable materials include aluminum, chromium, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum or alloys of these metals, such as TiSi 2 .

Preferably, the second (upper) electrode 36 and the power conductor 42 Vcc, are formed from a second redistribution layer RDL 2 . Specifically, the second (upper) electrode 36 and the power conductor 42 Vcc comprise portions of the second redistribution layer RDL 2 . As shown in FIG. 5D , the second (upper) electrode 36 includes a pad 70 Vcc for the power terminal contact 14 Vcc.

Next, as shown in FIG. 4E , the outer protective layer 28 can be formed over the face 21 of the die 12 to encapsulate the capacitor 32 and associated conductors 40 VSS, 42 Vcc. The outer protective layer 28 can comprise a deposited polymer, such as polyimide, a glass, such as BPSG, or an oxide such as SiO 2 . The outer protective layer 28 can also comprise a photoimageable material, such as photoimageable polyimide, that can be blanket deposited as a wet or dry film, exposed through a mask, developed, and then cured.

As shown in FIG. 5E , the outer protective layer 28 includes the openings 26 for the terminal contacts 14 in a required pattern and with required diameters. The openings 26 align with the pads 70 for the terminal contacts 14 . The openings 26 can be formed using an etchant and a mask, such as a photoimageable resist mask. Alternately, if the outer protective layer 28 comprises a photoimageable material, the openings 26 can be formed by exposure and development. In the illustrative embodiment, the outer protective layer 28 also functions as a solder mask to prevent bridging of solder material between the terminal contacts 14 during fabrication of the component 10 P, and during flip chip mounting of the component 10 P.

Next, as shown in FIGS. 4F and 5F , the terminal contacts 14 , including the ground terminal contact 14 Vss and the power terminal contact 14 Vcc, can be formed in the openings 26 in electrical communication with the pads 70 . Prior to forming terminal contacts 14 , the under bump metallization layers 30 can be formed in the openings 26 and bonded to the pads 70 . The under bump metallization layers 70 can comprise a suitable metal, such as copper, nickel, gold, palladium and molybdenum, formed using a suitable deposition process, such as CVD.

The terminal contacts 14 can be formed of a metal, such as a solder alloy. For example, the terminal contacts 14 can comprise a solder alloy, such as 95% Pb/5% Sn, 60% Pb/40% Sn, 63% In/37% Sn, or 62% Pb/36% Sn/2% Ag. Alternately, the terminal contacts 14 can comprise a conductive polymer such as an isotropic or anisotropic adhesive, or a relatively hard metal such as nickel, copper, beryllium copper, alloys of nickel, alloys of copper, alloys of beryllium copper, nickel-cobalt-iron alloys and iron-nickel alloys.

The terminal contacts 14 can be formed using a reflow process, or by electrolytic deposition or electroless deposition. Another method for forming the terminal contacts 14 is by bonding pre-fabricated balls to the under bump metallization layers 30 . A ball bumper can also be employed to bond pre-fabricated balls. A suitable ball bumper is manufactured by Pac Tech Packaging Technologies of Falkensee, Germany. The terminal contacts 14 can also be formed using a conventional wire bonder apparatus adapted to form a ball bond, and then to sever the attached wire.

In addition, the number of terminal contacts 14 , the diameter D ( FIG. 1A ) of the terminal contacts 14 , and a pitch P ( FIG. 1B ) of the terminal contacts 14 can be selected as required. A representative diameter D can be from about 0.005-in (0.127 mm) to about 0.016-in (0.400 mm) or larger. A representative pitch P can be from about 0.004-in (0.100 mm) to about 0.039-in (1.0) mm or more.

Referring to FIGS. 6A–6B , a wafer component 10 W constructed in accordance with the invention is illustrated. The wafer component 10 W comprises a semiconductor wafer containing semiconductor dice 12 W. As shown in FIG. 6B , each die 12 W includes an array of terminal contacts 14 W. In addition, each die 12 W includes an on board capacitor 32 W constructed substantially as previously described.

Referring to FIG. 6C , an electronic assembly 76 W constructed using the wafer component 10 W is illustrated. The electronic assembly 76 W includes a circuit board 72 W and the wafer component 10 W flip chip mounted to the circuit board 72 W. In addition, the terminal contacts 14 W on the wafer component 10 W are bonded to electrodes 74 W on the circuit board 72 W. The capacitors 32 W on the wafer component 10 W function to reduce transient voltages, spurious signals and power supply noise in signals transmitted to the integrated circuits contained on the dice 12 W on the wafer component 10 W. In addition, the capacitors 32 W improve test procedures performed on the wafer component 10 W, particularly wafer level burn-in.

Thus the invention provides improved semiconductor components having on board capacitors, a method for fabricating the components, and systems incorporating the components. While the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.