Inventor
Salman Akram
Inventor
Boise, ID, US
Overview
Patents· 724 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1032%
G01RMeasuring electric variables15%
H05KPrinted circuits12%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
Y10TTechnical subjects covered by former us classification8%
H10DInorganic electric semiconductor devices5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
B33YAdditive manufacturing, i.e. manufacturing of three-dimensional [3d] objects by additive deposition, additive agglomeration or additive layering, e.g. by 3d printing, stereolithography or selective laser sintering3%
B28DWorking stone or stone-like materials2%
PatentTitleYear
11,127,769Elevated pocket pixels, imaging devices and systems including the same and method of forming the same202110,741,718Laser de-bond carrier wafer from device wafer202010,504,948Elevated pocket pixels, imaging devices and systems including the same and method of forming the same201910,490,644Hybrid gate dielectrics for semiconductor power devices201910,446,440Semiconductor devices comprising nickel-- and copper--containing interconnects201910,181,486Elevated pocket pixels, imaging devices and systems including the same and method of forming the same201910,062,608Semiconductor devices comprising nickel- and copper-containing interconnects201810,050,180LED with stress-buffer layer under metallization layer201810,002,941Hybrid gate dielectrics for semiconductor power devices20189,960,148Methods for transferring heat from stacked microfeature devices20189,935,069Reducing solder pad topology differences by planarization20189,911,769'Elevated pocket pixels, imaging devices and systems including the same and method of forming the same'20189,705,047'Method of attaching a light emitting device to a support substrate'20179,660,154'Chip scale light emitting device package with dome'20179,640,729'LED with stress-buffer layer under metallization layer'20179,640,433'Methods of forming interconnects and semiconductor structures'20179,437,762'Elevated pocket pixels, imaging devices and systems including the same and method of forming the same'20169,431,581'Method of attaching a light emitting device to a support substrate'20169,406,857'Chip scale light emitting device with metal pillars in a molding compound formed at wafer level'20169,343,612'Method of bonding a semiconductor device to a support substrate'20169,153,758'Method of attaching a light emitting device to a support substrate'20158,816,463'Wafer-level packaged microelectronic imagers having interconnects formed through terminals'20148,816,405'Elevated pocket pixels, imaging devices and systems including the same and method of forming the same'20148,786,097'Method of forming vias in semiconductor substrates and resulting structures'20148,759,970'Semiconductor device having copper interconnect for bonding'20148,703,518'Packaged microelectronic imagers and methods of packaging microelectronic imagers'20148,669,179'Through-wafer interconnects for photoimager and memory wafers'20148,647,982'Methods of forming interconnects in a semiconductor structure'20148,637,962'Semiconductor dice including at least one blind hole, wafers including such semiconductor dice, and intermediate products made while forming at least one blind hole in a substrate'20148,502,353'Through-wafer interconnects for photoimager and memory wafers'20138,470,687'Strained semiconductor by full wafer bonding'20138,389,920'Method and apparatus for breaking surface tension during a recessed color filter array process'20138,324,100'Methods of forming conductive vias'20128,324,101'Semiconductor dice including at least one blind hole, wafers including such semiconductor dice, and intermediate products made while forming at least one blind hole in a substrate'20128,294,273'Methods for fabricating and filling conductive vias and conductive vias so formed'20128,129,764'Imager devices having differing gate stack sidewall spacers, method for forming such imager devices, and systems including such imager devices'20128,111,515'Methods and apparatuses for transferring heat from stacked microfeature devices'20128,053,857'Packaged microelectronic imagers and methods of packaging microelectronic imagers'20118,035,179'Packaged microelectronic imagers and methods of packaging microelectronic imagers'20117,994,547'Semiconductor devices and assemblies including back side redistribution layers in association with through wafer interconnects'20117,994,595'Strained semiconductor by full wafer bonding'20117,989,345'Methods of forming blind wafer interconnects, and related structures and assemblies'20117,989,311'Strained semiconductor by full wafer bonding'20117,960,829'Support structure for use in thinning semiconductor substrates and for supporting thinned semiconductor substrates'20117,956,443'Through-wafer interconnects for photoimager and memory wafers'20117,952,158'Elevated pocket pixels, imaging devices and systems including the same and method of forming the same'20117,918,383'Methods for placing substrates in contact with molten solder'20117,919,348'Methods for protecting imaging elements of photoimagers during back side processing'20117,892,972'Methods for fabricating and filling conductive vias and conductive vias so formed'20117,858,429'Packaged microelectronic imagers and methods of packaging microelectronic imagers'20107,855,454'Semiconductor device structures including nickel plated aluminum, copper, and tungsten structures'20107,855,140'Method of forming vias in semiconductor substrates and resulting structures'20107,842,915'Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers'20107,829,976'Microelectronic devices and methods for forming interconnects in microelectronic devices'20107,829,979'High permeability layered films to reduce noise in high speed interconnects'20107,791,184'Image sensor packages and frame structure thereof'20107,772,116'Methods of forming blind wafer interconnects'20107,759,240'Use of palladium in IC manufacturing with conductive polymer bump'20107,759,800'Microelectronics devices, having vias, and packaged microelectronic devices having vias'20107,732,885'Semiconductor structures with dual isolation structures, methods for forming same and systems including same'20107,727,858'Method for fabricating a chip scale package using wafer level processing'20107,713,841'Methods for thinning semiconductor substrates that employ support structures formed on the substrates'20107,709,279'Methods for testing semiconductor devices methods for protecting the same from electrostatic discharge events during testing, and methods for fabricating inserts for use in testing semiconductor devices'20107,709,776'Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers'20107,705,349'Test inserts and interconnects with electrostatic discharge structures'20107,683,458'Through-wafer interconnects for photoimager and memory wafers'20107,645,635'Frame structure and semiconductor attach process for use therewith for fabrication of image sensor packages and the like, and resulting packages'20107,646,075'Microelectronic imagers having front side contacts'20107,602,618'Methods and apparatuses for transferring heat from stacked microfeature devices'20097,598,167'Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures'20097,592,246'Method and semiconductor device having copper interconnect for bonding'20097,569,934'Copper interconnect'20097,561,938'Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as repairs, to select procedures the ICs will undergo, such as additional repairs'20097,547,877'Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers'20097,531,453'Microelectronic devices and methods for forming interconnects in microelectronic devices'20097,518,227'Multiple die stack apparatus employing T-shaped interposer elements'20097,517,797'Carrier for wafer-scale package, wafer-scale package including the carrier, and methods'20097,514,291'Methods relating to singulating semiconductor wafers and wafer scale assemblies'20097,511,363'Copper interconnect'20097,511,262'Optical device and assembly for use with imaging dies, and wafer-label imager assembly'20097,504,615'Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers'20097,498,647'Packaged microelectronic imagers and methods of packaging microelectronic imagers'20097,489,041'Copper interconnect'20097,483,286'Semiconductor memory device with high permeability lines interposed between adjacent transmission lines'20097,443,022'Board-on-chip packages'20087,439,158'Strained semiconductor by full wafer bonding'20087,435,620'Low temperature methods of forming back side redistribution layers in association with through wafer interconnects'20087,419,852'Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies'20087,419,841'Microelectronic imagers and methods of packaging microelectronic imagers'20087,419,299'Methods of sensing temperature of an electronic device workpiece'20087,413,979'Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices'20087,391,637'Semiconductor memory device with high permeability composite films to reduce noise in high speed interconnects'20087,387,119'Dicing saw with variable indexing capability'20087,385,412'Systems and methods for testing microfeature devices'20087,375,414'High permeability layered films to reduce noise in high speed interconnects'20087,367,845'Modular sockets using flexible interconnects'20087,368,812'Interposers for chip-scale packages and intermediates thereof'20087,358,596'Device isolation for semiconductor devices'20087,345,358'Copper interconnect for semiconductor device'20087,341,881'Methods of packaging and testing microelectronic imaging devices'20087,338,889'Method of improving copper interconnects of semiconductor devices for bonding'20087,335,988'Use of palladium in IC manufacturing with conductive polymer bump'20087,335,968'High permeability composite films to reduce noise in high speed interconnects'20087,329,943'Microelectronic devices and methods for forming interconnects in microelectronic devices'20087,327,016'High permeability composite films to reduce noise in high speed interconnects'20087,317,322'Interconnect for bumped semiconductor components'20087,300,857'Through-wafer interconnects for photoimager and memory wafers'20077,294,897'Packaged microelectronic imagers and methods of packaging microelectronic imagers'20077,282,794'Multiple die stack apparatus employing t-shaped interposer elements'20077,282,793'Multiple die stack apparatus employing T-shaped interposer elements'20077,279,407'Selective nickel plating of aluminum, copper, and tungsten structures'20077,271,491'Carrier for wafer-scale package and wafer-scale package including the carrier'20077,265,330'Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers'20077,259,578'System for testing semiconductor components having interconnect with variable flexure contacts'20077,256,069'Wafer-level package and methods of fabricating'20077,253,957'Integrated optics units and methods of manufacturing integrated optics units for use with microelectronic imagers'20077,250,780'Probe card for semiconductor wafers having mounting plate and socket'20077,235,457'High permeability layered films to reduce noise in high speed interconnects'20077,235,837'Technique to control tunneling currents in DRAM capacitors, cells, and devices'20077,233,158'Air socket for testing integrated circuits'20077,232,754'Microelectronic devices and methods for forming interconnects in microelectronic devices'20077,217,597'Die stacking scheme'20077,214,962'Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer'20077,205,661'Projected contact structures for engaging bumped semiconductor devices and methods of making the same'20077,205,221'Under bump metallization pad and solder bump connections'20077,199,439'Microelectronic imagers and methods of packaging microelectronic imagers'20077,193,306'Semiconductor structure having stacked semiconductor devices'20077,192,311'Apparatus for forming modular sockets using flexible interconnects and resulting structures'20077,189,954'Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers'20077,189,623'Semiconductor processing method and field effect transistor'20077,183,191'Method for fabricating a chip scale package using wafer level processing'20077,169,693'Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same'20077,166,915'Multi-chip module system'20077,166,925'Semiconductor devices having stereolithographically fabricated protective layers thereon through which contact pads are exposed and assemblies including the same'20077,165,322'Process of forming socket contacts'20077,162,796'Method of making an interposer with contact structures'20077,161,250'Projected contact structures for engaging bumped semiconductor devices and methods of making the same'20077,160,795'Method and structures for reduced parasitic capacitance in integrated circuit metallizations'20077,159,311'Method of making an interposer with contact structures'20077,157,364'Method for forming metal contacts on a substrate'20077,156,362'Method and apparatus for forming metal contacts on a substrate'20077,156,361'Method and apparatus for forming metal contacts on a substrate'20077,153,164'Method and apparatus for forming modular sockets using flexible interconnects and resulting structures'20067,154,354'High permeability layered magnetic films to reduce noise in high speed interconnection'20067,155,300'Method for using data regarding manufacturing procedures integrated circuits (IC\'s) have undergone, such as repairs, to select procedures the IC\'s will undergo, such as additional repairs'20067,148,715'Systems and methods for testing microelectronic imagers and microfeature devices'20067,141,994'Air socket for testing integrated circuits'20067,138,653'Structures for stabilizing semiconductor devices relative to test substrates and methods for fabricating the stabilizers'20067,131,195'Method for forming metal contacts on a substrate'20067,129,725'Semiconductor test interconnect with variable flexure contacts having polymer material'20067,129,156'Method for fabricating a silicon carbide interconnect for semiconductor components using heating'20067,129,114'Methods relating to singulating semiconductor wafers and wafer scale assemblies'20067,126,224'Semiconductor substrate-based interconnection assembly for semiconductor device bearing external connection elements'20067,120,513'Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as repairs, to select procedures the ICS will undergo, such as additional repairs'20067,115,961'Packaged microelectronic imaging devices and methods of packaging microelectronic imaging devices'20067,115,495'Methods of making projected contact structures for engaging bumped semiconductor devices'20067,112,878'Die stacking scheme'20067,109,068'Through-substrate interconnect fabrication methods'20067,105,411'Methods of forming a transistor gate'20067,095,106'Collars, support structures, and forms for protruding conductive structures'20067,094,108'Apparatus for forming modular sockets using flexible interconnects and resulting structures'20067,093,358'Method for fabricating an interposer'20067,090,750'Plating'20067,091,622'Semiconductor device, ball grid array connection system, and method of making'20067,091,124'Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices'20067,087,984'Methods for protecting intermediate conductive elements of semiconductor device assemblies'20067,087,511'Method for conducting heat in a flip-chip assembly'20067,084,012'Programmed material consolidation processes for protecting intermediate conductive structures'20067,084,351'Electrical device allowing for increased device densities'20067,082,033'Removing heat from integrated circuit devices mounted on a support structure'20067,071,557'Metallization structures for semiconductor device interconnects, methods for making same, and semiconductor devices including same'20067,069,638'Air socket for testing integrated circuits'20067,064,006'Multiple die stack apparatus employing T-shaped interposer elements'20067,061,109'Semiconductor substrate-based BGA interconnection for testing semiconductor devices'20067,061,092'High-density modularity for ICS'20067,049,840'Hybrid interconnect and system for testing semiconductor dice'20067,049,206'Device isolation for semiconductor devices'20067,043,831'Method for fabricating a test interconnect for bumped semiconductor components by forming recesses and cantilevered leads on a substrate'20067,041,537'Method for fabricating semiconductor component with on board capacitor'20067,041,533'Stereolithographic method for fabricating stabilizers for semiconductor devices'20067,041,513'Methods for forming semiconductor devices so as to stabilize the same when positioned face-down over test substrates'20067,040,930'Modular sockets using flexible interconnects'20067,033,920'Method for fabricating a silicon carbide interconnect for semiconductor components'20067,011,532'Spring element for use in an apparatus for attaching to a semiconductor and a method of making'20067,008,823'Die stacking scheme'20067,008,824'Method of fabricating mounted multiple semiconductor dies in a package'20067,002,362'Test system for bumped semiconductor components'20067,002,248'Semiconductor components having multiple on board capacitors'20066,998,344'Method for fabricating semiconductor components by forming conductive members using solder'20066,995,577'Contact for semiconductor components'20066,982,564'Semiconductor test interconnect with variable flexure contacts'20066,980,017'Test interconnect for bumped semiconductor components and method of fabrication'20056,980,014'Interposer and methods for fabricating same'20056,979,895'Semiconductor assembly of stacked substrates and multiple semiconductor dice'20056,979,607'Technique to control tunneling currents in DRAM capacitors, cells, and devices'20056,975,030'Silicon carbide contact for semiconductor components'20056,972,249'Use of nitrides for flip-chip encapsulation'20056,970,053'Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection'20056,963,127'Protective structures for bond wires'20056,960,924'Electrical contact'20056,955,979'Methods for making metallization structures for semiconductor device interconnects'20056,953,995'Hermetic chip in wafer form'20056,952,054'Semiconductor package having interconnect with conductive members'20056,946,732'Stabilizers for flip-chip type semiconductor devices and semiconductor device components and assemblies including the same'20056,946,378'Methods for fabricating protective structures for bond wires'20056,939,145'Spring element for use in an apparatus for attaching to a semiconductor and a method of making'20056,939,744'Use of palladium in IC manufacturing with conductive polymer bump'20056,932,077'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions and dicing apparatus'20056,919,220'Method of making chip package with grease heat sink'20056,917,107'Board-on-chip packages'20056,914,278'High permeability thin films and patterned thin films to reduce noise in high speed interconnections'20056,913,997'Method of using tantalum-aluminum-nitrogen material as diffusion barrier and adhesion layer in semiconductor devices'20056,914,198'Electrical device allowing for increased device densities'20056,913,988'Methods for fabricating semiconductor device test apparatus that include protective structures for intermediate conductive elements'20056,911,735'Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same'20056,911,723'Multiple die stack apparatus employing T-shaped interposer elements'20056,909,055'Electrical device allowing for increased device densities'20056,909,196'Method and structures for reduced parasitic capacitance in integrated circuit metallizations'20056,906,417'Ball grid array utilizing solder balls having a core material covered by a metal layer'20056,906,402'High permeability thin films and patterned thin films to reduce noise in high speed interconnections'20056,903,003'High permeability composite films to reduce noise in high speed interconnects'20056,903,444'High permeability thin films and patterned thin films to reduce noise in high speed interconnections'20056,900,116'High permeability thin films and patterned thin films to reduce noise in high speed interconnections'20056,900,079'Method for fabricating a chip scale package using wafer level processing'20056,900,077'Methods of forming board-on-chip packages'20056,899,797'Apparatus for continuous processing of semiconductor wafers'20056,897,667'Test system for silicon substrate having electrical contacts'20056,897,571'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'20056,893,961'Methods for making metallization structures for semiconductor device interconnects'20056,893,904'Stereolithographic methods of fabricating semiconductor devices having protective layers thereon through which contact pads are exposed'20056,893,952'Methods of forming a ball grid array including a non-conductive polymer core and a silver or silver alloy outer layer'20056,890,787'Methods for protecting intermediate conductive elements of semiconductor device assemblies'20056,891,248'Semiconductor component with on board capacitor'20056,887,763'Method for using thin spacers and oxidation in gate oxides'20056,884,706'High permeability thin films and patterned thin films to reduce noise in high speed interconnections'20056,884,658'Die stacking scheme'20056,882,167'Method of forming an electrical contact'20056,881,663'Methods of fabricating silicide pattern structures'20056,876,089'Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer'20056,873,046'Chip-scale package and carrier for use therewith'20056,873,036'Die stacking scheme'20056,861,745'Method and apparatus for conducting heat in a flip-chip assembly'20056,861,763'Semiconductor devices having stereolithographically fabricated protective layers thereon through which contact pads are exposed and assemblies including the same'20056,853,069'Packaged die on PCB with heat sink encapsulant and methods'20056,853,210'Test interconnect having suspended contacts for bumped semiconductor components'20056,852,613'High permeability thin films and patterned thin films to reduce noise in high speed interconnections'20056,853,211'Method and system having switching network for testing semiconductor components on a substrate'20056,846,738'High permeability composite films to reduce noise in high speed interconnects'20056,847,110'Method and apparatus for conducting heat in a flip-chip assembly'20056,844,256'High permeability composite films to reduce noise in high speed interconnects'20056,841,868'Memory modules including capacity for additional memory'20056,835,643'Method of improving copper interconnects of semiconductor devices for bonding'20046,833,317'High permeability composite films to reduce noise in high speed interconnects'20046,833,613'Stacked semiconductor package having laser machined contacts'20046,831,472'Method of forming an electrical contact'20046,825,550'Board-on-chip packages with conductive foil on the chip surface'20046,815,804'High permeability composite films to reduce noise in high speed interconnects'20046,815,251'High density modularity for IC\'s'20046,815,314'Hermetic chip and method of manufacture'20046,815,817'Underfill of a bumped or raised die utilizing barrier adjacent to the side wall of a flip-chip'20046,812,146'Chemical vapor deposition process for depositing titanium nitride films from an organo-metallic compound'20046,806,493'Spring element for use in an apparatus for attaching to a semiconductor and a method of attaching'20046,798,224'Method for testing semiconductor wafers'20046,794,735'High permeability composite films to reduce noise in high speed interconnects'20046,794,224'SEMICONDUCTOR DEVICE INCLUDING LEADS IN COMMUNICATION WITH CONTACT PADS THEREOF AND A STEREOLITHOGRAPHICALLY FABRICATED PACKAGE SUBSTANTIALLY ENCAPSULATING THE LEADS AND METHODS FOR FABRICATING THE SAME'20046,794,749'Chip package with grease heat sink'20046,791,185'Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer'20046,787,888'High permeability composite films to reduce noise in high speed interconnects'20046,785,144'High density stackable and flexible substrate-based devices and systems and methods of fabricating'20046,782,613'Method of making an interposer with contact structures'20046,780,746'Method for fabricating a chip scale package using wafer level processing and devices resulting therefrom'20046,773,965'Semiconductor device, ball grid array connection system, and method of making'20046,760,970'Method for forming modular sockets using flexible interconnects and resulting structures'20046,762,502'Semiconductor device packages including a plurality of layers substantially encapsulating leads thereof'20046,758,696'Method and apparatus for forming modular sockets using flexible interconnects and resulting structures'20046,751,859'Method for forming modular sockets using flexible interconnects and resulting structures'20046,744,346'Electronic device workpieces, methods of semiconductor processing and methods of sensing temperature of an electronic device workpiece'20046,740,578'Methods of fabricating semiconductor substrate-based BGA interconnections'20046,735,855'Methods for electrical connector'20046,730,526'Multi-chip module system and method of fabrication'20046,730,543'Methods for multiple die stack apparatus employing'20046,729,027'Method of forming recessed socket contacts'20046,725,536'Methods for the fabrication of electrical connectors'20046,720,652'Apparatus providing redundancy for fabricating highly reliable memory modules'20046,717,422'Air socket for testing integrated circuits'20046,717,245'Chip scale packages performed by wafer level processing'20046,716,745'Silicide pattern structures and methods of fabricating the same'20046,713,879'Semiconductor substract with substantially matched lines'20046,709,878'Electronic device workpieces, methods of semiconductor processing and methods of sensing temperature of an electronic device workpiece'20046,708,399'Method for fabricating a test interconnect for bumped semiconductor components'20046,707,141'Multi-chip module substrate for use with leads-over chip type semiconductor devices'20046,703,640'Spring element for use in an apparatus for attaching to a semiconductor and a method of attaching'20046,703,714'Methods for fabricating flip-chip devices and preventing coupling between signal interconnections'20046,696,109'Chemical vapor deposition process for depositing titanium silicide films from an organometallic compound'20046,696,669'Circuit and method for heating an adhesive to package or rework a semiconductor die'20046,693,349'Semiconductor chip package having a leadframe with a footprint of about the same size as the chip'20046,691,696'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions'20046,687,989'Method for fabricating interconnect having support members for preventing component flexure'20046,687,978'Method of forming tester substrates'20046,690,184'Air socket for testing integrated circuits'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2021Patents assigned to MICRON TECHNOLOGY INC (694)· patent assignee history
1995–2021Based in Boise, ID, US· patent location history
1999Based in Bosie, ID, US· patent location history
2007–2018Patents assigned to AKRAM SALMAN (19)· patent assignee history
2009–2013Patents assigned to APTINA IMAGING CORP (6)· patent assignee history
2012–2014Patents assigned to KIRBY KYLE K (5)· patent assignee history
2016–2017Patents assigned to KONINKLIJKE PHILIPS NV (5)· patent assignee history
2016–2020Based in Eindhoven, NL· patent location history
2017–2018Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 694 | 1995–2021 |
| AKRAM SALMANself | 19 | 2007–2018 |
| APTINA IMAGING CORP | 6 | 2009–2013 |
| KIRBY KYLE K | 5 | 2012–2014 |
| KONINKLIJKE PHILIPS NV | 5 | 2016–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 715 | 1995–2021 |
| Eindhoven, NL | 6 | 2016–2020 |
| San Jose, California, US | 2 | 2017–2018 |
| Bosie, ID, US | 1 | 1999 |