Variable output charge pump circuit

Embodiments of the present invention relate to circuits for providing operational voltages in complementary metal-oxide semiconductor (CMOS) circuits. In particular, embodiments of the present invention relate to a charge pump circuit with a variable output.

As the operating voltages for CMOS transistor circuits have decreased, variations in the threshold voltages for the transistors have become more significant. Although low operating voltages offer the potential for reduced power consumption, threshold voltage variations due to process and environmental variables often prevent optimum efficiency and performance from being achieved due to increased leakage currents.

Threshold voltage variations may be compensated for by body biasing. In typical CMOS transistors, the body of the transistor is connected to a supply rail (e.g., V ss for NMOS, and V dd for PMOS). In this configuration the transistor is often treated as a three terminal device.

Body biasing introduces a reverse bias potential between the bulk and the source of the transistor that allows the threshold voltage of the transistor to be adjusted electrically. The purpose of body biasing is to compensate for: 1) process variations; 2) temperature variations; 3) supply voltage variations; 4) changes in frequency of operation; and 5) changing levels of switching activity.

Whereas the typical CMOS transistor is a three-terminal device, the body biased CMOS transistor is a four-terminal device, and thus requires a more complex interconnect scheme. Connections for body biasing may be made on the substrate surface using conventional metal/dielectric interconnects similar to those used for typical gate, drain, and source connections, or they may be made using buried complementary well structures (e.g., buried N-well).

Prior Art FIG. 1 shows a conventional CMOS inverter 100 . A P-type substrate 105 supports an NFET 110 and a PFET 120 . The NFET 110 comprises a gate 112 , source 113 , and drain 114 . The PFET 120 resides in an n-well 115 , and comprises a gate 122 , drain 123 , and a source 124 . Body bias can provided to the PFET 120 through a direct bias contact 135 a , or by a buried n-well 125 using contact 135 b . Similarly, body bias may be provided to the NFET 110 by a surface contact 140 a , or by a backside contact 140 b . An aperture 130 is provided in the buried n-well 125 so that the bias potential reaches the NFET 110 . In general, a PFET 120 or an NFET 110 will be biased by one of the alternative contacts shown.

In a complex integrated circuit different parts of the circuit may require different bias voltages, and a given part of the circuit may also require a variable bias. A variable bias is particularly desirable when minimum power dissipation is required in a circuit.

Thus, a need exists for a bias voltage source for use in CMOS integrated circuits that provides a variable output that can be controlled to minimize power dissipation in the biased device.

Accordingly, embodiments of the present invention provide charge pump circuits that may be used for biasing PFETs and NFETs. Two charge pump arrays are used under common control to provide bias to a CMOS circuit.

In one embodiment of the present invention, a first array of basic charge pump units are connected in parallel to provide bias for an N-well. The input of the first array is connected to a first output of a clock divider circuit having a first selectable output frequency. A second array of basic charge pump units are connected in parallel to provide bias for a P-type substrate. The input of the second array is connected to a second output of the clock divider circuit having a second selectable output frequency.

In another embodiment, one or more of the basic charge pump units making up the aforementioned first and second charge pump arrays has an enable input allowing its output current contribution to be added or subtracted from the total array output.

In a further embodiment, charge pump controller is coupled to a dual output charge pump circuit having a first output coupled to an N-well and a second output coupled to a P-type substrate. A single supply voltage and a single clock frequency input are provided to the dual output charge pump circuit. An output monitor providing feedback may be coupled between the outputs of the dual output charge pump circuit and the charge pump controller.

These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention:

Prior Art FIG. 1 shows a conventional CMOS inverter with bias connections for a P-type substrate and an N-well.

FIG. 2 shows a diagram of a dual variable output charge pump circuit for CMOS circuits in accordance with an embodiment of the present claimed invention.

FIG. 3 shows a diagram of a portion of the dual variable output charge pump circuit of FIG. 2 , in accordance with an embodiment of the present claimed invention.

In the following detailed description of the present invention, a variable output charge pump circuit, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one skilled in the art that the present invention may be practiced without these specific details. In other instances well known methods, procedures, components, and circuit elements have not been described in detail as not to unnecessarily obscure aspects of the present invention.

FIG. 2 shows a diagram 200 of a dual variable output charge pump circuit for CMOS circuits. A charge pump controller 205 provides control of a dual output charge pump circuit 210 . The dual output charge pump circuit 210 has a supply voltage input V DD and a primary clock frequency input φ. The dual output charge pump circuit 210 includes a number of capacitors that are switched at a frequency derived from φ. The number of capacitors being charged and the charging frequency are controlled by the charge pump controller 205 .

The dual output charge pump circuit has two outputs that are independently controlled, with the first output being used to bias a substrate (e.g., P-type substrate 220 ) and the second output being used to bias a complementary well resident in the substrate (e.g., N-well 215 ).

The inverter shown in FIG. 1 is a basic building block for logic circuits. In an embodiment of the present invention, N-well 215 may correspond to N-well 115 and P-type substrate 220 may correspond to P-type substrate 105 . Power dissipation in a CMOS inverter may be reduced by controlling the bias of the PFET and NFET. Thus embodiments of the present invention may be used to reduce power dissipation in integrated circuits such as microprocessors.

The charge pump controller 205 of FIG. 2 may be a dedicated programmable logic circuit, or it may be a general purpose microprocessor that executes instruction for controlling the a dual output charge pump circuit 210 in addition to performing other functions. The N-well 215 and P-substrate 220 may include transistors that are part of the charge pump controller 205 .

An output monitor 225 may be used to provide feedback from the outputs of the dual output charge pump circuit 210 and the charge pump controller 205 . Typically the operating parameters (e.g. programming) of the charge pump controller will be determined a priori from modeling or previous testing. Feedback from the output monitor 225 allows the outputs of the dual output charge pump circuit to be adjusted. Thus, variations due to processing or temperature may be compensated for.

FIG. 3 shows an example of the dual output charge pump circuit 210 of FIG. 2 . A clock divider 305 has a control input and a primary clock input frequency φ. Basic V DD supply is not shown. The clock divider 305 has a first output φ N and a second output φ P . Each of the two outputs is produced by dividing the primary frequency φ and are independently selectable.

In one embodiment, the selectable clock divider output frequencies form a binary progression, that is, each of the output frequencies is half or twice the value of another frequency. The output frequencies may be obtained from a series of taps on a sequence of dividers. For example, a series of eight divide-by-two taps could be used to provide a binary progression, and would also provide a frequency output ratio of 256 to 1.

Selectable frequency output φ N is coupled to a first charge pump array 310 . Charge pump array 310 includes an array of N basic charge pump units A 1 to A N connected in parallel. The basic charge pump unit is preferably a charge pump design that can be implemented using a CMOS process.

Basic charge pump units A 1 and A N each have an enable input; however, some of the units in the array 310 may not have an enable input. The enable input allows the output of each basic charge pump unit to be added or subtracted from the total output of the array 310 .

Each of the basic charge pump units A 1 to A N may have the same nominal output, or they may be designed with different output values. For example, a binary progression may be used for the output values, thus providing improved output selection range. For an eight unit array having normalized output values of 1, 2, 4, 8, 16, 32, and 128, the output may be adjusted from 0 to 255 in increments of one. The outputs of the individual basic charge pump units A 1 to A N are connected in parallel and coupled to provide a single bias output (e.g., N-well bias).

A second charge pump array 315 is connected to second selectable frequency output φ P . The second charge pump array 315 includes an array of basic charge pump units B 1 to B M . N and M are integers and may or may not have the same value. Basic charge pump units B 1 to B M are shown without enable inputs and are always operational; however, other basic charge pump units in array 315 may have enable inputs.

In general, the individual size, number, and enablement of basic charge pump units within array 310 or 315 will be determined by the range and resolution requirements for the array. Typically, the requirements for well bias will be different from the requirements for substrate bias.

The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.