Power saving in FPU with gated power based on opcodes and data

1. Field of the Invention

The invention relates generally to microprocessors and, more particularly, to power management of functional units of microprocessors.

2. Description of the Related Art

Power consumption of microprocessors is becoming an important concern for designers. First, the market for battery-powered systems (e.g., mobile systems) is expanding at a rapid rate, in which systems battery life is important and power is at a premium. Second, having complex designs and large on-chip caches, modern microprocessor chips can ill afford to overheat. Therefore, power consumption is a primary design factor that determines the commercial success of most modern microprocessor products.

Generally, microprocessors have one or more functional units, which execute instructions. These functional units in general and floating-point units (FPUs) in particular are the main culprits in power consumption of microprocessors.

Therefore, a need exists for reducing power consumption in the functional units of microprocessors without affecting the performance. Additionally, there is a need for reducing cooling demand. Further, there is a need for reducing device junction temperature for improved reliability.

The present invention provides a method and an apparatus for saving power in a microprocessor. The microprocessor has at least one functional unit, which has a plurality of blocks. The blocks each include a plurality of sub-blocks. It is determined whether there is any instruction for the functional unit. Upon a determination that there is no instruction for the functional unit, the functional unit is shut down. Upon a determination that there is at least one instruction for the functional unit, at least one inactive block of the functional unit is shut down based on the instruction.

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a clock gating mechanism for a functional unit of a microprocessor;

FIGS. 2A–2D each represent a block diagram illustrating different clock gating modes for saving power consumption in an adder block of a floating-point unit (FPU);

FIGS. 3A–3F each represent a block diagram illustrating different clock gating modes for saving power consumption in a floating-point unit (FPU) pipeline; and

FIG. 4 is a flow diagram illustrating a multilevel clock gating scheme.

In the following discussion, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present invention in unnecessary detail.

It is further noted that, unless indicated otherwise, all functions described herein may be performed in either hardware or software, or some combination thereof. In a preferred embodiment, however, the functions are performed by a processor such as a computer or an electronic data processor in accordance with code such as computer program code that, for example, resides on a computer readable medium or is stored on a computer readable medium, software, and/or integrated circuits that are coded to perform such functions, unless indicated otherwise.

Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a clock gating mechanism for a functional unit of a microprocessor. The clock gating mechanism 100 comprises an operational code 102 , an operand 104 , a control logic 106 , a sequencer 108 , a functional unit 110 , and optionally a lookup table 112 . The operational code 102 refers to an instruction to be executed in the function unit 110 and is also known as OPCODE. The operand 104 refers to a data input to be used in the execution of the operational code 102 . The control logic 106 and the sequencer 108 are coupled to the functional unit 110 . The control logic 106 and the sequencer 108 are shown to be coupled to each other. Alternatively, the control logic 106 and the sequencer 108 may be implemented in a single block (not shown).

The control logic 106 and the functional unit 110 are configured to receive the operational code 102 and the operand 104 . The control logic 106 is configured to receive the operational code 102 and the operand 104 and to generate control signals (not shown) that control the clock gating of the functional unit 110 . Note that an important example of the functional unit 110 is a floating-point unit (FPU).

In one embodiment of the present invention, the control signals are determined based on the operational code 102 , the operand 104 , and/or the execution cycle of the operational code 102 . In another embodiment, the control logic 106 is coupled to the optional lookup table 112 , which contains a set of predetermined control signals corresponding to combinations of the operational code 102 and the operand 104 .

The functional unit 110 includes N cycles, each of which cycles has at least one latch (not show). The sequencer 108 is configured to detect which cycle among the N cycles the operand is currently in and to generate activation signals for latches (not shown). Preferably, the sequencer 108 is coupled to each cycle of the functional unit 110 .

Now referring to FIGS. 2A–2D , shown is a block diagram illustrating an adder block 200 in different clock gating modes for saving power consumption. The adder block 200 is shown to describe part of a functional unit 110 of FIG. 1 . Preferably, the adder block 200 is part of a floating-point unit (FPU) (not shown). As is well known in the art, an FPU consumes more power than any other type of functional unit. The adder block 200 comprises three parallel portions: an incrementer portion 202 , a compound adder portion 204 , and a sticky and select logic portion 206 . The adder block 200 has two cycles. The first cycle is implemented by latches 208 A, 208 B, and 208 C. The second cycle is implemented by latches 210 A, 210 B, and 210 C. A first incrementer stage (INC) 212 of the incrementer portion 202 is coupled to and gated by the latch 208 A. A second incrementer stage (INC) 214 of the incrementer portion 202 is coupled to and gated by the latch 210 A. The latch 210 A is also coupled to the first INC 212 .

Similarly, a first compound adder stage (CADD) 216 of the compound adder portion 204 is coupled to and gated by the latch 208 B. A second compound adder stage (CADD) 218 of the compound adder portion 204 is coupled to and gated by the latch 210 B. The latch 210 B is also coupled to the first CADD 216 . A sticky logic 220 is coupled to and gated by the latch 208 C. A select logic 222 is coupled to and gated by the latch 210 C. The latch 210 C is also coupled to the sticky logic 220 .

FIGS. 2A–2D show different clock gating modes of the adder block 200 for different types of operations engaged in the adder block 200 and/or different values of operands used in the operations. For illustration purposes, the adder block 200 is used to calculate AB+C, where A, B, and C each are n-bit wide operands. In a single precision, for example, n is 24 . In this instance, AB represents a product of A and B, whereas C represents an addend. Here, the product AB is 2 n bit wide. Note that only minimum details are shown for the adder block 200 for purposes of illustrating the present invention. Also note that a latch turned off is lightly shaded throughout FIGS. 2A–2D and 3 A– 3 F.

Specifically, FIG. 2A applies to any floating-point multiply-add type of operation, when the addend C is much larger than the product AB. Here, the addend C is considered much larger than the product AB if the least significant bit (LSB) of the addend C is x-bit higher in the order of magnitude in the binary scale than the most significant bit (MSB) of the product AB. Preferably, x is 2. In this case, the first CADD 216 , the second CADD 218 , and the sticky logic 220 can be shut down. This is done by gating off the latches 208 B, 208 C, and 210 B, as shown in FIG. 2A .

FIG. 2B applies to any floating-point multiply-add type of operation, when the addend C is larger than the product AB but the addend C and the product AB overlap. In this case, the sticky logic 220 can be shut down. This is done by gating off the latch 208 C, as shown in FIG. 2B .

FIG. 2C applies to any floating-point multiply-add type of operation, when the addend C is no larger than the product AB. FIG. 2C also applies to conversions from floating-point to integer. Here, the addend C is considered no larger than the product AB if the most significant bit (MSB) of the addend C is not higher than the MSB of the product AB by any more than x bits. As before, x is preferably two. In this case, the first INC 212 and the second INC 214 can be shut down. This is done by gating off the latches 208 A and 210 A, as shown in FIG. 2C .

FIG. 2D applies to floating-point multiplications, integer multiplications and conversions from integer to floating-point. In this case, the first INC 212 , the second INC 214 , and the sticky logic 220 can be shut down. This is done by gating off the latches 208 A, 210 A, and 208 C, as shown in FIG. 2D .

Now referring to FIGS. 3A–3F , shown is a block diagram illustrating a floating-point unit (FPU) pipeline 300 in different clock gating modes for saving power consumption. Note that the FPU pipeline 300 has ten cycles. The first cycle is implemented by an operational latch 302 . The second cycle is implemented by latches 304 A and 304 B. The third cycle is implemented by latches 306 A, 306 B, 306 C, 306 D, and 306 E. The fourth cycle is implemented by latches 308 A, 308 B, 308 C, 308 D, and 308 E. The fifth cycle is implemented by latches 310 A, 310 B, 310 C, and 310 D. The sixth cycle is implemented by latches 312 A, 312 B, 312 C, and 312 D. The seventh cycle is implemented by latches 314 A, 314 B, 314 C, and 314 D. The eighth cycle is implemented by latches 316 A, 316 B, and 316 C. The ninth cycle is implemented by latches 318 A, 318 B, and 318 C. And the tenth cycle is implemented by latches 320 A, 320 B, and 320 C.

In the first cycle, the operational latch 302 is coupled to and drives both a format block 322 and a special cases block 323 . The latch 304 A is coupled to drive a first EXP block 324 . Similarly, the latch 306 A is coupled to drive a second EXP block 326 ; the latch 308 A is coupled to drive a third EXP block 328 ; the latch 310 A is coupled to drive a fourth EXP block 330 ; the latch 312 A is coupled to drive a fifth EXP block 332 ; the latch 314 A is coupled to drive a sixth EXP block 334 ; the latch 316 A is coupled to drive a seventh EXP block 336 ; and the latch 318 A is coupled to drive an eighth EXP block 338 .

The latch 304 A is also coupled to drive a first ALIGN block 340 ; the latch 306 B is coupled to drive a second ALIGN block 342 ; and the latch 308 B is coupled to drive a third ALIGN block 344 . The latch 304 A is also coupled to drive a first BYPASS block 346 . The latch 304 A is finally coupled to drive a first MUL block 348 ; the latch 306 D is coupled to drive a second MUL block 350 ; and the latch 308 D is coupled to drive a third MUL block 352 . The latch 304 B is coupled to drive a SPEC. block 354 . The latch 314 D is coupled to drive a second BYPASS block 356 .

The latches 310 B and 310 C are coupled to drive a first LZA block 358 . The latch 312 B is coupled to drive a second LZA block 360 . The latches 310 B and 310 C are also coupled to drive a first ADD block 362 . The latch 312 C is coupled to drive a second ADD block 364 . The latches 314 B and 314 C are coupled to drive a NORMALIZE block 366 . The latch 316 B is coupled to a first ROUND block 368 . The latch 318 B is coupled to a second ROUND block 370 . The latches 320 A, 320 B, and 320 C are coupled to drive a RESULT SELECT block 372 .

FIG. 3A illustrates a gating mode on a floating-point multiply-add operation with standard operands and results with no special values. In this case, most of the blocks are needed; but two bypass paths including the first BYPASS block 346 and the second BYPASS block 356 can be shut down. Hence, the latches 306 C, 308 C, 308 E, 310 D, 312 D, 314 D, 316 C, 318 C, and 320 C can be turned off, as shown in FIG. 3A .

FIG. 3B illustrates any floating-point operations with special inputs and/or results. In this case, only the special case logic is needed. Except for that logic and the corresponding bypass, the rest logic blocks of the FPU can be shut down. Hence, the latches 306 A– 306 D, 308 A– 308 D, 310 A– 310 C, 312 A– 312 C, 314 A– 314 C, 316 A, 316 B, 318 A, 318 B, 320 A, and 320 B can be turned off, as shown in FIG. 3B .

FIG. 3C illustrates a floating-point multiply operation with standard operands and results. In this case, the aligner and the bypassing of the special case values can be shut down. Hence, the latches 306 B, 308 B, 308 E, 310 D, 312 D, 314 D, 316 C, 318 C, and 320 C can be turned off, as shown in FIG. 3C .

FIG. 3D illustrates a floating-point operation of addition, subtraction, or conversion to integer with standard operands. In this case, the multiplier and the bypassing of the special case values can be shut down. Hence, the latches 306 D, 308 D, 308 E, 310 D, 312 D, 314 D, 316 C, 318 C, and 320 C can be turned off, as shown in FIG. 3D .

FIG. 3E illustrates a conversion operation from integer to floating-point for standard inputs. In this case, multiplier, aligner, and bypassing of the special case values can be shut down. Hence, the latches 306 B, 306 D, 308 B, 308 D, 308 E, 310 D, 312 D, 314 D, 316 C, 318 C, and 320 C can be turned off, as shown in FIG. 3E .

FIG. 3F illustrates integer multiply and multiply-add operations. In this case, aligner, exponent path, rounder, and the upper part of the special case bypass logic can be shut down. Hence, the latches 304 B, 306 A, 306 B, 306 E, 308 A, 308 B, 308 E, 310 A, 310 D, 312 A, 312 D, 314 A, 316 A, 316 B, 318 A, 318 B, 320 A, and 320 B can be turned off, as shown in FIG. 3F .

Now referring to FIG. 4 , a flow diagram illustrates a multilevel clock gating scheme 400 . In step 402 , it is determined whether there is any instruction for a functional unit. Preferably, the functional unit is a floating-point unit (FPU). Upon a determination that there is no instruction for the functional unit, in step 404 , the entire functional unit is shut down. Upon a determination that there is at least one instruction for the functional unit, in step 406 , at least one inactive block of the functional unit is shut down based on instruction type and/or values of operands. Preferably, the execution cycle of the instruction may also be considered in addition to the instruction type and/or values of operands.

In step 408 , for at least one active block of the functional unit, at least one sub-block of the active block is shut down based on instruction type and/or value of the operands. For example, at least one active block is an adder block as shown in FIGS. 2A–2D .

It will be understood from the foregoing description that various modifications and changes may be made in the preferred embodiment of the present invention without departing from its true spirit. This description is intended for purposes of illustration only and should not be construed in a limiting sense. The scope of this invention should be limited only by the language of the following claims.