Inventor
Silvia M. Mueller
Inventor
Altdorf, DE
Overview
Patents· 118 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing84%
G06NComputing arrangements based on specific computational models4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
H03MCoding2%
H04LTransmission of digital information, e.g. telegraphic communication2%
G01RMeasuring electric variables1%
G11BInformation storage based on relative movement between record carrier and transducer1%
G11CStatic stores1%
H03KPulse technique1%
PatentTitleYear
11,132,198Instruction handling for accumulation of register results in a microprocessor202111,132,228SMT processor to create a virtual vector register file for a borrower thread from a number of donated vector register files202111,099,853Digit validation check control in instruction execution202111,029,921Performing processing using hardware counters in a computer system202111,023,205Negative zero control in instruction execution202110,990,390Decimal load immediate instruction202110,963,219Hybrid floating point representation for deep learning acceleration202110,929,213Residue prediction of packed data202110,915,385Residue prediction of packed data202110,846,053Underflow/overflow detection prior to normalization202010,846,054Underflow/overflow detection prior to normalization202010,740,098Aligning most significant bits of different sized elements in comparison result vectors202010,713,056Wide vector execution in single thread mode for an out-of-order processor202010,705,847Wide vector execution in single thread mode for an out-of-order processor202010,656,913Enhanced low precision binary floating-point formatting202010,649,730Normalization of a product on a datapath202010,649,738Combined residue circuit protecting binary and decimal data202010,592,208Very low precision floating point representation for deep learning acceleration202010,579,375Method to build reconfigurable variable length comparators202010,572,223Parallel decimal multiplication hardware with a 3x generator202010,558,432Multiply-add operations of binary numbers in an arithmetic unit202010,489,114Shift amount correction for multiply-add201910,489,115Shift amount correction for multiply-add201910,459,689Calculation of a number of iterations201910,430,185Decimal load immediate instruction201910,416,962Decimal and binary floating point arithmetic calculations201910,379,859Inference based condition code generation201910,379,860Inference based condition code generation201910,379,811Normalization of a product on a datapath201910,372,417Multiply-add operations of binary numbers in an arithmetic unit201910,365,892Decimal floating point instructions to perform directly on compressed decimal floating point data201910,346,134Perform sign operation decimal instruction201910,331,408Decimal multiply and shift instruction201910,331,407Tiny detection in a floating-point unit201910,310,936Temporary pipeline marking for processor error workarounds201910,310,815Parallel decimal multiplication hardware with a 3X generator201910,303,438Fused-multiply-add floating-point operations on 128 bit wide operands201910,303,563Initializable repair circuit for selectively replacing a table-driven output201910,303,440Combined residue circuit protecting binary and decimal data201910,296,294Multiply-add operations of binary numbers in an arithmetic unit201910,241,756Tiny detection in a floating-point unit201910,241,757Decimal shift and divide instruction201910,235,137Decimal shift and divide instruction201910,235,135Normalization of a product on a datapath201910,235,170Decimal load immediate instruction201910,228,910Overflow detection for sign-magnitude adders201910,198,302Residue prediction of packed data201910,175,946Perform sign operation decimal instruction201910,168,993Zero detection of a sum of inputs without performing an addition201910,127,015Decimal multiply and shift instruction201810,101,967Zero detection of a sum of inputs without performing an addition201810,095,475Decimal and binary floating point rounding201810,067,744Overflow detection for sign-magnitude adders20189,959,093Binary fused multiply-add floating-point calculations20189,952,829Binary fused multiply-add floating-point calculations20189,940,199Checking arithmetic computations20189,928,135'Non-local error detection in processor systems'20189,870,200'Decimal and binary floating point rounding'20189,785,435'Floating point instruction with selectable comparison attributes'20179,767,073'Arithmetic operation in a data processing system'20179,753,690'Splitable and scalable normalizer for vector data'20179,734,126'Post-silicon configurable instruction behavior based on input operands'20179,727,399'Residue-based checking of a shift operation'20179,720,648'Optimized structure for hexadecimal and binary multiplier array'20179,697,074'Non-local error detection in processor systems'20179,684,514'Inference based condition code generation'20179,684,515'Inference based condition code generation'20179,658,828'Decimal and binary floating point rounding'20179,588,852'Temporary pipeline marking for processor error workarounds'20179,575,836'Temporary pipeline marking for processor error workarounds'20179,563,400'Optimized structure for hexadecimal and binary multiplier array'20179,529,664'Using error correcting codes for parity purposes'20169,513,987'Using error correcting codes for parity purposes'20169,507,659'Temporary pipeline marking for processor error workarounds'20169,430,190'Fused multiply add pipeline'20169,361,268'Splitable and scalable normalizer for vector data'20169,361,267'Splitable and scalable normalizer for vector data'20169,348,796'Arithmetic operation in a data processing system'20169,256,397'Fused multiply-adder with booth-encoding'20169,244,654'Decimal floating-point quantum exception detection'20169,128,759'Decimal multi-precision overflow and tininess detection'20159,128,758'Encoding densely packed decimals'20159,122,517'Fused multiply-adder with booth-encoding'20158,977,835'Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency'20158,954,485'Range check based lookup tables'20158,949,575'Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency'20158,914,431'Range check based lookup tables'20148,909,994'Dynamic hardware trace supporting multiphase operations'20148,892,958'Dynamic hardware trace supporting multiphase operations'20148,626,807'Reuse of rounder for fixed conversion of log instructions'20148,578,196'Zero indication forwarding for floating point unit power reduction'20138,566,383'Distributed residue-checking of a floating point unit'20138,554,822'Decimal adder with end around carry'20138,495,124'Decimal floating point mechanism and process of multiplication without resultant leading zero detection'20138,407,275'Fast floating point compare with slower backup for corner cases'20138,352,531'Efficient forcing of corner cases in a floating point rounder'20138,346,828'System and method for storing numbers in first and second formats in a register file'20138,332,453'Shifter with all-one and all-zero detection using a portion of partially shifted vector and shift amount in parallel to generated shifted result'20128,291,003'Supporting multiple formats in a floating point processor'20128,255,726'Zero indication forwarding for floating point unit power reduction'20128,229,989'Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units'20128,219,605'Decimal floating-pointing quantum exception detection'20128,166,085'Reducing the latency of sum-addressed shifters'20128,131,795'High speed adder design for a multiply-add based floating point unit'20128,032,854'3-stack floorplan for floating point unit'20117,694,112'Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation'20107,490,119'High speed adder design for a multiply-add based floating point unit'20097,469,265'Methods and apparatus for performing multi-value range checks'20087,461,117'Floating point unit with fused multiply add and method for calculating a result with a floating point unit'20087,447,725'Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units'20087,406,589'Processor having efficient function estimate instructions'20087,392,270'Apparatus and method for reducing the latency of sum-addressed shifters'20087,290,023'High performance implementation of exponent adjustment in a floating point design'20077,245,159'Protecting one-hot logic against short-circuits during power-on'20077,237,163'Leakage current reduction system and method'20077,149,877'Byte execution unit for carrying out byte instructions in a processor'20067,137,021'Power saving in FPU with gated power based on opcodes and data'20067,058,830'Power saving in a floating point unit using a multiplier and aligner bypass'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2021Patents assigned to IBM (118)· patent assignee history
2006–2012Based in St. Ingbert, DE· patent location history
2007–2021Based in Altdorf, DE· patent location history
2012–2016Patents assigned to MUELLER SILVIA MELITTA (12)· patent assignee history
2012–2016Patents assigned to MUELLER SILVIA M (11)· patent assignee history
2012–2014Patents assigned to PREISS JOCHEN (9)· patent assignee history
2012–2016Patents assigned to BOERSMA MAARTEN J (8)· patent assignee history
2012–2019Based in Boeblingen, DE· patent location history
2016Based in Schoenaicher, DE· patent location history
2017Based in Atdorf, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 118 | 2006–2021 |
| MUELLER SILVIA MELITTAself | 12 | 2012–2016 |
| MUELLER SILVIA Mself | 11 | 2012–2016 |
| PREISS JOCHEN | 9 | 2012–2014 |
| BOERSMA MAARTEN J | 8 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Altdorf, DE | 96 | 2007–2021 |
| Boeblingen, DE | 12 | 2012–2019 |
| St. Ingbert, DE | 6 | 2006–2012 |
| Atdorf, DE | 1 | 2017 |
| Schoenaicher, DE | 1 | 2016 |