High density mask ROM having flat-type bank select

This application is a Continuation-in-Part of application Ser. No. 09/930,306, filed Aug. 16, 2001 now abandoned.

1. Field of the Invention

The invention relates to mask read-only memory, and more particularly to mask read-only memory having flat-type bank select.

2. Description of the Prior Art

There are several read-only memory (ROM) cell structures are well known in application. One approach is referred to as the flat-type ROM design. With the requirement of better memory cell efficiency, the cell pitch and bank height become the key factor to be considered. While the memory cell is shrinking down, the contact size and metal pitch become the limit of it. On the other hand, memory array used to use LOCOS-type MOS for the bank selection transistors, which causes difficulties in the reduction of the layout area.

Memory devices with flat-type ROM design are well documented. For example, a prior technique is illustrated in U.S. Pat. No. 5,117,389 of Yiu, entitled “Flat-Cell Read-Only-Memory Integrated Circuit”. Shown in FIG. 1 , the number of bank selection transistors utilized is reduced in a memory array, and the metal lines are shared between even and odd banks. Access to the metal lines is made through a plurality of LOCOS bank selection transistors connected to every other buried diffusion. By using this architecture, the metal lines are running parallel to the buried diffusion lines. A block select transistor (BWL N ), word select transistor (SWL N ), bank left select transistor (SBL N ) and a bank right select transistor (SBR N ) are required to access a ROM cell. Contacts are made for connecting them by using isolated bank selection transistors. The alternate buried diffusion bit lines are connected through either a buried diffusion region to its left or a buried diffusion region to its right to the metal lines, by means of left-right bit selection transistors. One disadvantage of the ROM design of Yiu is the number of transistor required to access the ROM cell, which affects the overall size of the array. Other peripheral circuits also contribute to the overall array size.

Another design is U.S. Pat. No. 5,621,697 of Weng et al., entitled in “High Density Integrated Circuit with Bank Select Structure”. In this design, the bank selection structure includes bank selection transistors which are located and oriented adjacent diffusion bit lines and intrabank diffusion bit lines. Each intrabank bit lines of a bank extends into neighboring banks either above or below the bank. Interbank bit lines provide reducing the number of bank selection transistors. To improve the vertical pitch, the bank selection transistors are coupled to the metal lines by metal-to-diffusion region contacts.

Therefore, it is desirable to design a high performance ROM that can be manufactured with high yield. It is also desirable to utilize straight metal bit lines to simplify manufacture and increase circuit efficiency. It is also desirable to minimize the number of transistors in an array in order to optimize speed, size, power consumption and ease of fabrication parameters. Furthermore, for reduction of layout area and flexible fabrication, the contact number should be reduced and the metal pitch should be released.

It is one object of the present invention to provide an architecture of a flat-type ROM. The contact and transistor numbers can be reduced, which can further reduce the effect of the metal coupling and have larger cell current.

It is another object of the present invention to provide a structure of a flat-type ROM. The area of the bank layout can be compact in both horizontal and vertical directions, and the metal pitch can be released.

It is another object of the present invention to provide a compact structure of a memory array. The bank selection lines are shared between adjacent two bank arrays, which can reduce the area of the memory array.

The present invention provides a read-only memory array having a flat-type structure. The read-only memory array comprises at least two memory banks having a plurality of memory cells. At least two inter-bank transistors are coupled to the two memory banks and shared by the two memory banks. Each inter-bank transistor is used for enabling to select the memory cells of the two memory banks. At least a contact commonly is coupled to the two memory banks through the two inter-bank transistors.

A better understanding of the invention may be derived by reading the following detailed description with reference to the accompanying drawing wherein:

FIG. 1 is a circuit diagram of a bank array of a read-only memory in accordance with the prior art;

FIG. 2 is a circuit diagram of a bank array of a read-only memory illustrating the layout representation of a preferred embodiment in accordance with the present invention;

FIG. 3 is the plan view of the layout of FIG. 2 ;

FIG. 4 is another circuit diagram of the bank array of a read-only memory illustrating the layout representation of the other preferred embodiment in accordance with the present invention; and

FIG. 5 is the plan view of the layout of FIG. 4 .

While the invention is particularly shown and described with reference to the following preferred embodiment, it will be understood by those skilled in the art that many other modifications and variations may be made thereto without departing from the broader spirit and scope of the invention as set forth in the claims. Use of the disclosed structure or method is not limited to mask read-only memory device, but may also be used in fabricating other types of memory devices with equal architectures. The specification and drawings are according to be regarded as being illustrative, rather than being restrictive.

Furthermore, there is shown a representative portion of a semiconductor structure of the present invention in enlarged. The drawings are not necessarily to scale, as the thickness of the various layers are shown for clarify of illustration and should not be interpreted in a limiting sense. Accordingly, these regions will have dimensions, including length, width and depth, when fabricated in an actual device.

In the present invention, a read-only memory array has a flat-type structure comprising at least two memory banks having a plurality of memory cells. At least two inter-bank transistors are coupled to the two memory banks and shared by the two memory banks. Each inter-bank transistor is used for enabling to select the memory cells of the two memory banks. At least two intra-bank transistors are which each intra-bank transistor is coupled to any one of the two memory banks. At least a contact is commonly coupled to the two memory banks through the two inter-bank transistors and the intra-bank transistors.

The bank array architecture of a memory cell array containing bank selection structure is disclosed in the present invention. The first embodiment shown in FIG. 2 , a first plurality of memory cells MA 1 , MA 2 , MA 3 , MA 4 , are connected in parallel to a second plurality of memory cells MB 1 , MB 2 , MB 3 , MB 4 , and a third plurality of memory cells MC 1 , MC 2 , MC 3 , MC 4 . Each memory cell of the first, second and third plurality of memory cells is coupled to two adjacent lines constituting a memory bank (herein named first memory bank). A memory array consisting of a plurality of memory banks. Furthermore, with their individual gate terminals, the memory cells MA 1 to MA 4 are commonly connected to corresponding word line WL 0 . Similarly, the gate terminals of the memory cells MB 1 to MB 4 are commonly connected to corresponding word line WL 1 , and those of the memory cells MC 1 to MC 4 are commonly connected to corresponding word line WL 2 .

On the other hand, an adjacent memory bank (herein named second memory bank) comprises a first plurality of memory cells MA 1 ′, MA 2 ′, MA 3 ′, MA 4 ′, connected in parallel to a second plurality of memory cells MB 1 ′, MB 2 ′, MB 3 ′, MB 4 ′, and a third plurality of memory cells MC 1 ′, MC 2 ′, MC 3 ′, MC 4 ′. Furthermore, with their individual gate terminals, the memory cells MA 1 ′ to MA 4 ′ are commonly connected to corresponding word line WL 0 ′. Similarly, the gate terminals of the memory cells MB 1 ′ to MB 4 ′ are commonly connected to corresponding word line WL 1 ′, and those of the memory cells MC 1 ′ to MC 4 ′ are commonly connected to corresponding word line WL 2 ′.

Furthermore, an inter-bank selection transistor MS 1 is connected to a bank selection line BS 0 through the gate terminal thereof. Another inter-bank selection transistor MS 0 is connected to another bank selection line BS 1 through the gate terminal thereof. In the present invention, the bank selection lines BS 0 and BS 1 are shared among adjacent memory banks. That is, the bank selection lines BS 0 and BS 1 can be selected for the memory cells of the first and second memory banks.

The metal bit line S 1 is connected to the inter-bank selection transistors MS 0 and MS 1 through a contact 10 . In the present invention, one metal bit line S 1 is at least coupled to the first terminal, such as a drain or source, of the inter-bank selection transistor MS 0 and the second terminal, such as a source or drain, of the inter-bank selection transistor MS 1 through one contact 10 . The second terminal of inter-bank selection transistor MS 0 is commonly connected to the memory cells of the first memory bank through a sub bit line SB 1 and the memory cells of the second memory bank through sub bit line SB 2 ′. Similarly, the first terminal of the inter-bank selection transistor MS 1 is commonly connected to the memory cells of the first memory bank through a sub bit line SB 3 and the memory cells of the second memory bank through sub bit line SB 4 ′. That is, the first terminals of the memory cells MA 1 , MB 1 , and MC 1 , and the second terminals of the memory cells MA 2 , MB 2 , and MC 2 are coupled to the metal bit line S 1 through sub bit line SB 1 . The first terminals of the memory cells MA 2 , MB 2 , and MC 2 , and the second terminals of the memory cells MA 3 , MB 3 , and MC 3 are coupled downward to another metal bit line (not shown) through sub bit line SB 2 . The first terminals of the memory cells MA 3 , MB 3 , and MC 3 , and the second terminals of the memory cells MA 4 , MB 4 , and MC 4 are coupled to the metal bit line S 1 through sub bit line SB 3 . The first terminals of the memory cells MA 4 , MB 4 , and MC 4 are coupled downward to another metal bit line (not shown) through sub bit line SB 4 .

Similarly, the first terminals of the memory cells MA 1 ′, MB 1 ′, and MC 1 ′, and the second terminals of the memory cells MA 2 ′, MB 2 ′, and MC 2 ′ are coupled upward to another metal bit line (not shown) through sub bit line SB 1 ′. The first terminals of the memory cells MA 2 ′, MB 2 ′, and MC 2 ′, and the second terminals of the memory cells MA 3 ′, MB 3 ′, and MC 3 ′ are coupled downward to the metal bit line S 1 through sub bit line SB 2 ′. The first terminals of the memory cells MA 3 ′, MB 3 ′, and MC 3 ′, and the second terminals of the memory cells MA 4 ′, MB 4 ′, and MC 4 ′ are coupled upward to another metal bit line (not shown) through sub bit line SB 3 ′. The first terminals of the memory cells MA 4 ′, MB 4 ′, and MC 4 ′ are coupled to the metal bit line S 1 through sub bit line SB 4 ′. Thus, the metal bit line S 1 of the present invention through two inter-bank selection transistors (MS 0 and MS 1 ) with the contact 10 can coordinate with four buried diffusion regions (that is, SB 1 , SB 2 ′, SB 3 , and SB 4 ′).

Accordingly, the memory cells MA 1 , MA 2 , MB 1 , MB 2 , MC 1 , and MC 2 are individually selected by the inter-bank selection transistor MS 0 through the sub bit line SB 1 . The memory cells MA 2 ′, MA 3 ′, MB 2 ′, MB 3 ′, MC 2 ′, and MC 3 ′ are individually selected by the inter-bank selection transistor MS 0 through the sub bit line SB 2 ′. The memory cells MA 3 , MA 4 , MB 3 , MB 4 , MC 3 , and MC 4 are individually selected by the inter-bank selection transistor MS 1 through the sub bit line SB 3 . The memory cells MA 4 ′, MB 4 ′, and MC 4 ′ are individually selected by the inter-bank selection transistor MS 1 through the sub bit line SB 4 ′. All memory cells of other memory banks can be selected following the above configuration. There are many advantages on using the configuration. First, the bank selection lines are shared between adjacent two memory banks, which reduces the layout area of the bank selection area along vertical direction. Second, each contact is only connected to two inter-bank selection transistors instead of four ones of the prior art, which reduces the amount of the transistors. Furthermore, the configuration can be implemented by the general processes without extra specific ones. Third, the amount of transistors is reduced when current passes through, which can reduce work voltage. Fourth, the amount reduction of the metal contacts can reduce metal coupling.

The equivalent layout of the architecture of FIG. 2 is represented in FIG. 3 . The source and drain regions of the memory cells are formed by crossing word lines (WL 0 , WL 1 , WL 2 ) and buried diffusions (BDs). To connect buried diffusion in each bank to metal bit/ground lines (S 1 , S 2 , S 3 , G 1 , G 2 , G 3 , G 4 , etc.), bank selection lines BS 0 , BS 1 , BT 0 and BT 1 made of polysilicon go across these extended buried diffusions BD to form inter-bank selection transistors MS 0 , MS 1 of FIG. 2 , etc. Furthermore, metal bit lines S 1 , S 2 , S 3 and metal ground lines G 1 , G 2 , G 3 , G 4 , are also directly connected to the buried diffusions BD by contacts 10 . Thus, each metal bit line can be coupled to at least four buried diffusions BD through two inter-bank selection transistors.

The second embodiment shown in FIG. 4 illustrates the amount reduction of the contact number and pitch release of metal contact in the present invention. In the second embodiment, the metal bit line S 1 is coupled to two inter-bank selection transistors MS 0 and MS 5 , and four intra-bank selection transistors MS 1 , MS 2 , MS 3 , and MS 4 through a contact 20 . Similar to FIG. 2 , the gate terminal of inter-bank selection transistor MS 0 is connected to bank selection line BS 0 . The individual gate terminals of intra-bank selection transistors MS 1 and MS 2 are commonly connected to bank selection line BS 1 . The individual gate terminals of intra-bank selection transistors MS 3 and MS 4 are commonly connected to bank selection line BS 2 . The gate terminal of inter-bank selection transistor MS 5 is connected to bank selection line BS 3 . The metal bit line S 1 is connected to second or first terminals of the intra-bank and inter-bank selection transistors MS 0 to MS 5 . In the embodiment, the individual first terminals of inter-bank selection transistors MS 0 , intra-bank selection transistors MS 1 , MS 3 , and the individual second terminals of intra-bank selection transistors MS 2 , MS 4 , inter-bank selection transistor MS 5 , are commonly connected to the metal bit line S 1 .

The second terminal of inter-bank selection transistor MS 0 is commonly connected to both the memory cells of one memory bank through a sub bit line SB 1 and the memory cells of the other memory bank through sub bit line SB 1 ′. Similarly, the first terminal of the inter-bank selection transistor MS 5 is commonly connected to the memory cells of the one memory bank through a sub bit line SB 7 and the memory cells of the other memory bank through sub bit line SB 7 ′. That is, the first terminals of the memory cells MA 1 , MB 1 , and MC 1 , and the second terminals of the memory cells MA 2 , MB 2 , and MC 2 are coupled to the metal bit line S 1 with the inter-bank selection transistor MS 0 through sub bit line SB 1 . The first terminals of the memory cells MA 1 ′, MB 1 ′, and MC 1 ′, and the second terminals of the memory cells MA 2 ′, MB 2 ′, and MC 2 ′ are coupled to the metal bit line S 1 with the inter-bank selection transistor MS 0 through sub bit line SB 1 ′. The first terminals of the memory cells MA 7 , MB 7 , and MC 7 , and the second terminals of the memory cells MA 8 , MB 8 , and MC 8 are coupled to the metal bit line S 1 with the inter-bank selection transistor MS 5 through sub bit line SB 7 . The first terminals of the memory cells MA 7 ′, MB 7 ′, and MC 7 ′, and the second terminals of the memory cells MA 8 ′, MB 8 ′, and MC 8 ′ are coupled to the metal bit line S 1 with the inter-bank selection transistor MS 5 through sub bit line SB 7 ′.

On the other hand, the intra-bank selection transistor MS 1 , MS 2 , MS 3 , or MS 4 is coupled to the memory cells of one memory bank. In the embodiment, the first terminals of the memory cells MA 2 , MB 2 , and MC 2 , and the second terminals of the memory cells MA 3 , MB 3 , and MC 3 are coupled downward to another metal bit line (not shown) through sub bit line SB 2 . The first terminals of the memory cells MA 3 , MB 3 , and MC 3 , and the second terminals of the memory cells MA 4 , MB 4 , and MC 4 are coupled to the metal bit line S 1 with the intra-bank selection transistor MS 1 through sub bit line SB 3 . The first terminals of the memory cells MA 4 , MB 4 , and MC 4 , and the second terminals of the memory cells MA 5 , MB 5 , MC 5 are coupled downward to another metal bit line (not shown) through sub bit line SB 4 . The first terminals of the memory cells MA 5 , MB 5 , and MC 5 , and the second terminals of the memory cells MA 6 , MB 6 , and MC 6 are coupled to the metal bit line S 1 with the intra-bank selection transistor MS 3 through sub bit line SB 5 . The first terminals of the memory cells MA 6 , MB 6 , and MC 6 and the second terminals of the memory cells MA 7 , MB 7 , MC 7 are coupled downward to another metal bit line (not shown) through sub bit line SB 6 .

Similarly, the first terminals of the memory cells MA 2 ′, MB 2 ′, and MC 2 ′, and the second terminals of the memory cells MA 3 ′, MB 3 ′, and MC 3 ′ are coupled upward to another metal bit line (not shown) through sub bit line SB 2 ′. The first terminals of the memory cells MA 3 ′, MB 3 ′, and MC 3 ′, and the second terminals of the memory cells MA 4 ′, MB 4 ′, and MC 4 ′ are coupled to the metal bit line S 1 with the intra-bank selection transistor MS 2 through sub bit line SB 3 ′. The first terminals of the memory cells MA 4 ′, MB 4 ′, and MC 4 ′, and the second terminals of the memory cells MA 5 ′, MB 5 ′, MC 5 ′ are coupled upward to another metal bit line (not shown) through sub bit line SB 4 ′. The first terminals of the memory cells MA 5 ′, MB 5 ′, and MC 5 ′, and the second terminals of the memory cells MA 6 ′, MB 6 ′, and MC 6 ′ are coupled to the metal bit line S 1 with the intra-bank selection transistor MS 4 through sub bit line SB 5 ′. The first terminals of the memory cells MA 6 ′, MB 6 ′, and MC 6 ′ and the second terminals of the memory cells MA 7 ′, MB 7 ′, MC 7 ′ are coupled upward to another metal bit line (not shown) through sub bit line SB 6 ′.

Accordingly, the memory cells MA 1 , MA 2 , MB 1 , MB 2 , MC 1 , and MC 2 are individually selected by the inter-bank selection transistor MS 0 through the sub bit line SB 1 . The memory cells MA 1 ′, MA 2 ′, MB 1 ′, MB 2 ′, MC 1 ′, and MC 2 ′ are individually selected by the inter-bank selection transistor MS 0 through the sub bit line SB 1 ′. The memory cells MA 3 , MA 4 , MB 3 , MB 4 , MC 3 , and MC 4 are individually selected by the intra-bank selection transistor MS 1 through the sub bit line SB 3 . The memory cells MA 3 ′, MA 4 ′, MB 3 ′, MB 4 ′, MC 3 ′, and MC 4 ′ are individually selected by the intra-bank selection transistor MS 2 through the sub bit line SB 3 ′. The memory cells MA 5 , MA 6 , MB 5 , MB 6 , MC 5 , and MC 6 are individually selected by the intra-bank selection transistor MS 3 through the sub bit line SB 5 . The memory cells MA 5 ′, MA 6 ′, MB 5 ′, MB 6 ′, MC 5 ′, and MC 6 ′ are individually selected by the intra-bank selection transistor MS 4 through the sub bit line SB 5 ′. The memory cells MA 7 , MA 8 , MB 7 , MB 8 , MC 7 , and MC 8 are individually selected by the inter-bank selection transistor MS 5 through the sub bit line SB 7 . The memory cells MA 7 ′, MA 8 ′, MB 7 ′, MB 8 ′, MC 7 ′, and MC 8 ′ are individually selected by the inter-bank selection transistor MS 5 through the sub bit line SB 7 ′. All memory cells of other memory banks can be selected following the above configuration. In the embodiment, the bank selection features one bit line or one ground line connected to every 8 sub bit line of the array. Also, in the embodiment, the layout structure features one metal contact for every 8 buried diffusions (sub bit lines), which is half amount of metal contacts compared with one in a conventional layout design. The release of metal pitch makes it easy in flexible layout design and is good for shrinking down to the next generation. The released metal line pitch also reduces the effect of metal coupling among them, and it will be healthy for reading data.

The equivalent layout of the architecture of FIG. 4 is represented in FIG. 5 . Each contact 20 is connected to the source or drain regions of the inter/intra-bank selection transistors, for example, MS 0 to MS 5 of FIG. 4 . The source and drain regions of the memory cells are formed by crossing word lines (WL 0 , WL 1 , WL 2 ) and buried diffusions (BDs). To connect buried diffusion in each memory bank to metal bit/ground lines (S 1 , S 2 , G 1 , G 2 , etc.), bank selection lines BS 0 to BS 3 , BT 0 to BT 3 made of polysilicon go across these extended buried diffusions BD to form inter/intra-bank selection transistors MS 0 to MS 5 of FIG. 4 , etc. Furthermore, metal bit lines S 1 , S 2 , and metal ground lines G 1 , G 2 , are also directly connected to the buried diffusions BD by contacts 20 .

To be specific, the bank selection transistors in the first embodiment can be combined with one in the second embodiment for design requirement. For example, in FIG. 2 , while the buried diffusion SB 1 and SB 3 are coupled to the bank selection transistors of the first embodiment, the buried diffusion SB 2 and SB 4 are coupled to the bank selection transistors of the second embodiment (not shown as figure).

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.