Adjustable frequency oscillator with programmable calibrating circuit and related system and method

This application claims priority from Italian patent application No. TO2002A 000288, filed Apr. 2, 2002, which is incorporated herein by reference.

The present invention relates generally to an adjustable frequency oscillator circuit and to a corresponding calibration method.

As is known, digital oscillator circuits are very often based upon astable circuits comprising an odd number of logic inverters, connected to one another so as to form a loop, and a plurality of capacitive elements, inserted between the outputs of respective inverters and a reference potential line, for example, ground. Such astable circuits have a natural frequency that depends upon various factors, among which, in particular, the switching voltages of the inverters, the currents supplied by the inverters themselves, and the capacitance of the individual capacitive elements.

Of course, it is of extreme importance that the natural frequency of an oscillator should be equal or at least close to a nominal frequency fixed in the design stage and defined on the basis of particular combinations of the factors listed above.

The fabrication processes currently used are however affected by a margin of imprecision which cannot be eliminated and, consequently, the characteristics of the active and passive components made may differ significantly with respect to the design values. On account of such imprecisions, the switching speed of the individual inverters is different from the one envisaged and consequently also the natural frequency of the oscillator is influenced by the process parameters and can show unacceptable deviations with respect to the nominal frequency.

Currently, it is known in the art to use compensation circuits which enable control of operation of the oscillator so as to modify the natural frequency of oscillation and reduce the sensitivity with respect to the variations of the process parameters.

However, the use of compensation circuits also entails some drawbacks. In fact, even if the imprecisions in the natural frequency of the oscillator caused by the process variations can be in effect reduced, on the other hand, the dependency upon other potentially variable quantities such as supply voltage and temperature increases considerably. Hence, in practice, known compensation circuits introduce factors of instability which render the oscillation frequency in any case far from precise.

In addition, oscillators provided with compensation circuits are rather complex and disadvantageously have large overall dimensions.

One embodiment of the present invention provides an adjustable frequency digital oscillator which is free from the drawbacks described above.

For a better understanding of the present invention, some embodiments thereof are now described, purely by way of non-limiting example and with reference to the annexed drawings, in which:

FIG. 1 is a circuit diagram of an oscillator circuit according to a first embodiment of the present invention;

FIG. 2 is a more detailed circuit diagram of a part of the oscillator circuit of FIG. 1 ;

FIG. 3 shows the plots of quantities which refer to the oscillator circuit of FIG. 1 ; and

FIG. 4 is a circuit diagram of an oscillator circuit according to a different embodiment of the present invention.

With reference to FIG. 1 , the reference number 1 designates, as a whole, an adjustable frequency oscillator comprising an astable circuit 2 , a calibration circuit 3 , a counter 4 , and a control unit 5 .

The astable circuit 2 comprises an odd number of current limited CMOS inverters 7 (five, in the example shown), connected to one another so as to form a loop, and a plurality of capacitors 8 , each of which is connected between ground and the output terminal of a respective CMOS inverter 7 . In this case, in particular, there are four capacitors 8 . In addition, the output terminal of one of the CMOS inverters 7 is connected to an output 10 of the oscillator 1 through two output inverters 11 in series. In particular, the output 10 supplies an oscillating output signal CK, as is explained hereinafter.

The calibration circuit 3 comprises a reference branch 13 , a programming circuit 14 for programming the reference branch 13 , and a limiting stage 15 .

In greater detail, the reference branch 13 comprises a programmable nonvolatile memory cell 17 , for example, of an EEPROM or Flash type, a voltage regulator 18 and a load transistor 19 . The cell 17 has its source terminal connected to ground and its gate terminal and drain terminal connected, respectively, to a first programming terminal 14 a and a second programming terminal 14 b of the programming circuit 14 . In addition, the gate terminal of the cell 17 is connected to a regulation terminal 18 a of the voltage regulator 18 , which supplies a regulated gate voltage V G . The load transistor 19 , of a PMOS type, has its source terminal connected to a supply line 24 , which supplies a supply voltage V DD , and is diode-connected, i.e., its gate and drain terminals are directly connected together. In addition, the drain terminals of the cell 17 and of the load transistor 19 are connected to one another via a switch 20 and a cascode stage 21 , comprising a cascode transistor 22 and a cascode inverter 23 , connected between the drain terminal and gate terminal of the cascode transistor 22 . The switch 20 is here a NMOS transistor having its gate terminal connected to a first control terminal 14 c of the programming circuit 14 . In practice, the cell 17 is a programmable constant current generator, which supplies a reference current I R , the value of which can be selected in a continuous range of current values. In addition, the reference current I R itself flows also in the load transistor 19 .

The programming circuit 14 is a circuit for programming nonvolatile memory cells, of a known type, and has a second control terminal 14 d connected to an input of the voltage regulator 17 , and a programming input 14 e connected to a programming output of the control unit 5 , which supplies a programming signal P. In particular, during a step of calibration of the oscillator 1 , the programming circuit 14 supplies to the gate and drain terminals of the cell 17 respective programming voltages so as to bring a threshold voltage V T of the cell 17 itself to a value correlated to the programming signal P.

The limiting stage 15 comprises a plurality of limiting transistors 25 , of a PMOS type, connected to the load transistor 19 in a current mirror configuration with a mirror ratio, for example, of unity. In particular, the limiting transistors 25 , which are equal in number to the number of the CMOS inverters of the astable circuit 2 , all have their source terminals connected to the supply line 24 and their gate terminals 25 a connected to the gate terminal of the load transistor 19 . In addition, each limiting transistor 25 has its drain terminal connected to a limitation terminal 7 a of a respective CMOS inverter 7 . Consequently, each of the limiting transistors 25 is able to supply to the respective CMOS inverter 7 a limited current I L equal to the reference current I R .

FIG. 2 shows in detail one of the CMOS inverters 7 , together with the capacitive element 8 and the limiting transistor 25 associated thereto. The CMOS inverter 7 comprises a first transistor 27 , of an NMOS type, and a second transistor 28 , of a PMOS type, the said transistors having gate terminals in common, so as to form the input stage of the CMOS inverter 7 , and drain terminals also in common, so as to form the output terminal of the CMOS inverter 7 . In addition, the first transistor 27 has its source terminal connected to ground, while the source terminal of the second transistor 28 forms the limitation terminal 7 a of the CMOS inverter 7 . Clearly, when the second transistor 28 conducts, the maximum current I M which can be delivered by the CMOS inverter 7 is equal to the limited current I L supplied by the respective limiting transistor 25 .

With reference once again to FIG. 1 , the counter 4 is a counter of a known type, for instance, an 8-bit counter, and has a count input connected to the output 10 of the oscillator 1 , an activation input 4 a connected to an activation output of the control unit 5 , which supplies an activation logic signal START, and a plurality of outputs 4 b (here eight). In particular, the outputs 4 b of the counter 4 are connected to respective inputs of the control unit 5 and supply a count signal NC, which represents the number of counts carried out by the counter 4 after its activation.

The control unit 5 is of a known type and, in particular, in the step of calibration of the oscillator 1 , activates the counter 4 , setting the activation signal START to an activation level for a predetermined time interval; compares the count signal NC with a nominal number of counts, which is stored in a register of the control unit 5 (not illustrated herein) and is correlated to a nominal frequency of the oscillator 1 ; and generates the programming signal P, which is correlated to the difference between the count signal NC and the nominal number of counts.

Operation of the oscillator 1 is described hereinafter. The astable circuit 2 oscillates with a natural frequency which depends upon the number of CMOS inverters 7 and of capacitive elements 8 present, as well as upon the maximum current I M which can be delivered by the CMOS inverters 7 , their switching voltages V S , and the capacitances of the capacitive elements 8 . In practice, a switching signal SW cyclically circulates through the astable circuit 2 and propagates with a speed determined by the switching speed of the individual CMOS inverters 7 . The switching speed of the CMOS inverters 7 depends, in turn, upon the rapidity with which the CMOS inverters 7 themselves are able to charge the capacitive elements 8 connected to the respective output terminals, i.e., it depends upon the maximum current I M that can be delivered, which is equal to the limited current I L supplied by the limiting transistors 25 .

By way of example, FIG. 3 illustrates plots of the voltage at output from one of the CMOS inverters 7 , in the presence of a first value I M ′ and a second value I M ″ of the maximum current I M that can be delivered (in this case, I M ″>I M ′). FIG. 3 further shows corresponding switching intervals T′, T″, which represent, in each of the two cases, the time necessary for the voltage at output from the CMOS inverter 7 in question to reach the switching voltage V S of the CMOS inverter 7 set immediately downstream.

As previously mentioned, the limited current I L is moreover equal to the reference current I R which flows in the cell 17 and in the load transistor 19 . More precisely, the cell 17 , previously programmed in order to have a nominal threshold voltage V T , is sent into conduction by the voltage regulator 18 and conducts the reference current I R , which is repeated through the load transistor 19 and the limiting transistors 25 , when the respective CMOS inverters 7 conduct.

In order to calibrate the oscillator 1 , the natural frequency is initially estimated using the counter 4 . Then, the programming state of the cell 17 is modified through the programming circuit 14 , according to the difference between the estimated natural frequency and the nominal frequency fixed in the design stage. In this way, the reference current I R which flows in the cell 17 , the limited currents I L supplied by the limiting transistors 25 , and the maximum current I M that can be delivered by the CMOS inverters 7 are also modified. Consequently, the switching speed of the CMOS inverters 7 and the propagation speed of the switching signal SW through the astable circuit 2 vary and, hence, the natural frequency of the oscillator 1 is modified.

In greater detail, the counter 4 is initially activated by the control unit 5 for an estimation interval of predetermined duration. During the said estimation interval, the output signal CK, which oscillates at the natural frequency of the oscillator 1 , is supplied on the output 10 and fed to the count input of the counter 4 . Consequently, the count signal NC of the counter 4 is incremented by one unit at each cycle of the output signal CK, for example, at the rising edges thereof.

At the end of the estimation interval, the control unit 5 compares the value of the count signal NC with the nominal number of counts stored, i.e., with the number of cycles of the output signal CK which the counter 4 is to detect in the estimation interval when the natural frequency of the oscillator 1 is equal to the nominal frequency. In addition, the control unit 5 supplies a value of the programming signal P correlated to the difference between the value of the count signal NC and the nominal number of counts. Then, the programming circuit 14 , in a conventional manner, de-activates the voltage regulator 18 and programs the cell 17 , by modifying its threshold voltage V T according to the value of the programming signal P. In particular, if the natural frequency of the oscillator 1 is less than the nominal frequency, the threshold voltage V T of the cell 17 is reduced, and hence the reference current I R flowing in the cell 17 increases. If, however, the natural frequency of the oscillator 1 is greater than the nominal frequency, the threshold voltage V T of the cell 17 is increased, so as to reduce the reference current I R . In this way, the maximum current I M that each CMOS inverter 7 can deliver for charging the respective capacitive element 8 is also modified. In fact, as has been explained previously, the said maximum current I M is equal to the limited current I L that each limiting transistor 25 is able to supply to the respective CMOS inverter 7 . On the other hand, since the limiting transistors 25 are connected as current mirrors with the load transistor 19 , the limited currents I L are in turn equal to the reference current I R imposed by the cell 17 .

In practice, if the estimated natural frequency is less than the nominal frequency, the maximum current I M that can be delivered by the CMOS inverters 7 is increased so as to render switching of the CMOS inverters 7 more rapid, and hence the natural frequency of the oscillator 1 increases. If, however, the estimated natural frequency is greater than the nominal frequency, the maximum current I M that can be delivered by the CMOS inverters 7 is reduced, and the natural frequency of the oscillator 1 decreases.

The calibration procedure described herein may possibly be repeated in an iterative manner, until the natural frequency of the oscillator 1 is substantially equal to the nominal frequency fixed in the design stage.

The above-described embodiment of the invention has the following advantages. In the first place, the natural frequency of the oscillator 1 can be calibrated with high precision. In fact, the maximum current that can be delivered by the CMOS inverters 7 , which, in practice, determines the natural frequency, can be regulated by acting upon the reference current I R , i.e., in the last resort, upon the threshold voltage V T of the cell 17 . On the other hand, the procedures and circuits for programming nonvolatile memory cells are well known and enable control of the threshold voltages of the cells in an extremely accurate way.

In addition, the oscillator 1 is free from any components that are particularly sensitive to the operating conditions, and hence the natural frequency is normally stable. However, if the oscillator 1 is used in operating conditions that are markedly variable and such as to affect the natural frequency, the calibration can easily be repeated at any moment.

A further advantage is provided by the fact that the oscillator 1 has contained overall dimensions.

According to another embodiment of the invention, illustrated in FIG. 4 , in which parts that are the same as those already shown are designated by the same reference numbers, an oscillator 30 is without the control unit 5 . Furthermore, the activation input 4 a and the outputs 4 b of the counter 4 and the input 14 e of the programming circuit 14 can be connected to an external control unit 31 by means of respective pins 32 . Clearly, in this case, calibration can be performed only when the oscillator 30 is connected to the external control unit 31 , for example, in the testing stage; on the other hand, calibration is in any case precise and, furthermore, the overall dimensions of the oscillator 30 are advantageously reduced to a considerable extent.

Referring to FIGS. 1 and 4 , the oscillator 1 , the oscillator 30 , or both the oscillators 1 and 30 , may be disposed in an integrated circuit (IC) such as a memory or a processor. Furthermore, such an IC may be included in an electronic system such as a computer system.

Finally, it is clear that modifications and variations may be made to the device described herein, without thereby departing from the scope of the present invention. For example, instead of the limiting transistors 25 of a PMOS type, NMOS transistors having drain terminals connected to the source terminals of respective first transistors 27 of the CMOS inverters 7 may be used.